Coaxial Through-Silicon Vias Thermal Stress Coupling Optimization Design Method

Abstract

This invention discloses a thermal-stress coupling optimization design method for coaxial through-silicon vias (TSVs), relating to the field of three-dimensional integrated circuit design technology. The method includes: constructing a finite element model of the coupled temperature and stress fields of the TSV; conducting finite element simulation experiments to obtain a database of design parameters and peak temperatures, and a database of design parameters and peak stresses for the TSV; constructing a peak temperature mapping model for the TSV; constructing a peak stress mapping model for the TSV; based on the peak temperature and peak stress mapping models, constructing a multi-objective optimization function for the peak temperature and peak stress of the TSV; and optimizing the design parameters of the TSV using an optimization algorithm based on the peak temperature and peak stress mapping models and the multi-objective optimization function. This application can improve the design efficiency of integrated circuits.

Description

Technical Field

[0001] This invention belongs to the field of three-dimensional integrated circuit design technology, specifically relating to a thermal stress coupling optimization design method for coaxial through-silicon vias. Background Technology

[0002] The rapidly developing information world cannot function without integrated circuits, which form its cornerstone. The level of development of integrated circuits has become one of the important indicators for measuring a country's industrial competitiveness and comprehensive national strength. Among them, three-dimensional integrated circuits have advantages that two-dimensional planar circuits cannot match, such as optimizing system performance and improving chip integration. They represent a new approach for the further development of integrated circuits and the realization of System-on-Chips (SoCs).

[0003] In the existing technology, the manufacturing technology and design methods of three-dimensional integrated circuits rely more on the trial and error of engineers and the repeated iterative simulation verification of software. Engineers continuously adjust the structural parameters of devices in integrated circuits to optimize the performance of the circuit. This design method not only prolongs the R&D cycle of integrated circuit chips, but also increases the R&D cost.

[0004] Therefore, there is an urgent need to improve the shortcomings of existing technologies, such as long R&D cycles and high R&D costs for integrated circuit chips. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a thermal stress coupling optimization design method for coaxial through-silicon vias. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, this application provides a thermal stress coupling optimization design method for coaxial through-silicon vias, including:

[0007] A finite element model of the temperature field and stress field coupled together is constructed for a coaxial through-silicon via.

[0008] Based on the orthogonal design principle, finite element simulation experiments were conducted to obtain the design parameters and peak temperature database of coaxial through-silicon vias, and at the same time, the design parameters and peak stress database of coaxial through-silicon vias were obtained.

[0009] Based on the design parameters and peak temperature database, a peak temperature mapping model for coaxial through-silicon vias (TSVs) is constructed; based on the design parameters and peak stress database, a peak stress mapping model for coaxial TSVs is constructed.

[0010] Based on the peak temperature mapping model and the peak stress mapping model, a multi-objective optimization function for the peak temperature and peak stress of coaxial through-silicon vias is constructed.

[0011] Based on the peak temperature mapping model and the peak stress mapping model, as well as the multi-objective optimization function, the design parameters of coaxial through-silicon vias are optimized using an optimization algorithm.

[0012] Optionally, the coaxial through-silicon via includes a copper pillar and a copper ring surrounding the copper pillar. A first insulating layer is disposed around the copper pillar, a second insulating layer is disposed around the inner sidewall of the copper ring, and a third insulating layer is disposed around the outer sidewall of the copper ring. A dielectric layer is disposed between the first insulating layer and the second insulating layer.

[0013] In the temperature field coupled finite element model and stress field finite element model of the coaxial through-silicon via, the current source is located directly above the copper pillar, and the current propagates along the extension direction of the coaxial through-silicon via.

[0014] Optionally, the design parameters include the copper pillar radius, dielectric layer thickness, copper ring thickness, first insulating layer thickness, second insulating layer thickness, and third insulating layer thickness.

[0015] Optionally, the peak temperature of the coaxial through-silicon via includes the bulk peak temperature of the coaxial through-silicon via;

[0016] The peak stress of a coaxial through-silicon via includes the volume peak stress of the coaxial through-silicon via, the peak stress of the copper pillar, and the peak stress of the copper ring.

[0017] Optionally, the peak temperature mapping model and the peak stress mapping model are constructed using a support vector machine model;

[0018] Based on the support vector machine model, a volume peak temperature mapping model, a volume peak stress mapping model, a copper pillar peak stress mapping model, and a copper ring peak stress mapping model were constructed respectively.

[0019] Optionally, the expression for the peak volume temperature mapping model is:

[0020]

[0021]

[0022]

[0023] Where l represents the total number of training sample points, U i Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via (TSV), and TT be the volume peak temperature of the TSV. The first Lagrange multiplier for the peak volume temperature support vector machine model. C is the second Lagrange multiplier for the peak volume temperature support vector machine model. TT K(U,U) is the regularization parameter for the mapping model of coaxial through-silicon vias. i )TT UU is the kernel function of the support vector machine model for the volume peak temperature of coaxial through-silicon vias. i 2 for U and U i Euclidean distance, σ TT b is the width of the kernel function in the support vector machine model for the volume peak temperature of a coaxial through-silicon via. TT K represents the bias term of the support vector machine model for the volume peak temperature of a coaxial through-silicon via, where K is the kernel, i.e., the simplified expression of the kernel function.

[0024] The expression for the volume peak stress mapping model is:

[0025]

[0026]

[0027]

[0028] Where l represents the total number of training sample points, U i Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via, and TS be the volume peak stress of the coaxial through-silicon via. The first Lagrange multiplier is the volume peak stress support vector machine model for coaxial through-silicon vias. C is the second Lagrange multiplier for the volume peak stress support vector machine model of a coaxial through-silicon via. TS K(U,U) is the regularization parameter for the volume peak stress support vector machine model of a coaxial through-silicon via. i ) TS UU is the kernel function for the support vector machine model of the peak volume stress of a coaxial through-silicon via. i 2 for U and U i Euclidean distance, σ TS b is the width of the kernel function in the support vector machine model of the volume peak stress of a coaxial through-silicon via. TS K represents the bias term of the support vector machine model for the peak volume stress of a coaxial through-silicon via, where K is the kernel, i.e., the simplified expression of the kernel function.

[0029] The expression for the peak stress mapping model of the copper pillar is:

[0030]

[0031]

[0032]

[0033] Where l represents the total number of training sample points, Ui Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via (TSV), CS be the peak stress of the copper pillar in the TSV, and α be the vector representing the i-th training sample. i CS α is the first Lagrange multiplier for the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias. i *CS C is the second Lagrange multiplier for the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias. CS K(U,U) is the regularization parameter for the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias. i ) CS For the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias, ||UU i || 2 for U and U i Euclidean distance, σ CS b is the width of the kernel function in the peak stress support vector machine model of a copper pillar with a coaxial through-silicon via. CS K represents the bias term of the peak stress support vector machine model for a copper pillar with a coaxial through-silicon via, where K is the kernel, i.e., the simplified expression of the kernel function.

[0034] The expression for the peak stress mapping model of the copper ring is:

[0035]

[0036]

[0037]

[0038] Where l represents the total number of training sample points, U i Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via, and RS be the peak stress of the copper ring in the coaxial through-silicon via. The first Lagrange multiplier for the support vector machine model of coaxial through-silicon via (TSV) is... For the support vector machine model of coaxial through-silicon vias, the second Lagrange multiplier is K(U,U). i ) RS For the kernel function of the support vector machine model of coaxial through-silicon vias, C RS For the support vector machine model of coaxial through-silicon vias, ||UU i || 2 for U and U i Euclidean distance, σ RS b is the width of the kernel function in the support vector machine model of a coaxial through-silicon via. RSFor the support vector machine model of coaxial through-silicon via, K is the kernel, i.e., the simplified expression of the kernel function.

[0039] Optionally, the expression for the multi-objective optimization function is:

[0040] J = α(TT - TT) des ) 2 +β(TS-TS des ) 2 +γ(CS-CS des ) 2 +λ(RS-RS des ) 2 ;

[0041] Where J is the multi-objective optimization criterion for the peak temperature of the coaxial through-silicon via (TSV), TT is the bulk peak temperature of the TSV, TS is the bulk peak stress of the TSV, CS is the peak stress of the copper pillar in the TSV, RS is the peak stress of the copper ring in the TSV, and TT des For the desired bulk peak temperature of the coaxial through-silicon via, TS des For the desired bulk peak stress of the coaxial through-silicon via, CS des For the desired peak stress of the copper pillar in a coaxial through-silicon via, RS des Let α be the desired peak stress of the copper ring in the coaxial through-silicon via (TSV), β be the peak volume temperature of the TSV, γ be the peak volume stress of the TSV, and λ be the optimized weighting coefficient for the peak stress of the copper ring in the TSV.

[0042] Optionally, the process of optimizing the design parameters of coaxial through-silicon vias using optimization algorithms includes:

[0043] Initialize the parameters of the particle swarm optimization algorithm;

[0044] Based on the design parameters, the peak temperature and peak pressure are predicted using the peak temperature mapping model and the peak stress mapping model.

[0045] Based on the peak temperature and the peak pressure, and based on a multi-objective optimization function, the design parameters of the coaxial through-silicon via are optimized using a particle swarm optimization algorithm.

[0046] Determine whether the optimal design parameters have been obtained. If not, continue to optimize the design parameters; if so, the optimization is complete.

[0047] The beneficial effects of this invention are:

[0048] This invention provides a thermal stress coupling optimization design method for coaxial through-silicon vias (TSVs). Addressing the challenges of excessively long development cycles and over-reliance on experience in process parameter design for existing 3D integrated circuit manufacturing, this invention proposes an optimization strategy for TSV design parameters in 3D integrated circuits. Utilizing a particle swarm optimization algorithm, the design parameters of TSVs in 3D integrated circuits can be optimized efficiently, leading to the determination of 3D integrated circuit device design dimensions. This shortens the development cycle of integrated circuit chips, reduces development costs, and improves integrated circuit design efficiency.

[0049] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0050] Figure 1 This is a flowchart of a thermal stress coupling optimization design method for coaxial through-silicon vias provided in an embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram of a structure for the volume peak temperature of a coaxial through-silicon via provided in an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of a structure for the volume peak stress of a coaxial through-silicon via provided in an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of a structure for the peak stress of a copper pillar with a coaxial through-silicon via provided in an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of a copper ring with peak stress in a coaxial through-silicon via provided in an embodiment of the present invention. Detailed Implementation

[0055] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0056] Please see Figure 1 , Figure 1 This is a flowchart of a coaxial through-silicon via thermal stress coupling optimization design method provided in an embodiment of the present invention. The coaxial through-silicon via thermal stress coupling optimization design method provided in this application includes:

[0057] S101. Construct a finite element model of the temperature field and stress field coupling of a coaxial through-silicon via;

[0058] S102. Based on the orthogonal design principle, conduct finite element simulation experiments to obtain the design parameters and peak temperature database of the coaxial through-silicon via, and at the same time obtain the design parameters and peak stress database of the coaxial through-silicon via.

[0059] S103. Based on the design parameters and peak temperature database, construct a peak temperature mapping model for coaxial through-silicon vias; based on the design parameters and peak stress database, construct a peak stress mapping model for coaxial through-silicon vias.

[0060] S104. Based on the peak temperature mapping relationship model and the peak stress mapping relationship model, construct a multi-objective optimization function for the peak temperature and peak stress of coaxial through-silicon vias.

[0061] S105. Based on the peak temperature mapping model and peak stress mapping model, as well as the multi-objective optimization function, the design parameters of the coaxial through-silicon via are optimized using an optimization algorithm.

[0062] Specifically, through-silicon via (TSV) technology is a cutting-edge technology that enables interconnection between chips by creating vertical connections between chips and wafers. Chips generate heat during information transmission, and the large amount of heat generated can affect the performance of coaxial through-silicon vias, as well as the stress changes in the coaxial through-silicon vias.

[0063] This application addresses the challenges of excessively long R&D cycles and over-reliance on experience in the design of process parameters for existing 3D integrated circuit manufacturing. It proposes an optimization strategy for the design parameters of coaxial through-silicon vias (TSVs) in 3D integrated circuits. By utilizing particle swarm optimization (PSO) algorithm to optimize the design parameters of coaxial TSVs in 3D integrated circuits, the design dimensional parameters of 3D integrated circuit devices can be efficiently determined, thereby shortening the R&D cycle of integrated circuit chips, reducing R&D costs, and improving the efficiency of integrated circuit design.

[0064] Please see Figure 2 As shown, Figure 2 This is a schematic diagram of the volume peak temperature of a coaxial through-silicon via provided in an embodiment of the present invention. In an optional embodiment of this application, the coaxial through-silicon via includes a copper pillar 101 and a copper ring 102 disposed around the copper pillar 101. A first insulating layer 103 is disposed around the copper pillar 101, a second insulating layer 104 is disposed around the inner sidewall of the copper ring 102, a third insulating layer 105 is disposed around the outer sidewall of the copper ring 102, and a dielectric layer 106 is disposed between the first insulating layer 103 and the second insulating layer 104.

[0065] In the temperature field coupled finite element model and stress field finite element model of the coaxial through-silicon via, the current source is located directly above the copper pillar 101, and the current propagates along the extension direction of the coaxial through-silicon via.

[0066] It should be noted that the copper pillar 101 is a columnar body, with a first insulating layer 103 on its outer side wall, a dielectric layer 106 on the outer side of the first insulating layer 103, a second insulating layer 104 on the outer side of the dielectric layer 106, a copper ring 102 on the outer side of the second insulating layer 104, and a third insulating layer 105 on the outer side of the copper ring 102. It can also be understood that the outer side of the copper pillar 101 is sequentially provided with the first insulating layer 103, the dielectric layer 106, the second insulating layer 104, the copper ring 102, and the third insulating layer 105.

[0067] In one optional embodiment of this application, the design parameters include the copper pillar radius, dielectric layer thickness, copper ring thickness, first insulating layer thickness, second insulating layer thickness, and third insulating layer thickness.

[0068] It should be noted that the thickness of the dielectric layer, the copper ring, the first insulating layer, the second insulating layer, and the third insulating layer are all circumferential thicknesses of the copper pillar.

[0069] Please see Figure 3 As shown~ Figure 5 As shown, Figure 3 This is a schematic diagram of a structure for the volume peak stress of a coaxial through-silicon via provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a structure for the peak stress of a copper pillar with a coaxial through-silicon via provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the peak stress of the copper ring in a coaxial through-silicon via provided in an embodiment of the present invention. In an optional embodiment of this application, the peak temperature of the coaxial through-silicon via includes the volume peak temperature of the coaxial through-silicon via.

[0070] The peak stress of a coaxial through-silicon via includes the volume peak stress of the coaxial through-silicon via, the peak stress of the copper pillar, and the peak stress of the copper ring.

[0071] In one optional embodiment of this application, the peak temperature mapping model and the peak stress mapping model are constructed using a support vector machine model;

[0072] Based on the support vector machine model, a volume peak temperature mapping model, a volume peak stress mapping model, a copper pillar peak stress mapping model, and a copper ring peak stress mapping model were constructed respectively.

[0073] In one optional embodiment of this application, the support vector machines that construct each mapping relationship model are obtained by using COMSOL software in combination with orthogonal design methods to obtain simulation experimental data.

[0074] In an optional embodiment of this application, the expression for the volume peak temperature mapping model is:

[0075]

[0076]

[0077]

[0078] Where l represents the total number of training sample points, U i Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via (TSV), and TT be the volume peak temperature of the TSV. The first Lagrange multiplier for the peak volume temperature support vector machine model. C is the second Lagrange multiplier for the peak volume temperature support vector machine model. TT K(U,U) is the regularization parameter for the mapping model of coaxial through-silicon vias. i ) TT The kernel function for the support vector machine model of the volume peak temperature of a coaxial through-silicon via (TSV), ||UU i || 2 for U and U i Euclidean distance, σ TT The width of the kernel function for the support vector machine model of the volume peak temperature of a coaxial through-silicon via (TSV) can optionally be σ. TT =10, b TT For the bias term of the support vector machine model of the volume peak temperature of coaxial through-silicon vias, optionally, b TT = -0.7800, where K stands for Kernel, i.e., the simplified expression of the kernel function;

[0079] The expression for the volume peak stress mapping model is:

[0080]

[0081]

[0082]

[0083] Where l represents the total number of training sample points, U i Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via, TS be the peak volume stress of the coaxial through-silicon via, and α be the vector representing the vector representing the i-th training sample. i TS α is the first Lagrange multiplier for the volume peak stress support vector machine model of a coaxial through-silicon via. i *TS C is the second Lagrange multiplier for the volume peak stress support vector machine model of a coaxial through-silicon via. TS For the regularization parameters of the support vector machine model of the volume peak stress of coaxial through-silicon vias, C can optionally be used. TS =10000, K(U,U) i )TS For the support vector machine model of the peak volume stress of a coaxial through-silicon via, ||UU i || 2 for U and U i Euclidean distance, σ TS The width of the kernel function for the support vector machine model of the volume peak stress of a coaxial through-silicon via (TSV) can optionally be σ. TS =10, b TS For the bias term of the support vector machine model of the volume peak stress of coaxial through-silicon vias, optionally, b TS = -0.8333, where K stands for Kernel, i.e., the simplified expression of the kernel function;

[0084] The expression for the peak stress mapping model of the copper pillar 101 is as follows:

[0085]

[0086]

[0087]

[0088] Where l represents the total number of training sample points, U i Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via (TSV), CS be the peak stress of the copper pillar in the TSV, and α be the vector representing the i-th training sample. i CS α is the first Lagrange multiplier for the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias. i *CS C is the second Lagrange multiplier for the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias. CS C represents the regularization parameter for the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias. CS =10000, K(U,U) i ) CS For the peak stress support vector machine model of a copper pillar with coaxial through-silicon vias, ||UU i || 2 for U and U i Euclidean distance, σ CS The width of the kernel function for the peak stress support vector machine model of a copper pillar with a coaxial through-silicon via can optionally be σ. CS =10, b CS b is the bias term in the support vector machine model of the peak stress of a copper pillar with a coaxial through-silicon via. CS = -0.1560, where K stands for Kernel, i.e., the simplified expression of the kernel function;

[0089] The expression for the peak stress mapping model of the copper ring is:

[0090]

[0091]

[0092]

[0093] Where l represents the total number of training sample points, U i Let be the vector representing the i-th training sample, U be the design parameters of the coaxial through-silicon via (TSV), RS be the peak stress of the copper ring in the TSV, and α be the vector representing the i-th training sample. i RS α is the first Lagrange multiplier for the support vector machine model of coaxial through-silicon vias. i *RS For the support vector machine model of coaxial through-silicon vias, the second Lagrange multiplier is K(U,U). i ) RS For the kernel function of the support vector machine model of coaxial through-silicon vias, C RS For the regularization parameters of the support vector machine model of coaxial through-silicon vias, C can optionally be used. RS =10000, ||UU i || 2 for U and U i Euclidean distance, σ RS The width of the kernel function for the support vector machine model of a coaxial through-silicon via (TSV) can optionally be σ. RS =10, b RS For the bias term of the support vector machine model of coaxial through-silicon vias, optionally, b RS =0.3138, where K stands for Kernel, i.e., the simplified expression of the kernel function.

[0094] In one optional embodiment of this application, the expression for the multi-objective optimization function is:

[0095] J = α(TT - TT) des ) 2 +β(TS-TS des ) 2 +γ(CS-CS des ) 2 +λ(RS-RS des ) 2 ;

[0096] Where J is the multi-objective optimization criterion for the peak temperature of the coaxial through-silicon via (TSV), TT is the bulk peak temperature of the TSV, TS is the bulk peak stress of the TSV, CS is the peak stress of the copper pillar in the TSV, RS is the peak stress of the copper ring in the TSV, and TT desFor the desired bulk peak temperature of the coaxial through-silicon via, TT des =325K, TS des For the desired bulk peak stress of the coaxial through-silicon via, optionally, TS des =85MPa, CS des For the desired peak stress of the copper pillar in the coaxial through-silicon via, optionally, CS des =25MPa, RS des For the desired peak stress of the copper ring in the coaxial through-silicon via, optionally, RS des =5 MPa, α is the volume peak temperature of the coaxial through-silicon via, β is the volume peak stress of the coaxial through-silicon via, γ is the peak stress of the copper pillar of the coaxial through-silicon via, and λ is the optimized weighting coefficient of the peak stress of the copper ring of the coaxial through-silicon via.

[0097] In an optional embodiment of this application, the process of optimizing the design parameters of a coaxial through-silicon via using an optimization algorithm includes:

[0098] Initialize the parameters of the particle swarm optimization algorithm;

[0099] Based on the design parameters, the peak temperature and peak pressure are predicted using the peak temperature mapping model and the peak stress mapping model.

[0100] Based on peak temperature and peak pressure, and using a multi-objective optimization function, the design parameters of coaxial through-silicon vias are optimized using a particle swarm optimization algorithm.

[0101] Determine whether the optimal design parameters have been obtained. If not, continue to optimize the design parameters; if so, the optimization is complete.

[0102] Specifically, the Particle Swarm Optimization (PSO) algorithm finds the optimal solution through cooperation and information sharing among individuals in a swarm. The principle and mechanism of PSO are simple and easy to understand; it only updates velocity and position and compares fitness values ​​to ultimately calculate the global optimum. Furthermore, PSO has advantages such as simple structure, fast convergence speed, strong optimization ability, and easy implementation. Within the framework of PSO, this application proposes a simple and effective intelligent optimization method for the design parameters of coaxial through-silicon vias (TSVs) in three-dimensional integrated circuits, targeting the peak temperature and peak stress of TSVs. This provides an efficient method and approach for studying heat dissipation technology in three-dimensional integrated circuits.

[0103] In this embodiment, a particle swarm optimization algorithm with linearly decreasing inertia weights is used to optimize the design parameters of the coaxial TSV in a three-dimensional integrated circuit. The particle swarm optimization algorithm with linearly decreasing inertia weights can be described as follows:

[0104] v i (t+1)=wv i(t)+c1r1(p i -x i (t))+c2r2(p g -x i (t));

[0105] x i (t+1)=x i (t)+v i (t+1);

[0106]

[0107] Where, x i and v i Let p be the position vector and velocity vector of the i-th particle, respectively, w be the inertia weight, and p be the velocity vector. i For the local optimal position, p g For the globally optimal position, c1 and c2 are constants, r1 and r2 are random numbers between [0,1], and iter is the current iteration number. max w represents the maximum number of iterations. max and w min These represent the maximum and minimum values ​​of the inertia weight, respectively.

[0108] In this embodiment, the parameters for initializing the particle swarm optimization algorithm in the above process specifically include the parameters in Table 1 below.

[0109] Table 1

[0110]

[0111]

[0112] In one alternative embodiment of this application, please refer to Figures 2-5 , Figure 2 This is a flowchart of a coaxial through-silicon via (TSV) thermal stress coupling optimization design method provided in an embodiment of the present invention. Taking a finite element model of a single coaxial TSV embedded in a three-dimensional integrated circuit as an example, the material of the copper pillar 101 from the inside out is Cu, the material of the first insulating layer 103 is SiO2, the material of the dielectric layer 106 is Si, the material of the second insulating layer 104 is SiO2, the material of the copper ring 102 is Cu, the material of the third insulating layer 105 is SiO2, and the coaxial TSV is embedded in a substrate made of Si.

[0113] In this embodiment, the design parameters of the coaxial TSV in the three-dimensional integrated circuit were optimized according to the desired performance indicators using the aforementioned coaxial TSV thermal stress coupled particle swarm optimization design method. The optimized radius of the copper pillar 101, the thickness of the dielectric layer 106, the thickness of the copper ring 102, the thickness of the first insulating layer 103, the thickness of the second insulating layer 104, and the thickness of the third insulating layer 105 are 3.11 μm, 5.77 μm, 1.95 μm, 0.25 μm, 0.52 μm, and 0.61 μm, respectively. According to the optimized coaxial TSV design parameters, the peak volume temperature of the coaxial TSV is 325 K, the peak volume stress is 85 MPa, the peak stress of the copper pillar 101 is 25 MPa, and the peak stress of the copper ring 102 is 5 MPa. However, in actual manufacturing processes, the design dimensions of the coaxial TSV cannot be made so precise; therefore, the optimized coaxial TSV design parameters are approximated. After approximation, the radius of the copper pillar 101, the thickness of the dielectric layer 106, the thickness of the copper ring 102, the thickness of the first insulating layer 103, the thickness of the second insulating layer 104, and the thickness of the third insulating layer 105 are 3 μm, 6 μm, 2 μm, 0.25 μm, 0.50 μm, and 0.60 μm, respectively. The coaxial TSV in the 3D integrated circuit exhibits a volume peak temperature of 324.945 K, a volume peak stress of 84.7130 MPa, a peak stress of 34.1521 MPa for the copper pillar 101, and a peak stress of 5.46918 MPa, almost meeting the desired performance indicators. This demonstrates that the proposed method can effectively optimize the design parameters of the coaxial TSV in the 3D integrated circuit, obtaining a coaxial TSV with lower peak temperature and peak stress.

[0114] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A thermal stress coupling optimization design method for coaxial through-silicon vias, characterized in that, include: A finite element model of the temperature field and stress field coupled together is constructed for a coaxial through-silicon via. Based on the orthogonal design principle, finite element simulation experiments were conducted to obtain the design parameters and peak temperature database of coaxial through-silicon vias, and at the same time, the design parameters and peak stress database of coaxial through-silicon vias were obtained. Based on the design parameters and peak temperature database, a peak temperature mapping model for the coaxial through-silicon via is constructed. Based on the design parameters and peak stress database, a peak stress mapping relationship model for the coaxial through-silicon via is constructed. Based on the peak temperature mapping model and the peak stress mapping model, a multi-objective optimization function for the peak temperature and peak stress of the coaxial through-silicon via is constructed; the peak temperature mapping model and the peak stress mapping model are constructed using a support vector machine model. Based on the support vector machine model, a volume peak temperature mapping model, a volume peak stress mapping model, a copper pillar peak stress mapping model, and a copper ring peak stress mapping model are constructed respectively. Based on the peak temperature mapping model and the peak stress mapping model, as well as the multi-objective optimization function, the design parameters of the coaxial through-silicon via are optimized using the particle swarm optimization algorithm.

2. The coaxial through-silicon via thermal stress coupling optimization design method according to claim 1, characterized in that, The coaxial through-silicon via includes a copper pillar and a copper ring surrounding the copper pillar. A first insulating layer is disposed around the copper pillar, a second insulating layer is disposed around the inner sidewall of the copper ring, and a third insulating layer is disposed around the outer sidewall of the copper ring. A dielectric layer is disposed between the first insulating layer and the second insulating layer. In the temperature field coupled finite element model and stress field finite element model of the coaxial through-silicon via, the current source is located directly above the copper pillar, and the current propagates along the extension direction of the coaxial through-silicon via.

3. The coaxial through-silicon via thermal stress coupling optimization design method according to claim 2, characterized in that, The design parameters include the radius of the copper pillar, the thickness of the dielectric layer, the thickness of the copper ring, the thickness of the first insulating layer, the thickness of the second insulating layer, and the thickness of the third insulating layer.

4. The coaxial through-silicon via thermal stress coupling optimization design method according to claim 3, characterized in that, The peak temperature of the coaxial through-silicon via includes the volume peak temperature of the coaxial through-silicon via. The peak stress of the coaxial through-silicon via includes the volume peak stress of the coaxial through-silicon via, the peak stress of the copper pillar, and the peak stress of the copper ring.

5. The coaxial through-silicon via thermal stress coupling optimization design method according to claim 4, characterized in that, The expression for the volume peak temperature mapping model is as follows: ； ； ； in, For common use Group training sample points, For the first The vectors represented by the training samples. These are the design parameters for the coaxial through-silicon via. The bulk peak temperature of the coaxial through-silicon via is [temperature value missing]. The first Lagrange multiplier for the peak volume temperature support vector machine model is... The second Lagrange multiplier for the peak volume temperature support vector machine model is... The regularization parameters are those for the mapping model of the coaxial through-silicon via. Let be the kernel function of the support vector machine model for the volume peak temperature of the coaxial through-silicon via. for and European distance, The width of the kernel function in the support vector machine model for the volume peak temperature of the coaxial through-silicon via is given. This is the bias term of the support vector machine model for the volume peak temperature of the coaxial through-silicon via. For Kernel, that is, the simplified expression of kernel function; The expression for the volume peak stress mapping relationship model is as follows: ； ； ； in, For common use Group training sample points, For the first The vectors represented by the training samples. These are the design parameters for the coaxial through-silicon via. The peak volume stress of the coaxial through-silicon via is given. The first Lagrange multiplier is the volume peak stress support vector machine model of the coaxial through-silicon via. The second Lagrange multiplier is the volume peak stress support vector machine model of the coaxial through-silicon via. These are the regularization parameters for the volume peak stress support vector machine model of the coaxial through-silicon via. Let be the kernel function of the support vector machine model for the volume peak stress of the coaxial through-silicon via. for and Euclidean distance, The width of the kernel function in the support vector machine model of the volume peak stress of the coaxial through-silicon via is given. This refers to the bias term in the support vector machine model of the volume peak stress of the coaxial through-silicon via. For Kernel, that is, the simplified expression of kernel function; The expression for the peak stress mapping relationship model of the copper column is: ； ； ； in, For common use Group training sample points, For the first The vectors represented by the training samples. These are the design parameters for the coaxial through-silicon via. The peak stress of the copper pillar in the coaxial through-silicon via is given. The first Lagrange multiplier is the peak stress support vector machine model of the copper pillar with the coaxial through-silicon via. The second Lagrange multiplier is the peak stress support vector machine model of the copper pillar with the coaxial through-silicon via. These are the regularization parameters for the peak stress support vector machine model of the copper pillar with the coaxial through-silicon via. Let be the kernel function of the support vector machine model for the peak stress of the copper pillar in the coaxial through-silicon via. for and European distance, The width of the kernel function in the peak stress support vector machine model of the copper pillar with the coaxial through-silicon via is given. This refers to the bias term in the support vector machine model of the peak stress of the copper pillar with the coaxial through-silicon via. For Kernel, that is, the simplified expression of kernel function; The expression for the peak stress mapping relationship model of the copper ring is: ； ； ； in, For common use Group training sample points, For the first The vectors represented by the training samples. These are the design parameters for the coaxial through-silicon via. The peak stress of the copper ring in the coaxial through-silicon via is given. The first Lagrange multiplier of the support vector machine model for the coaxial through-silicon via is given. The second Lagrange multiplier of the support vector machine model for the coaxial through-silicon via is given. Let be the kernel function of the support vector machine model for the coaxial through-silicon via. These are the regularization parameters for the support vector machine model of the coaxial through-silicon via. for and Euclidean distance, The width of the kernel function of the support vector machine model for the coaxial through-silicon via is given. This refers to the bias term of the support vector machine model for the coaxial through-silicon via. For Kernel, that is, the simplified expression of kernel function.

6. The coaxial through-silicon via thermal stress coupling optimization design method according to claim 5, characterized in that, The expression for the multi-objective optimization function is: ； in, The multi-objective optimization criterion for the peak temperature of the coaxial through-silicon via is defined as follows: The bulk peak temperature of the coaxial through-silicon via is [temperature value missing]. The peak volume stress of the coaxial through-silicon via is given. The peak stress of the copper pillar in the coaxial through-silicon via is given. The peak stress of the copper ring in the coaxial through-silicon via is given. The desired bulk peak temperature of the coaxial through-silicon via (TSV) is... For the desired volume peak stress of the coaxial through-silicon via, For the desired peak stress of the copper pillar in the coaxial through-silicon via, For the desired peak stress of the copper ring in the coaxial through-silicon via, The bulk peak temperature of the coaxial through-silicon via is [temperature value missing]. The peak volume stress of the coaxial through-silicon via is given. The peak stress of the copper pillar in the coaxial through-silicon via is given. The optimized weighting coefficients are used for the peak stress of the copper ring in the coaxial through-silicon via.

7. The coaxial through-silicon via thermal stress coupling optimization design method according to claim 1, characterized in that, The process of optimizing the design parameters of the coaxial through-silicon via using the particle swarm optimization algorithm includes: Initialize the parameters of the particle swarm optimization algorithm; Based on the design parameters, the peak temperature and peak pressure are predicted using the peak temperature mapping model and the peak stress mapping model. Based on the peak temperature and the peak pressure, and based on the multi-objective optimization function, the design parameters of the coaxial through-silicon via are optimized using the particle swarm optimization algorithm. Determine whether the optimal design parameters have been obtained. If not, continue to optimize the design parameters; if so, the optimization is complete.

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