Scanning circuit and its driving method, display panel

Abstract

This invention discloses a scanning circuit and its driving method, as well as a display panel. The scanning circuit includes: a trigger input module, a potential control module, a node mutual control module, a first output module, and a second output module. The trigger input module receives a first clock signal; the potential control module receives both the first clock signal and a fourth clock signal; the node mutual control module receives both the first clock signal and the second clock signal; the first output module is electrically connected to both the trigger input module and the potential control module, receives the second clock signal, and outputs a first scanning signal; the second output module is electrically connected to both the trigger input module and the potential control module, receives a third clock signal, and outputs a second scanning signal; the initial pulses of the first to fourth clock signals are sequentially delayed by a preset time, and the pulses of adjacent clock signals overlap. This invention simplifies the scanning circuit structure and facilitates the implementation of narrow bezels in the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a scanning circuit and its driving method, and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming increasingly wide, and people's requirements for display panels are also getting higher and higher. A display panel includes pixel circuits and scanning circuits that provide scanning signals to the pixel circuits. As refresh rates increase and resolutions increase, the line time (i.e., the time interval between the start of scanning for each line of pixel circuits) is compressed shorter and shorter. This results in insufficient time for the scanning circuits to write data to the pixel circuits, leading to a deterioration in the uniformity of the display panel and limiting the development of high refresh rate and high resolution display panels. To solve the above problems and enhance the threshold compensation effect of the driving transistors, existing solutions require overlapping pulses of adjacent scanning signals. However, in existing technologies, the pulses of the scanning signals output from each stage of the same cascaded scanning circuit do not overlap. To provide scanning signals with overlapping pulses, two sets of scanning circuits are required, making the overall structure of the scanning drive circuit complex and unfavorable for the design of narrow bezels in display panels. Summary of the Invention

[0003] This invention provides a scanning circuit and its driving method, as well as a display panel, to simplify the scanning circuit structure and facilitate the realization of a narrow bezel on the display panel.

[0004] To achieve the above technical objectives, the embodiments of the present invention provide the following technical solutions:

[0005] A scanning circuit, wherein the scanning circuit is connected to a first clock signal, a second clock signal, a third clock signal and a fourth clock signal;

[0006] The scanning circuit includes:

[0007] A trigger input module is connected to a trigger input signal and the first clock signal, respectively, and the output terminal of the trigger input module serves as a first output control terminal; the trigger input module is used to control the potential of the first output control terminal;

[0008] A potential control module is connected to the first clock signal, the fourth clock signal, and the first potential signal, respectively. The output terminal of the potential control module serves as the second output control terminal. The potential control module is used to control the potential of the second output control terminal.

[0009] The node interconnection module is electrically connected to the first output control terminal and the second output control terminal respectively, and is connected to the first clock signal, the second clock signal and the second potential signal; the node interconnection module is used to control the potential of the first output control terminal and the second output control terminal;

[0010] The first output module is electrically connected to the first output control terminal and the second output control terminal respectively, and is connected to the second potential signal and the second clock signal; the first output module is used to output the first scan signal;

[0011] The second output module is electrically connected to the first output control terminal and the second output control terminal respectively, and is connected to the second potential signal and the third clock signal; the second output module is used to output the second scan signal;

[0012] The initial pulses of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially delayed by a preset time, and the pulses of adjacent clock signals overlap, so that the pulses of the first scan signal and the second scan signal overlap. Optionally, the pulse periods of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all 4 times the preset time.

[0013] The pulse widths of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all greater than the preset time and less than twice the preset time.

[0014] Optionally, the trigger input module includes: a first transistor; the gate of the first transistor is connected to the first clock signal, the first terminal of the first transistor is connected to the trigger input signal, and the second terminal of the first transistor is electrically connected to the first output control terminal.

[0015] Optionally, the potential control module includes a second transistor and a third transistor; the second transistor and the third transistor are connected in series between a first potential signal terminal and a second output control terminal; wherein, the first potential signal terminal is used to receive the first potential signal; the gate of the second transistor is connected to the fourth clock signal, and the gate of the third transistor is connected to the first clock signal.

[0016] Optionally, the node inter-control module includes: a first node inter-control unit, used to transmit the fourth clock signal to the second output control terminal in response to the first clock signal and the potential of the first output control terminal;

[0017] The second node mutual control unit is used to respond to the second clock signal and the potential of the second output control terminal, and transmit the second potential signal to the first output control terminal;

[0018] Preferably, the first node mutual control unit includes a fourth transistor and a fifth transistor; the fourth transistor and the fifth transistor are connected in series between the second output control terminal and the fourth clock terminal; wherein, the fourth clock terminal is used to receive the fourth clock signal; the gate of the fourth transistor is electrically connected to the first output control terminal, and the gate of the fifth transistor is connected to the first clock signal;

[0019] The second node mutual control unit includes a sixth transistor and a seventh transistor; the sixth transistor and the seventh transistor are connected in series between the first output control terminal and the second potential signal terminal; wherein, the second potential signal terminal is used to receive the second potential signal; the gate of the sixth transistor is electrically connected to the second output control terminal, and the gate of the seventh transistor is connected to the second clock signal.

[0020] Optionally, the first output module includes: a first output unit, configured to respond to the potential of the first output control terminal and output the second clock signal as the first scan signal;

[0021] The second output unit is used to respond to the potential of the second output control terminal and output the second potential signal as the first scan signal.

[0022] Preferably, the first output unit includes: an eighth transistor and a first capacitor; the gate of the eighth transistor is electrically connected to the first output control terminal and the first terminal of the first capacitor respectively, and the first terminal of the eighth transistor is connected to the second clock signal; the second terminal of the eighth transistor is electrically connected to the second terminal of the first capacitor and serves as the output terminal of the first output module.

[0023] The second output unit includes: a ninth transistor and a second capacitor; the gate of the ninth transistor is electrically connected to the second output control terminal and the first terminal of the second capacitor, respectively; the first terminal of the ninth transistor is connected to the second potential signal and is electrically connected to the second terminal of the second capacitor; the second terminal of the ninth transistor is electrically connected to the output terminal of the first output module.

[0024] Preferably, the first output unit further includes: a tenth transistor; the gate of the tenth transistor is connected to the first potential signal, the first terminal of the tenth transistor is electrically connected to the first output control terminal, and the second terminal of the tenth transistor is electrically connected to the gate of the eighth transistor.

[0025] Optionally, the second output module includes: a third output unit, configured to respond to the potential of the first output control terminal and output the third clock signal as the second scan signal;

[0026] The fourth output unit is used to respond to the potential of the second output control terminal and output the second potential signal as the second scan signal.

[0027] Preferably, the third output unit includes an eleventh transistor and a third capacitor; the gate of the eleventh transistor is electrically connected to the first output control terminal and the first terminal of the third capacitor, respectively, and the first terminal of the eleventh transistor is connected to the third clock signal; the second terminal of the eleventh transistor is electrically connected to the second terminal of the third capacitor and serves as the output terminal of the second output module.

[0028] The fourth output unit includes: a twelfth transistor; the gate of the twelfth transistor is electrically connected to the second output control terminal, the first terminal of the twelfth transistor is connected to the second potential signal, and the second terminal of the twelfth transistor is electrically connected to the output terminal of the second output module;

[0029] Preferably, the third output unit further includes: a thirteenth transistor; the gate of the thirteenth transistor is connected to the first potential signal, the first terminal of the thirteenth transistor is electrically connected to the first output control terminal, and the second terminal of the thirteenth transistor is electrically connected to the gate of the eleventh transistor.

[0030] Accordingly, embodiments of the present invention also provide a driving method for a scanning circuit, used to drive the scanning circuit provided in any embodiment of the present invention; the driving method includes:

[0031] In the first output stage, the first clock signal controls the trigger input module to transmit the trigger input signal to the first output control terminal; the node inter-control module responds to the potential of the first clock signal and the first output control terminal, and transmits the fourth clock signal to the second output control terminal; the first output module responds to the potential of the first output control terminal and outputs the second clock signal as the first scan signal; the second output module responds to the potential of the first output control terminal and outputs the third clock signal as the second scan signal.

[0032] In the second output stage, the first clock signal and the fourth clock signal control the potential control module to transmit the first potential signal to the second output control terminal; the node mutual control module responds to the potential of the second clock signal and the second output control terminal and transmits the second potential signal to the first output control terminal; the first output module responds to the potential of the second output control terminal and outputs the second potential signal as a first scan signal; the second output module responds to the potential of the second output control terminal and outputs the second potential signal as a second scan signal.

[0033] Accordingly, embodiments of the present invention also provide a display panel, including: a multi-stage scanning circuit as provided in any embodiment of the present invention, cascaded together.

[0034] Optionally, the second scan signal output by this stage scan circuit can be used as the trigger input signal for the next stage scan circuit.

[0035] The display panel further includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

[0036] The first clock terminal of the odd-level scanning circuit is electrically connected to the first clock signal line, the second clock terminal is electrically connected to the second clock signal line, the third clock terminal is electrically connected to the third clock signal line, and the fourth clock terminal is electrically connected to the fourth clock signal line.

[0037] The first clock terminal of the even-numbered scanning circuit is electrically connected to the third clock signal line, the second clock terminal is electrically connected to the fourth clock signal line, the third clock terminal is electrically connected to the first clock signal line, and the fourth clock terminal is electrically connected to the second clock signal line.

[0038] The scanning circuit provided in this invention offers a novel scanning drive architecture, including a trigger input module, a potential control module, a node inter-control module, a first output module, and a second output module. Based on the control of four clock signals, the scanning circuit's internal first output control terminal stabilizes at the on-state potential, and the second output control terminal stabilizes at the off-state potential. The width of this potential stabilization period covers the pulse duration of the second and third clock signals. During this stabilization period, the first output module outputs the second clock signal as the first scanning signal, and the second output module outputs the third clock signal as the second scanning signal. Therefore, one scanning circuit can output two sequentially shifted scanning signals with overlapping pulses. Thus, compared to the prior art's solution providing two sets of scanning circuits, this invention requires only one set, simplifying the overall structure of the scanning drive circuit and facilitating the implementation of narrow bezels. Furthermore, the simplified scanning circuit structure allows for increased spacing between functional patterns in each film layer within the same area, thereby reducing parasitic capacitance in the circuit, reducing signal delay, and improving driving performance. Therefore, compared to the prior art, this invention simplifies the scanning circuit structure, which is beneficial for achieving narrow bezels in display panels.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a scanning circuit provided in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of the driving timing of a scanning circuit provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of another scanning circuit provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of another scanning circuit provided in an embodiment of the present invention;

[0045] Figure 5 This is a driving timing diagram of another scanning circuit provided in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of another scanning circuit provided in an embodiment of the present invention;

[0047] Figure 7 This is a schematic flowchart of a scanning circuit driving method provided in an embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0049] Figure 9 This is a schematic diagram of the driving timing of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0050] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0052] As described in the background section, with increasing refresh rates and resolutions of display panels, line times are being compressed to increasingly shorter lengths. Since the threshold voltage compensation effect of the driving transistors in the pixel circuit is strongly correlated with line time, insufficient time for data writing and threshold compensation in the pixel circuit leads to poor display uniformity, thus limiting further improvements in refresh rates and resolutions. To address these issues, the following solutions have been proposed in the prior art:

[0053] Option 1 utilizes Dual Data technology to extend the data write time of each row of pixel circuits beyond the row time, thereby increasing the data write and threshold compensation time and improving data write performance. Specifically, this involves connecting adjacent pixel circuits in the same column of the display panel to different data lines. For example, odd-numbered row pixel circuits are connected to one set of data lines, and even-numbered row pixel circuits are connected to another set. The data write processes of odd and even-numbered row pixel circuits continue to alternate, without affecting each other. The data write times of adjacent rows of pixel circuits can overlap, allowing the data write time of each row of pixel circuits to exceed the row time, potentially extending it to nearly two row times.

[0054] Option 2: Improve the driving timing of the pixel circuit by inserting a driving transistor recovery stage before the data writing stage. Control the gate initialization transistor and the threshold compensation transistor to conduct simultaneously, and use a large current to impact the driving transistor to accelerate the recovery of the driving transistor threshold voltage, thereby improving the ghosting problem and enhancing display uniformity.

[0055] As the above analysis shows, all solutions that improve display uniformity require pulse overlap of adjacent scan signals. In existing technologies, two sets of scan circuits are needed to provide the overlapping scan signals, resulting in large parasitic capacitance and delay, which is detrimental to the design of narrow bezels on display panels.

[0056] To address the aforementioned problems, embodiments of the present invention provide a novel scanning circuit that can output two scanning signals with overlapping pulses from a single scanning circuit. Figure 1 This is a schematic diagram of a scanning circuit provided in an embodiment of the present invention. See also... Figure 1 The scanning circuit includes: a trigger input terminal, a first potential signal terminal, a second potential signal terminal, a first clock terminal, a second clock terminal, a third clock terminal, and a fourth clock terminal. The trigger input terminal is connected to the trigger input signal SIN, the first potential signal terminal is connected to the first potential signal VGL, and the second potential signal terminal is connected to the second potential signal VGH. The first clock terminal, the second clock terminal, the third clock terminal, and the fourth clock terminal are sequentially connected to the first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4.

[0057] The scanning circuit specifically includes: a trigger input module 10, a potential control module 20, a node mutual control module 30, a first output module 40, and a second output module 50.

[0058] The trigger input module 10 is electrically connected to the first clock terminal and the trigger input terminal, respectively. The output terminal of the trigger input module 10 serves as the first output control terminal N1. The trigger input module 10 is used to control the potential of the first output control terminal N1. For example, in response to the first clock signal SCK1, the trigger input module 10 transmits the trigger input signal SIN to the first output control terminal N1. The potential control module 20 is electrically connected to the first clock terminal, the fourth clock terminal, and the first potential signal terminal, respectively. The output terminal of the potential control module 20 serves as the second output control terminal N2. The potential control module 20 is used to control the potential of the second output control terminal N2. For example, in response to the first clock signal SCK1 and the fourth clock signal SCK4, the potential control module 20 transmits the first potential signal VGL to the second output control terminal N2.

[0059] The node inter-control module 30 is electrically connected to the first output control terminal N1, the second output control terminal N2, the first clock terminal, the second clock terminal, and the second potential signal terminal, respectively. The node inter-control module 30 is used to control the potentials of the first output control terminal N1 and the second output control terminal N2. For example, in response to the first clock signal SCK1 and the potential of the first output control terminal N1, the node inter-control module 30 transmits the fourth clock signal SCK4 to the second output control terminal N2; and in response to the potential of the second output control terminal N2 and the second clock signal SCK2, it transmits the second potential signal VGH to the first output control terminal N1.

[0060] The first output module 40 is electrically connected to the first output control terminal N1, the second output control terminal N2, the second potential signal terminal, and the second clock terminal, respectively. The first output module 40 is used to output a first scan signal Vout1. Exemplarily, the first output module 40 is used to output a second potential signal VGH or a second clock signal SCK2 as the first scan signal Vout1 based on the potentials of the first output control terminal N1 and the second output control terminal N2. The second output module 50 is electrically connected to the first output control terminal N1, the second output control terminal N2, the second potential signal terminal, and the third clock terminal, respectively. The second output module 50 is used to output a second scan signal Vout2. Exemplarily, the second output module 50 is used to output a second potential signal VGH or a third clock signal SCK3 as the second scan signal Vout2 based on the potentials of the first output control terminal N1 and the second output control terminal N2.

[0061] The initial pulses of the first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4 are delayed by a preset time in sequence, and the pulses of two adjacent clock signals overlap, so that the pulses of the first scan signal Vout1 and the second scan signal Vout2 overlap.

[0062] For example, both the first potential signal VGL and the second potential signal VGH can be DC voltage signals. The logic of the first potential signal VGL and the second potential signal VGH is opposite; for example, the first potential signal VGL is a low potential signal, and the second potential signal VGH is a high potential signal. Each clock signal is a clock signal that alternates between high and low potentials. The pulse of the clock signal refers to the conduction pulse of the clock signal. The overlap of pulses between two adjacent clock signals means that within one pulse cycle of the first clock signal SCK1, the pulses of the first clock signal SCK1 overlap with those of the second clock signal SCK2; the pulses of the second clock signal SCK2 overlap with those of the third clock signal SCK3; the pulses of the third clock signal SCK3 overlap with those of the fourth clock signal SCK4; and the pulse of the fourth clock signal SCK4 overlaps with the pulse of the first clock signal SCK1 in the next pulse cycle. The trigger input signal SIN can be a pulse signal with a low conduction potential, and its pulse width covers the pulse width of the first clock signal SCK1.

[0063] For example, the driving process of the scanning circuit includes:

[0064] In the first output phase, the trigger input module 10 controls the first output control terminal N1 to be at the on potential according to the first clock signal SCK1 and the trigger input signal SIN. This causes the first output module 40 to respond to the on potential of the first output control terminal N1 and output the second clock signal SCK2 as the first scan signal Vout1. The second output module 50 responds to the on potential of the first output control terminal N1 and outputs the third clock signal SCK3 as the second scan signal Vout2. During this phase, at least within the pulse time of the second clock signal SCK2 and the third clock signal SCK3, the node inter-control module 30 can control the second output control terminal N2 to be at the off potential according to the potential of the first clock signal SCK1, the fourth clock signal SCK4, and the first output control terminal N1, thereby preventing the two output modules from mistakenly outputting the second potential signal VGH.

[0065] In the second output stage, the potential control module 20 controls the second output control terminal N2 to be on-state based on the first clock signal SCK1, the fourth clock signal SCK4, and the first potential signal VGL. This causes the first output module 40 to respond to the on-state of the second output control terminal N2 and output the second potential signal VGH as the first scan signal Vout1. The second output module 50 responds to the on-state of the second output control terminal N2 and outputs the second potential signal VGH as the second scan signal Vout2. In this stage, the node inter-control module 30 can control the first output control terminal N1 to be off-state based on the second clock signal SCK2, the second potential signal VGH, and the potential of the second output control terminal N2, so that both output modules only output the second potential signal VGH.

[0066] Based on the joint control of the trigger input module 10, the potential control module 20, and the node mutual control module 30, the first output control terminal N1 can be stabilized at the on-potential, and the second output control terminal N2 can be stabilized at the off-potential for a period covering the pulse time of the second clock signal SCK2 and the third clock signal SCK3. This allows the first output module 40 to output the pulse of the second clock signal SCK2, and the second output module 50 to output the pulse of the third clock signal SCK3. This results in the first scan signal Vout1 and the second scan signal Vout2 forming two scan signals that are sequentially shifted and have overlapping pulses. By controlling the preset time of the pulse interval between the two scan signals to be equal to the line time, the output signal of the scan circuit can be matched with the Dual Data technology scheme and the accelerated recovery scheme of the drive transistor, providing conditions for the realization of high refresh rate and high resolution of the display panel.

[0067] The scanning circuit provided in this embodiment of the invention offers a novel scanning drive architecture, including a trigger input module 10, a potential control module 20, a node inter-control module 30, a first output module 40, and a second output module 50. Based on the control of four clock signals, the scanning circuit internally stabilizes the first output control terminal N1 at the on-state potential and the second output control terminal N2 at the off-state potential. The width of this potential stabilization period covers the pulse duration of the second clock signal SCK2 and the third clock signal SCK3. During this potential stabilization period, the first output module 40 outputs the second clock signal SCK2 as the first scanning signal Vout1, and the second output module 50 outputs the third clock signal SCK3 as the second scanning signal Vout1. Therefore, one scanning circuit can output two sequentially shifted scanning signals with overlapping pulses. Thus, compared to the prior art which provides two sets of scanning circuits, this embodiment of the invention only requires one scanning circuit, simplifying the overall structure of the scanning drive circuit and facilitating the implementation of a narrow bezel. From another perspective, the simplified structure of the scanning circuit allows for increased spacing between the functional patterns of each film layer while occupying the same area. This reduces parasitic capacitance in the circuit, decreases signal delay, and improves driving performance. Therefore, compared to existing technologies, the embodiments of this invention simplify the scanning circuit structure, which is beneficial for achieving narrow bezels in display panels.

[0068] The working process of the scanning circuit will be explained in detail below with reference to the circuit timing. Figure 2 This is a schematic diagram of the driving timing of a scanning circuit provided in an embodiment of the present invention. Combined with... Figure 1 and Figure 2 Taking the low-potential conduction response of each functional module in the scanning circuit as an example, the driving process of the scanning circuit includes: a first output stage T1 and a second output stage T2.

[0069] The first output stage T1, which is the clock signal output stage, can be further divided into the first sub-stage T11 and the second sub-stage T12.

[0070] In the first sub-stage T11, both the first clock signal SCK1 and the fourth clock signal SCK4 are at low levels, while both the second clock signal SCK2 and the third clock signal SCK3 are at high levels. The trigger input module 10 is turned on, transmitting the low level of the trigger input signal SIN to the first output control terminal N1, causing N1 to switch to a low level. In response to the low levels of the first clock signal SCK1 and the first output control terminal N1, the node inter-control module 20 transmits the low level of the fourth clock signal SCK4 to the second output control terminal N2; simultaneously, the level control module 20 is turned on, transmitting the low level of the first level signal VGL to the second output control terminal N2. In response to the low level of the first output control terminal N1, the first output module 10 outputs the high level of the second clock signal SCK2, and in response to the low level of the second output control terminal N2, outputs the high level of the second level signal VGH. Therefore, the first scan signal Vout1 is at a high level. The second output module 20 responds to the low potential of the first output control terminal N1 by outputting the high potential of the third clock signal SCK3, and responds to the low potential of the second output control terminal N2 by outputting the high potential of the second potential signal VGH. Therefore, the second scan signal Vout2 is at a high potential.

[0071] In the second sub-stage T12, the first clock signal SCK1 initially remains low and then transitions to a high level; the pulses of the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4 appear sequentially. When the first clock signal SCK1 remains low and the fourth clock signal SCK4 transitions to a high level, the trigger input module 10 is turned on, transmitting the low level of the trigger input signal SIN to the first output control terminal N1, which remains low. The level control module 20 remains off, not affecting the level of the second output control terminal N2; the node inter-control module 20 responds to the low level of the first clock signal SCK1 and the first output control terminal N1, transmitting the high level of the fourth clock signal SCK4 to the second output control terminal N2, which then transitions to a high level. After the first clock signal SCK1 transitions to a high level, regardless of the level of the fourth clock signal SCK4, both the trigger input module 10 and the level control module 20 are turned off, the first output control terminal N1 remains low, and the second output control terminal N2 remains high. The first sub-stage T11 is actually the output sub-stage of the clock signal and the second potential signal.

[0072] Therefore, throughout the entire second sub-stage T12, the first output control terminal N1 remains at a low potential, and the second output control terminal N2 remains at a high potential. In response to the low potential of the first output control terminal N1, the first output module 10 outputs the second clock signal SCK2 as the first scan signal Vout1, and the potential of the first scan signal Vout1 changes synchronously with the potential of the second clock signal SCK2. In response to the low potential of the first output control terminal N1, the second output module 20 outputs the third clock signal SCK3 as the second scan signal Vout2, and the potential of the second scan signal Vout2 changes synchronously with the potential of the third clock signal SCK3. The second sub-stage T12 is a clock signal-only output stage. The start time of the second sub-stage T12 is the end time of the previous pulse of the fourth clock signal SCK4, and the end time of the second sub-stage T12 is the start time of the next pulse of the first clock signal SCK1. Therefore, the node potential stabilization time (i.e., the duration of the second sub-stage T12) when the first output control terminal N1 is stable at a low potential and the second output control terminal N2 is stable at a high potential covers the pulse time of the second clock signal SCK2 and the third clock signal SCK3. This allows the first output module 40 to completely output the pulse of the second clock signal SCK2 and the second output module 50 to completely output the pulse of the third clock signal SCK3 in the second sub-stage T12, thereby causing the pulses of the first scan signal Vout1 and the second scan signal Vout2 to overlap.

[0073] The second output stage T2, namely the second potential signal output stage, can be further divided into the third sub-stage T21, the fourth sub-stage T22, and the fifth sub-stage T23.

[0074] In the third sub-stage T21, the first clock signal SCK1 and the fourth clock signal SCK4 are at low potentials, while the second clock signal SCK2 and the third clock signal SCK3 are at high potentials. The trigger input module 10 is turned on, transmitting the high potential of the trigger input signal SIN to the first output control terminal N1, causing N1 to switch to a high potential. The level control module 20 is turned on, transmitting the low potential of the fourth clock signal SCK4 to the second output control terminal N2, causing N2 to switch to a low potential.

[0075] In the fourth sub-stage T22, the first clock signal SCK1 remains low, while the fourth clock signal SCK4 transitions to a high level; the pulse of the second clock signal SCK2 begins to appear. The trigger input module 10 is turned on, transmitting the high potential of the trigger input signal SIN to the first output control terminal N1, which remains high. The potential control module 20 is turned off, without affecting the potential of the second output control terminal N2, which remains low. After the second clock signal SCK2 transitions to a low level, the node inter-control module 30 responds to the low potential of the second output control terminal N2 and the second clock signal SCK2 by transmitting the high potential of the second potential signal VGH to the first output control terminal N1, thus maintaining the first output control terminal N1 at a high level.

[0076] In the fifth sub-stage T23, the first clock signal SCK1 jumps to a high level. Both the trigger input module 10 and the level control module 20 are turned off, which does not affect the levels of the two output control terminals. The first output control terminal N1 remains at a high level, and the second output control terminal N2 remains at a low level.

[0077] Therefore, throughout the entire second output phase T2, the first output control terminal N1 remains at a high potential, and the second output control terminal N2 remains at a low potential. In response to the low potential of the second output control terminal N2, the first output module 10 outputs the second potential signal VGH as the first scan signal Vout1, which remains at a high potential. Similarly, in response to the low potential of the second output control terminal N2, the second output module 20 outputs the second potential signal VGH as the second scan signal Vout2, which remains at a high potential.

[0078] The subsequent stages repeat the second output stage T2 until the input signal SIN is triggered to change to a low level again.

[0079] In summary, the scanning circuit provided in this embodiment of the invention can provide a first scanning signal Vout1 and a second scanning signal Vout2 with overlapping pulses. When applied in a Dual Data scheme, the first scanning signal Vout1 and the second scanning signal Vout2 can be used as the scanning signals required by two adjacent rows of pixel circuits, respectively. When applied in a driver transistor accelerated recovery scheme, the first scanning signal Vout1 and the second scanning signal Vout2 can be used as the scanning signal required by the gate initialization transistor and the scanning signal required by the threshold compensation transistor in the same pixel circuit, respectively. For example, the preset time can be the row time of the pixel circuit, so that the output signal of the scanning circuit can be adapted to various schemes for improving display uniformity, thereby meeting the application requirements of high refresh rates and high resolutions.

[0080] See also Figure 2, based on the above embodiments, optionally, the pulse periods TT of the first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4 are all 4 times the preset time. The pulse widths w of the first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4 are all greater than the preset time and less than 2 times the preset time. Taking the preset time equal to the line time h as an example, h < w < 2h. Since the start times of the pulses of adjacent clock signals are separated by a line time h, the pulse overlap amount △w between two adjacent scan signals is △w = w - h. Therefore, the range of the pulse overlap amount △w is 0 to h. In design, the pulse overlap amount △w can be adjusted by adjusting the size of w.

[0081] Figure 3 is a schematic structural diagram of another scanning circuit provided by an embodiment of the present invention. Refer to Figure 3 , in one embodiment, optionally, the node mutual control module 30 includes: a first node mutual control unit 31 and a second node mutual control unit 32.

[0082] The first node mutual control unit 31 is electrically connected to the first clock terminal, the fourth clock terminal, the first output control terminal N1, and the second clock control terminal N2 respectively. The first node mutual control unit 31 is configured to conduct in response to the potential of the first clock signal SCK1 and the first output control terminal N1, and transmit the fourth clock signal SCK4 to the second output control terminal N2. The second node mutual control unit 32 is electrically connected to the second clock terminal, the second potential signal terminal, the first output control terminal N1, and the second clock control terminal N2 respectively, and is configured to conduct in response to the potential of the second clock signal SCK2 and the second output control terminal N2, and transmit the second potential signal VGH to the first output control terminal N1.

[0083] Through the two node mutual control units, the node potential mutual control between the first output control terminal N1 and the second output control terminal N2 can be realized, reducing the possibility of an intermediate potential between the high and low potentials of the potential of the first output control terminal N1 and the potential of the second output control terminal N2, ensuring that the potentials of the two control terminals are clear, enabling the first output module 40 and the second output module 50 to accurately identify the potentials of the two control terminals, and thus ensuring the accurate output states of the first output module 40 and the second output module 50, so as to improve the output stability of the scanning circuit.

[0084] Continue to refer to Figure 3 >In one embodiment, optionally, the first output module 40 includes: a first output unit 41 and a second output unit 42. The output terminal of the first output unit 41 is connected to the output terminal of the second output unit 42, serving as the output terminal of the first output module 40. The first output unit 41 is electrically connected to a first output control terminal N1 and a second clock terminal, respectively, and is used to output a second clock signal SCK2 as a first scan signal Vout1 in response to the potential of the first output control terminal N1. The second output unit 42 is electrically connected to a second output control terminal N2 and a second potential signal terminal, respectively, and is used to output a second potential signal VGH as a first scan signal Vout1 in response to the potential of the second output control terminal N2.

[0085] See also Figure 3 In one embodiment, optionally, the second output module 50 includes a third output unit 51 and a fourth output unit 52. The output terminal of the third output unit 51 is connected to the output terminal of the fourth output unit 52, serving as the output terminal of the second output module 50. The third output unit 51 is electrically connected to the first output control terminal N1 and the third clock terminal, respectively, and is used to output the third clock signal SCK3 as the second scan signal Vout2 in response to the potential of the first output control terminal N1. The fourth output unit 52 is electrically connected to the second output control terminal N2 and the second potential signal terminal, respectively, and is used to output the second potential signal VGH as the second scan signal Vout2 in response to the potential of the second output control terminal N2.

[0086] The above embodiments exemplarily describe the constituent units of the scanning circuit and their operation process. The specific structure that each functional unit may have will be described below.

[0087] Figure 4 This is a schematic diagram of another scanning circuit provided in an embodiment of the present invention. To verify the output effect of the scanning circuit provided in this embodiment of the present invention, the inventors, based on... Figure 4 The scanning circuit shown was simulated, and the simulation results are as follows: Figure 5 As shown.

[0088] See Figure 4 In one embodiment, optionally, the trigger input module 10 includes: a first transistor T1; the gate of the first transistor T1 is electrically connected to a first clock terminal, the first electrode of the first transistor T1 is electrically connected to a trigger input terminal, and the second electrode of the first transistor T1 is electrically connected to a first output control terminal N1. This embodiment sets the trigger input module 10 to consist of a single transistor, simplifying the circuit structure and making it easy to implement.

[0089] See also Figure 4In one embodiment, optionally, the potential control module 20 includes: a second transistor T2 and a third transistor T3; the second transistor T2 and the third transistor T3 are connected in series between a first potential signal terminal and a second output control terminal N2, the gate of the second transistor T2 is electrically connected to a fourth clock terminal, and the gate of the third transistor T3 is electrically connected to the first clock terminal. Exemplarily, the first terminal of the third transistor T3 is electrically connected to the first potential signal terminal, the second terminal of the third transistor T3 is electrically connected to the first terminal of the second transistor T2, and the second terminal of the second transistor T2 is electrically connected to the second output control terminal N2.

[0090] See also Figure 4 In one embodiment, optionally, the first node interconnection unit 31 includes: a fourth transistor T4 and a fifth transistor T5; the fourth transistor T4 and the fifth transistor T5 are connected in series between the second output control terminal N2 and the fourth clock terminal, the gate of the fourth transistor T4 is electrically connected to the first output control terminal N1, and the gate of the fifth transistor T5 is electrically connected to the first clock terminal. Exemplarily, the first terminal of the fourth transistor T4 is electrically connected to the second output control terminal N2, the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the fifth transistor T5, and the second terminal of the fifth transistor T5 is electrically connected to the fourth clock terminal.

[0091] See also Figure 4 In one embodiment, optionally, the second node interconnection unit 32 includes: a sixth transistor T6 and a seventh transistor T7; the sixth transistor T6 and the seventh transistor T7 are connected in series between the first output control terminal N1 and the second potential signal terminal, the gate of the sixth transistor T6 is electrically connected to the second output control terminal N2, and the gate of the seventh transistor T7 is electrically connected to the second clock terminal. Exemplarily, the first terminal of the sixth transistor T6 is electrically connected to the second potential signal terminal, the second terminal of the sixth transistor T6 is electrically connected to the first terminal of the seventh transistor T7, and the second terminal of the seventh transistor T7 is electrically connected to the first output control terminal N1.

[0092] See also Figure 4 In one embodiment, optionally, the first output unit 41 includes: an eighth transistor T8 and a first capacitor C1; the gate (i.e., node N3) of the eighth transistor T8 is electrically connected to the first output control terminal N1 and the first terminal of the first capacitor C1, respectively; the first terminal of the eighth transistor T8 is electrically connected to the second clock terminal; the second terminal of the eighth transistor T8 is electrically connected to the second terminal of the first capacitor C1, and serves as the output terminal of the first output module 40. The first capacitor C1 is used to stabilize the gate potential of the eighth transistor T8 and to couple and control the gate potential of the eighth transistor T8.

[0093] Combination Figure 4 and Figure 5It can be seen that before the pulse phase T121 of the first scan signal Vout1 begins, since the first output control terminal N1 is at a low potential, node N3 is also at a low potential, thereby controlling the eighth transistor T8 to conduct and outputting the second clock signal SCK2 at a high potential. At this time, the first capacitor C1 is used to store the potential of node N3 and the output terminal of the first output module 40. When the pulse phase T121 of the first scan signal Vout1 begins, the second clock signal SCK2 jumps from a high potential to a low potential, causing the first scan signal Vout1 to jump from a high potential to a low potential. Under the coupling effect of the first capacitor C1, the potential VN3 of node N3 jumps to an even lower potential to ensure that the eighth transistor T8 is fully turned on and that the first scan signal Vout1 can reach the low potential value of the second clock signal SCK2.

[0094] Furthermore, the first output unit 41 may further include: a tenth transistor T10; the gate of the tenth transistor T10 is electrically connected to the first potential signal terminal, the first terminal of the tenth transistor T10 is electrically connected to the first output control terminal N1, and the second terminal of the tenth transistor T10 is electrically connected to the gate of the eighth transistor T8. In this embodiment, the first and second terminals of the tenth transistor T10 are respectively connected to the first output control terminal N1 and the gate of the eighth transistor T8, which can reduce the large voltage difference between node N3 and the first output control terminal N1 when the potential of the first output control terminal N1 changes, thereby increasing the reliability of the circuit.

[0095] See also Figure 4 In one embodiment, optionally, the second output unit 42 includes: a ninth transistor T9 and a second capacitor C2; the gate of the ninth transistor T9 is electrically connected to the second output control terminal N2 and the first terminal of the second capacitor C2, respectively; the first terminal of the ninth transistor T9 is electrically connected to the second potential signal terminal and the second terminal of the second capacitor C2, respectively; the second terminal of the ninth transistor T9 is electrically connected to the output terminal of the first output module 40. The second capacitor C2 is used to maintain the potential of the second output control terminal N2.

[0096] See also Figure 4 In one embodiment, optionally, the third output unit 51 includes: an eleventh transistor T11 and a third capacitor C3; the gate (node ​​N4) of the eleventh transistor T11 is electrically connected to the first output control terminal N1 and the first terminal of the third capacitor C3 respectively, the first terminal of the eleventh transistor T11 is electrically connected to the third clock terminal; the second terminal of the eleventh transistor T11 is electrically connected to the second terminal of the third capacitor C3 and serves as the output terminal of the second output module 50.

[0097] Combination Figure 4 and Figure 5As can be seen, similar to the potential change process of the pulse phase T121 of the first scan signal Vout1, at the beginning of the pulse phase T122 of the second scan signal Vout2, due to the third clock signal SCK3 jumping from a high potential to a low potential, based on the coupling effect of the third capacitor C3, the potential VN4 of node N4 is coupled to a lower potential to ensure that the eleventh transistor T11 is fully turned on, and to ensure that the second scan signal Vout2 can reach the low potential value of the third clock signal SCK3.

[0098] Furthermore, the third output unit 51 also includes: a thirteenth transistor T13; the gate of the thirteenth transistor T13 is electrically connected to the first potential signal terminal, the first terminal of the thirteenth transistor T13 is electrically connected to the first output control terminal, and the second terminal of the thirteenth transistor T13 is electrically connected to the gate of the eleventh transistor T11. The function of the thirteenth transistor T13 is similar to that of the tenth transistor T10, and will not be described again.

[0099] See also Figure 4 In one embodiment, optionally, the fourth output unit 52 includes: a twelfth transistor T12; the gate of the twelfth transistor T12 is electrically connected to the second output control terminal N2, the first terminal of the twelfth transistor T12 is electrically connected to the second potential signal terminal, and the second terminal of the twelfth transistor T12 is electrically connected to the output terminal of the second output module 50. Since the second capacitor C2 is already provided in the second output unit 42 to maintain the potential of the second output control terminal N2, no other capacitors need to be provided in the fourth output unit 52.

[0100] The above embodiments exemplify a specific structure of the scanning circuit, but are not intended to limit the invention. In other embodiments, the positions of components in each functional module can be adjusted as needed.

[0101] Figure 6 This is a schematic diagram of another scanning circuit provided in an embodiment of the present invention. See also... Figure 6 In one embodiment, the positions of the second transistor T2 and the third transistor T3 can be interchanged. Since the two transistors are connected in series, the potential control module 20 will only be turned on when the pulses of the first clock signal SCK1 and the fourth clock signal SCK4 overlap. Interchanging the positions of the two transistors will not affect the operation of the scanning circuit.

[0102] See also Figure 6 In one embodiment, the positions of the fourth transistor T4 and the fifth transistor T5 can be interchanged. Since the two transistors are connected in series, the first node mutual control unit 31 will only be turned on when the first clock signal SCK1 and the first output control terminal N1 are both on. Interchanging the positions of the two transistors will not affect the operation of the scanning circuit.

[0103] See also Figure 6 In one embodiment, the positions of the sixth transistor T6 and the seventh transistor T7 can be interchanged. Since the two transistors are connected in series, the second node mutual control unit 32 will only be turned on when the second clock signal SCK2 and the second output control terminal N2 are both on potentials. Interchanging the positions of the two transistors will not affect the operation of the scanning circuit.

[0104] It should be noted that the first terminal of each transistor involved in the above embodiments can be called the source or drain, and the corresponding second terminal can be called the drain or source. Since the structure of the transistors in the display panel is symmetrical, the source and drain of each transistor are not distinguished.

[0105] It should also be noted that in the above embodiments, each transistor in the scanning circuit is exemplarily shown to be a P-type transistor, which is not intended to limit the present invention. In other embodiments, some or all of the transistors may be set to N-type transistors as needed, and the timing of the control signals connected to the transistors may be adjusted accordingly.

[0106] This invention also provides a driving method for a scanning circuit, which can be applied to the scanning circuit provided in any embodiment of this invention and has corresponding beneficial effects. Figure 7 This is a schematic flowchart illustrating a scanning circuit driving method according to an embodiment of the present invention. See also... Figure 7 The driving method of the scanning circuit includes:

[0107] S110, First output stage: The first clock signal controls the trigger input module to transmit the trigger input signal to the first output control terminal; the node mutual control module responds to the potential of the first clock signal and the first output control terminal and transmits the fourth clock signal to the second output control terminal; the first output module responds to the potential of the first output control terminal and outputs the second clock signal as the first scan signal; the second output module responds to the potential of the first output control terminal and outputs the third clock signal as the second scan signal.

[0108] S120, Second Output Stage: The first clock signal and the fourth clock signal control the potential control module to transmit the first potential signal to the second output control terminal; the node mutual control module responds to the second clock signal and the potential of the second output control terminal, and transmits the second potential signal to the first output control terminal; the first output module responds to the potential of the second output control terminal and outputs the second potential signal as the first scan signal; the second output module responds to the potential of the second output control terminal and outputs the second potential signal as the second scan signal.

[0109] The scanning circuit driving method provided in this embodiment of the invention, based on the control of four clock signals, enables the scanning circuit to output two sequentially shifted scanning signals with overlapping pulses. Thus, this embodiment of the invention requires only one set of scanning circuits, simplifying the overall structure of the scanning driving circuit, saving space occupied by the scanning circuit, and facilitating the implementation of narrow bezels. Furthermore, the simplified structure of the scanning circuit allows for increased spacing between the functional patterns of each film layer within the same area, thereby reducing parasitic capacitance in the circuit and reducing signal delay.

[0110] It should be noted that in the various embodiments of the scanning circuit, specific descriptions of the driving methods for different scanning circuits are provided. These driving methods can all be considered as the driving methods of the scanning circuit provided in the embodiments of the present invention, and repeated content will not be described here.

[0111] This invention also provides a display panel comprising multiple cascaded scanning circuits as provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also: Figure 8 The cascading connection of each scanning circuit 200 means that the output terminal of the second output module in the current scanning circuit is electrically connected to the trigger input terminal of the next scanning circuit. That is, the second scanning signal output by the current scanning circuit serves as the trigger input signal for the next scanning circuit. In terms of pulse relationship, the first scanning signal Vout1 output by the current scanning circuit 200 is equivalent to a shifted output of the trigger input signal for that circuit, and the second scanning signal Vout2 output by the current scanning circuit 200 is equivalent to a shifted output of the first scanning signal Vout1. In this embodiment, the cascading method is equivalent to using the second scanning signal Vout2 output by the current scanning circuit 200 as the trigger input signal for the next scanning circuit 200. Therefore, the first scanning signal Vout1 output by the next scanning circuit 200 is equivalent to a shifted output of the second scanning signal Vout2 output by the current scanning circuit 200. This allows for the step-by-step shifting and output of the scan signal. The pulses of each adjacent scan signal are spaced by the same preset time (line time), and there is overlap between the pulses of each adjacent scan signal, which meets the driving requirements of the pixel circuit. Specifically, the first scan signal Vout1 output by each stage of the scan circuit 200 serves as the odd-numbered stage scan signal, and the second scan signal Vout2 output by each stage of the scan circuit 200 serves as the even-numbered stage scan signal. The output waveforms of the multi-stage cascaded scan circuit can be seen in [reference needed]. Figure 9 , Figure 9 The waveforms of the first four scan signals Scan1 to Scan4 are given as an example. Figure 9 It can be seen that under this cascaded structure, the shift output of each scanning signal can be reliably realized.

[0112] See also Figure 8 Based on the above embodiments, the display panel may optionally include: a first clock signal line 71 for providing clock signal CLK1; a second clock signal line 72 for providing clock signal CLK2; a third clock signal line 73 for providing clock signal CLK3; a fourth clock signal line 74 for providing clock signal CLK4; and an input signal line 75 for scanning input signal IN as a trigger input signal for the first-stage scanning circuit 200.

[0113] In the odd-numbered scanning circuit 200, the first clock terminal is electrically connected to the first clock signal line 71, the second clock terminal is electrically connected to the second clock signal line 72, the third clock terminal is electrically connected to the third clock signal line 73, and the fourth clock terminal is electrically connected to the fourth clock signal line 74. In the even-numbered scanning circuit 200, the first clock terminal is electrically connected to the third clock signal line 73, the second clock terminal is electrically connected to the fourth clock signal line 74, the third clock terminal is electrically connected to the first clock signal line 71, and the fourth clock terminal is electrically connected to the second clock signal line 72.

[0114] Furthermore, the display panel may also include: multiple scan signal lines 61 for transmitting first scan signals at each stage; and multiple scan signal lines 62 for transmitting second scan signals at each stage.

[0115] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A scanning circuit, characterized in that, The scanning circuit is connected to a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; The scanning circuit includes: A trigger input module is connected to a trigger input signal and the first clock signal, respectively, and the output terminal of the trigger input module serves as a first output control terminal; the trigger input module is used to control the potential of the first output control terminal; A potential control module is connected to the first clock signal, the fourth clock signal, and the first potential signal, respectively. The output terminal of the potential control module serves as the second output control terminal. The potential control module is used to control the potential of the second output control terminal. The node interconnection module is electrically connected to the first output control terminal and the second output control terminal respectively, and is connected to the first clock signal, the second clock signal and the second potential signal; the node interconnection module is used to control the potential of the first output control terminal and the second output control terminal; The first output module is electrically connected to the first output control terminal and the second output control terminal respectively, and is connected to the second potential signal and the second clock signal; the first output module is used to output the first scan signal; The second output module is electrically connected to the first output control terminal and the second output control terminal respectively, and is connected to the second potential signal and the third clock signal; the second output module is used to output the second scan signal; The initial pulses of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially delayed by a preset time, and the pulses of two adjacent clock signals overlap, so that the pulses of the first scan signal and the second scan signal overlap. The node inter-control module includes: a first node inter-control unit, used to transmit the fourth clock signal to the second output control terminal in response to the first clock signal and the potential of the first output control terminal; The second node mutual control unit is used to respond to the second clock signal and the potential of the second output control terminal, and transmit the second potential signal to the first output control terminal; The first node mutual control unit includes a fourth transistor and a fifth transistor; the fourth transistor and the fifth transistor are connected in series between the second output control terminal and the fourth clock terminal; wherein, the fourth clock terminal is used to receive the fourth clock signal; the gate of the fourth transistor is electrically connected to the first output control terminal, and the gate of the fifth transistor is connected to the first clock signal; The second node mutual control unit includes a sixth transistor and a seventh transistor; the sixth transistor and the seventh transistor are connected in series between the first output control terminal and the second potential signal terminal; wherein, the second potential signal terminal is used to receive the second potential signal; the gate of the sixth transistor is electrically connected to the second output control terminal, and the gate of the seventh transistor is connected to the second clock signal.

2. The scanning circuit according to claim 1, characterized in that, The pulse periods of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all 4 times the preset time; The pulse widths of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all greater than the preset time and less than twice the preset time.

3. The scanning circuit according to claim 1, characterized in that, The trigger input module includes: a first transistor; the gate of the first transistor is connected to the first clock signal, the first terminal of the first transistor is connected to the trigger input signal, and the second terminal of the first transistor is electrically connected to the first output control terminal.

4. The scanning circuit according to claim 1, characterized in that, The potential control module includes a second transistor and a third transistor; the second transistor and the third transistor are connected in series between a first potential signal terminal and a second output control terminal; wherein, the first potential signal terminal is used to receive the first potential signal; the gate of the second transistor is connected to the fourth clock signal, and the gate of the third transistor is connected to the first clock signal.

5. The scanning circuit according to claim 1, characterized in that, The first output module includes: a first output unit, used to respond to the potential of the first output control terminal and output the second clock signal as the first scan signal; The second output unit is used to respond to the potential of the second output control terminal and output the second potential signal as the first scan signal.

6. The scanning circuit according to claim 5, characterized in that, The first output unit includes an eighth transistor and a first capacitor; the gate of the eighth transistor is electrically connected to the first output control terminal and the first terminal of the first capacitor, respectively, and the first terminal of the eighth transistor is connected to the second clock signal; the second terminal of the eighth transistor is electrically connected to the second terminal of the first capacitor and serves as the output terminal of the first output module. The second output unit includes: a ninth transistor and a second capacitor; the gate of the ninth transistor is electrically connected to the second output control terminal and the first terminal of the second capacitor, respectively; the first terminal of the ninth transistor is connected to the second potential signal and is electrically connected to the second terminal of the second capacitor; the second terminal of the ninth transistor is electrically connected to the output terminal of the first output module.

7. The scanning circuit according to claim 6, characterized in that, The first output unit further includes: a tenth transistor; the gate of the tenth transistor is connected to the first potential signal, the first terminal of the tenth transistor is electrically connected to the first output control terminal, and the second terminal of the tenth transistor is electrically connected to the gate of the eighth transistor.

8. The scanning circuit according to claim 1, characterized in that, The second output module includes: a third output unit, used to respond to the potential of the first output control terminal and output the third clock signal as the second scan signal; The fourth output unit is used to respond to the potential of the second output control terminal and output the second potential signal as the second scan signal.

9. The scanning circuit according to claim 8, characterized in that, The third output unit includes an eleventh transistor and a third capacitor; the gate of the eleventh transistor is electrically connected to the first output control terminal and the first terminal of the third capacitor, respectively, and the first terminal of the eleventh transistor is connected to the third clock signal; the second terminal of the eleventh transistor is electrically connected to the second terminal of the third capacitor and serves as the output terminal of the second output module. The fourth output unit includes: a twelfth transistor; the gate of the twelfth transistor is electrically connected to the second output control terminal, the first terminal of the twelfth transistor is connected to the second potential signal, and the second terminal of the twelfth transistor is electrically connected to the output terminal of the second output module.

10. The scanning circuit according to claim 9, characterized in that, The third output unit further includes a thirteenth transistor; the gate of the thirteenth transistor is connected to the first potential signal, the first terminal of the thirteenth transistor is electrically connected to the first output control terminal, and the second terminal of the thirteenth transistor is electrically connected to the gate of the eleventh transistor.

11. A method for driving a scanning circuit, characterized in that, For driving the scanning circuit according to any one of claims 1-10; the driving method includes: In the first output stage, the first clock signal controls the trigger input module to transmit the trigger input signal to the first output control terminal; the node inter-control module responds to the potential of the first clock signal and the first output control terminal, and transmits the fourth clock signal to the second output control terminal; the first output module responds to the potential of the first output control terminal and outputs the second clock signal as the first scan signal; the second output module responds to the potential of the first output control terminal and outputs the third clock signal as the second scan signal. In the second output stage, the first clock signal and the fourth clock signal control the potential control module to transmit the first potential signal to the second output control terminal; the node mutual control module responds to the potential of the second clock signal and the second output control terminal and transmits the second potential signal to the first output control terminal; the first output module responds to the potential of the second output control terminal and outputs the second potential signal as a first scan signal; the second output module responds to the potential of the second output control terminal and outputs the second potential signal as a second scan signal.

12. A display panel, characterized in that, include: A cascaded multi-stage scanning circuit as described in any one of claims 1-10.

13. The display panel according to claim 12, characterized in that, The second scan signal output by this stage scan circuit serves as the trigger input signal for the next stage scan circuit. The display panel further includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; The first clock terminal of the odd-level scanning circuit is electrically connected to the first clock signal line, the second clock terminal is electrically connected to the second clock signal line, the third clock terminal is electrically connected to the third clock signal line, and the fourth clock terminal is electrically connected to the fourth clock signal line. The first clock terminal of the even-numbered scanning circuit is electrically connected to the third clock signal line, the second clock terminal is electrically connected to the fourth clock signal line, the third clock terminal is electrically connected to the first clock signal line, and the fourth clock terminal is electrically connected to the second clock signal line.

Images