Display device and electronic equipment

Abstract

A display device and an electronic appliance capable of improving image quality are provided. One embodiment of the present application is a display device in which an adding circuit having a function of performing an addition operation on a plurality of data supplied from a source driver is provided inside and outside a display region. Part of the constituent elements of the adding circuit is arranged in the display region in a divided manner. Thus, the addition operation on the data can be performed efficiently while relaxing the restriction on the size of the constituent elements included in the adding circuit. Furthermore, by providing other constituent elements included in the adding circuit outside the display region, the number of wirings inside the display region can be reduced and the aperture ratio of a pixel can be improved.

Description

[0001] This divisional application is based on a patent application No. 201980042063.4 filed in China on June 25, 2019, with the title of “Display device and electronic device”. TECHNICAL FIELD

[0002] One embodiment of the present application relates to a display device.

[0003] Note that one embodiment of the present application is not limited to the technical field described above. One embodiment of the application disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present application relates to a process, a machine, manufacture, or a composition of matter. Thus, more specifically, examples of a technical field of one embodiment of the application disclosed in this specification to which one embodiment of the present application pertains can be a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, a method for driving any of them, or a method for manufacturing any of them.

[0004] Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of the semiconductor device. A storage device, a display device, an imaging device, and an electronic device may BACKGROUND

[0005] A technique for forming a transistor using a metal oxide formed over a substrate has attracted attention. For example, Patent Document 1 and Patent Document 2 disclose a technique in which a transistor using zinc oxide or an In-Ga-Zn-based oxide is used as a switching element or the like of a pixel of a display device.

[0006] In addition, Patent Document 3 discloses a storage device having a structure in which a transistor with extremely low off-state current is used for a storage unit.

[0007] [Prior Art Document]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Published Patent Application No. 2007-123861

[0010] [Patent Document 2] Japanese Published Patent Application No. 2007-96055

[0011] [Patent Document 3] Japanese Published Patent Application No. 2011-119674 SUMMARY

[0012] Technical problem to be solved by the invention

[0013] A high-resolution display device capable of displaying at 8K4K (number of pixels: 7680 x 4320) resolution or higher has been developed. Furthermore, introduction of an HDR (High Dynamic Range) display technique for improving image quality by luminance adjustment has also been advanced.

[0014] In order to perform clear gradation display, it is preferable to operate a display element using a wide range of data potentials. On the other hand, for example, the output voltage of a source driver for a liquid crystal display device is about 10 V to 20 V, and in the case where a higher voltage is supplied to a display element, a source driver with high output must be used. A source driver with high output has high power consumption, and sometimes a new driver IC has to be developed.

[0015] Therefore, one of objects of one embodiment of the present application is to provide a display device capable of improving image quality. Another one of objects of one embodiment of the present application is to provide a display device capable of supplying a voltage higher than the output voltage of a source driver to a display element. Another one of objects of one embodiment of the present application is to provide a display device capable of improving luminance of a displayed image. Another one of objects of one embodiment of the present application is to provide a display device capable of improving aperture ratio of a pixel.

[0016] Another one of objects of one embodiment of the present application is to provide a display device with low power consumption. Another one of objects of one embodiment of the present application is to provide a display device with high reliability. Another one of objects of one embodiment of the present application is to provide a novel display device. Another one of objects of one embodiment of the present application is to provide a driving method of the above display device. Another one of objects of one embodiment of the present application is to provide a novel semiconductor device.

[0017] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present application does not necessarily achieve all the above objects. Furthermore, an object other than the above can be apparent from the description, drawings, and the like, and can be extracted from the description, drawings, and the like.

[0018] Means for solving the technical problem

[0019] One embodiment of the present application relates to a display device capable of improving image quality.

[0020] One aspect of the present invention is a display device including pixels and a first circuit. The pixels are electrically connected to the first circuit. The first circuit has the function of adding second data to first data to generate third data. The pixels have the function of adding third data to first data to generate fourth data and displaying the fourth data.

[0021] Another aspect of the present invention is a display device including pixels and a first circuit, wherein the pixels are electrically connected to the first circuit, the first circuit has the function of adding second data to first data to generate third data, and the pixels have the function of adding third data to third data to generate fourth data and displaying the fourth data.

[0022] The first circuit may include a first transistor, a second transistor, a third transistor, and a first capacitor. One of the source and drain of the first transistor may be electrically connected to a pixel. One of the source and drain of the first transistor may be electrically connected to one electrode of the first capacitor. The other electrode of the first capacitor may be electrically connected to one of the source and drain of the second transistor. One of the source and drain of the second transistor may be electrically connected to one of the source and drain of the third transistor. The other of the source and drain of the first transistor may be electrically connected to the other of the source and drain of the second transistor.

[0023] The first capacitor may include multiple second capacitors, which may be connected in parallel.

[0024] A pixel may include a fourth transistor, a fifth transistor, a sixth transistor, a third capacitor, and a second circuit. One of the source and drain of the fourth transistor may be electrically connected to one electrode of the third capacitor. One electrode of the third capacitor may be electrically connected to the second circuit. The other electrode of the third capacitor may be electrically connected to one of the source and drain of the fifth transistor. One of the source and drain of the fifth transistor may be electrically connected to one of the source and drain of the sixth transistor. The other of the source and drain of the fourth transistor may be electrically connected to a first circuit. The second circuit may include a display device.

[0025] The second circuit may include a seventh transistor, a fourth capacitor, and a light-emitting device as a display device. The gate of the seventh transistor may be electrically connected to the other of the source and drain of the fourth transistor. One of the source and drain of the seventh transistor may be electrically connected to one electrode of the light-emitting device. One electrode of the light-emitting device may be electrically connected to one electrode of the fourth capacitor. The other electrode of the fourth capacitor may be electrically connected to the gate of the seventh transistor.

[0026] Further, the second circuit can include a liquid crystal device as a display device, and one of the electrodes of the liquid crystal device can be electrically connected to one of the source and drain of the fourth transistor. Further, the second circuit can include a fifth capacitor, and one of the electrodes of the fifth capacitor can be electrically connected to one of the electrodes of the liquid crystal device.

[0027] It is preferable that the transistors included in the first circuit and the pixel include a metal oxide including In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) in a channel formation region.

[0028] The channel width of the transistor included in the first circuit is preferably larger than the channel width of the transistor included in the pixel.

[0029] Effects of Invention

[0030] By using one embodiment of the present application, a display device capable of improving image quality can be provided. Further, a display device capable of supplying a voltage higher than an output voltage of a source driver to a display device can be provided. Further, a display device capable of improving luminance of a displayed image can be provided. Further, a display device capable of improving aperture ratio of a pixel can be provided.

[0031] Further, a display device with low power consumption can be provided. Further, a display device with high reliability can be provided. Further, a novel display device or the like can be provided. Further, a method for operating the above display device can be provided. Further, a novel semiconductor device or the like can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0032] [ Figure 1 ] Figure 1 is a diagram illustrating a display device.

[0033] [ Figure 2 ] Figure 2 is a diagram illustrating an addition circuit and a pixel.

[0034] [Fig. 3] Figures 3A-3F is a diagram illustrating an addition circuit and a pixel.

[0035] [ Figure 4 ] Figure 4 is a diagram illustrating an addition circuit and a pixel.

[0036] [ Figure 5 ] Figure 5 is a timing chart illustrating operation of an addition circuit and a pixel.

[0037] [ Figure 6 ] Figure 6 is a timing chart illustrating operation of an addition circuit and a pixel.

[0038] [Fig. 7] Figures 7A-7D is a diagram illustrating a circuit block.

[0039] [Fig. 8] Figures 8A-8D is a diagram illustrating a circuit block.

[0040] [Fig. 9] Figures 9A-9C is a diagram illustrating a circuit block.

[0041] [ Figure 10 ] Figure 10 is a diagram illustrating an addition circuit and a pixel.

[0042] [ Figure 11 ] Figure 11 is a diagram illustrating a structure of an addition circuit and a pixel for simulation.

[0043] [ Figure 12 ] Figure 12 is a timing chart for simulation.

[0044] [ Figure 13 ] Figure 13 is a timing chart for simulation.

[0045] [ Figure 14 ] Figure 14 is a diagram illustrating a result of simulation.

[0046] [ Figure 15 ] Figure 15 is a diagram illustrating a result of simulation.

[0047] [Fig. 16] Figures 16A-16C is a diagram illustrating a display device.

[0048] [Fig. 17] Figure 17A and Figure 17B are diagrams illustrating a touch panel.

[0049] [Fig. 18] Figure 18A and Figure 18B are diagrams illustrating a display device.

[0050] [ Figure 19 ] Figure 19 is a diagram illustrating a display device.

[0051] [Fig. 20] Figure 20A and Figure 20B are diagrams illustrating a display device.

[0052] [Fig. 21] Figure 21A and Figure 21B are diagrams illustrating a display device.

[0053] [Fig. 22] Figures 22A-22E is a diagram illustrating a display device.

[0054] [FIG. 23] Figures 23A1-23C2 is a diagram illustrating a transistor.

[0055] [FIG. 24] Figures 24A1-24C2 is a diagram illustrating a transistor.

[0056] [FIG. 25] Figures 25A1-25C2 is a diagram illustrating a transistor.

[0057] [FIG. 26] Figures 26A1-26C2 is a diagram illustrating a transistor.

[0058] [FIG. 27] Figures 27A-27F is a diagram illustrating an electronic device.

[0059] Embodiment of Invention

[0060] Embodiments are described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments, and it is readily apparent to those skilled in the art that a variety of changes can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments. Note that, in the structures of the invention described below, the same portions or portions having similar functions are denoted with the same reference numerals in different drawings, and repetitive description is omitted. Note that, in some cases, the hatching of the same components is omitted or changed appropriately in different drawings.

[0061] In addition, even when a circuit diagram shows one element, the element can be formed using a plurality of elements if there is no problem in function. For example, a plurality of transistors used as a switch can be connected in series or in parallel. Further, a capacitor can be divided and arranged at a plurality of positions.

[0062] Further, one conductor has a plurality of functions such as a wiring, an electrode, and a terminal in some cases, and a plurality of names are used for the same element in some cases in this specification. In addition, even when a circuit diagram shows a direct connection between elements, the elements are actually connected through a plurality of conductors in some cases, and such a structure is included in the category of the direct connection in this specification.

[0063] (Embodiment 1)

[0064] In this embodiment, a display device of one embodiment of the present invention is described with reference to drawings.

[0065] One embodiment of the present invention is a display device including a circuit having a function of performing addition of data (hereinafter referred to as an addition circuit) and a pixel also having a function of performing addition of data.

[0066] The addition circuit has a function of adding data supplied from the source driver. In addition, the pixel has a function of adding data supplied from the addition circuit. Thus, the display device of one embodiment of the present application can generate a voltage which is approximately several times the output voltage of the source driver and supply the voltage to the display element.

[0067] The addition circuit is electrically connected to the pixels in the column direction of the display region, and part of the constituent elements thereof can be arranged in the pixel region in a divided manner. Thus, the size of the constituent elements included in the addition circuit can be relaxed, and data can be added efficiently. Furthermore, by arranging other constituent elements included in the addition circuit outside the display region, the number of wirings in the inside of the display region can be reduced and the aperture ratio of the pixel can be increased.

[0068] Figure 1 FIG. 1 is a diagram illustrating a display device of one embodiment of the present application. The display device includes pixels 10 arranged in a column direction and a row direction, a source driver 12, a gate driver 13, and a circuit 11. The source driver 12 is electrically connected to the circuit 11. The gate driver 13 is electrically connected to the pixels 10. The circuit 11 is electrically connected to the pixels 10. Note that the display device includes a plurality of circuits 11 arranged in the column direction. Figure 1 An example in which one gate driver 13 is provided along one side of the display region 15 is illustrated, but another gate driver can also be provided along the other side opposite to the side, and the pixels 10 can be driven by the two gate drivers.

[0069] The circuit 11 can be provided on each column and electrically connected to all the pixels 10 arranged on the same column. Furthermore, constituent elements of the circuit 11 can be provided inside and outside the display region.

[0070] The circuit 11 is an addition circuit and has a function of generating third data by capacitively coupling a first data supplied from the source driver 12 with a second data.

[0071] The pixel 10 includes a circuit 20 and a circuit block 110. The circuit 20 has a function of generating fourth data by capacitively coupling a first data supplied from the addition circuit with a third data. In addition, the circuit 20 has a function of generating fifth data by capacitively coupling the third data supplied from the addition circuit with the third data. The circuit block 110 includes a display element and has a function of displaying using the display element in accordance with the fourth data or the fifth data supplied from the circuit 20.

[0072] Figure 2 FIG. 2 is a diagram illustrating the circuit 11 and the pixels 10 arranged on the same column (the m-th column) of the display device illustrated in FIG. 1. Figure 1 FIG. 2 is a diagram illustrating the circuit 11 and the pixels 10 arranged on the same column (the m-th column) of the display device illustrated in FIG. 1.

[0073] The circuit 11 can include the transistor 101, the transistor 102, the transistor 103, and the capacitor 107. One of the source and drain of the transistor 101 is electrically connected to one electrode of the capacitor 107. The other electrode of the capacitor 107 is electrically connected to one of the source and drain of the transistor 102. One of the source and drain of the transistor 102 is electrically connected to one electrode of the transistor 103.

[0074] Here, the capacitor 107 can be constituted by a plurality of capacitors 108 connected in parallel. By providing the capacitors 108 in a manner dispersed in the display region, it is easy to increase the total area of the capacitor 107. Further, the area occupied by the circuit 11 outside the display region can be reduced, and narrow bezel can be achieved. In addition, several capacitors 108 can also be provided outside the display region. Further, the capacitors 108 can also not be provided in all the pixel regions. By adjusting the number of the capacitors 108 connected in parallel, the capacitance value of the capacitor 107 can be made to be a desired value.

[0075] The capacitor 108 can have a structure in which the wiring 125 is used as one electrode and another wiring overlapping the wiring 125 is used as the other electrode. Thus, as shown in FIG. 1B, even if the capacitor 108 is arranged in the pixel region, the aperture ratio does not greatly decrease. Figure 2

[0076] The pixel 10 can have a structure including the circuit 20 and the circuit block 110. In addition, as described above, the capacitor 108 can be provided in the pixel region.

[0077] The circuit 20 can have a structure including the transistor 104, the transistor 105, the transistor 106, and the capacitor 109. One of the source and drain of the transistor 104 is electrically connected to one electrode of the capacitor 109. The other electrode of the capacitor 109 is electrically connected to one of the source and drain of the transistor 105. One of the source and drain of the transistor 105 is electrically connected to one of the source and drain of the transistor 106. One of the source and drain of the transistor 104 is electrically connected to the circuit block 110.

[0078] The circuit block 110 can have a structure of a transistor, a capacitor, a display device, and the like, the details of which will be described later.

[0079] The connection of the constituent elements included in the circuit 11 and the pixel 10 and various wirings is described. The gate of the transistor 101 is electrically connected to the wiring 121. The gate of the transistor 102 is electrically connected to the wiring 122. The gate of the transistor 103 is electrically connected to the wiring 121. The gate of the transistor 104 is electrically connected to the wiring 123. The gate of the transistor 105 is electrically connected to the wiring 124. The gate of the transistor 106 is electrically connected to the wiring 123.

[0080] ​One of the source and drain of the transistor 101 is electrically connected to a wiring 125. The other of the source and drain of the transistor 101 and the other of the source and drain of the transistor 102 are electrically connected to a wiring 126. The other of the source and drain of the transistor 103 and the other of the source and drain of the transistor 106 are electrically connected to a wiring which can supply V ref (0 V, for example, a reference potential).

[0081] The wirings 121, 122, 123 (123[1] to [n]), and the wirings 124 (124[1] to [n]) are used as gate lines. For example, the wirings 121, 122 can be electrically connected to a circuit which controls the operation of the circuit 11. The wirings 123, 124 can be electrically connected to the gate driver 13. The wiring 126 can be electrically connected to the source driver 12 (refer to Figure 1 ).

[0082] Here, the wiring (wiring 125) which connects one of the source and drain of the transistor 101, one electrode of the capacitor 107, and one of the source and drain of the transistor 105 is a node NA. The wiring which connects one of the source and drain of the transistor 102, one of the source and drain of the transistor 103, and the other electrode of the capacitor 107 is a node NB. The wiring which connects one of the source and drain of the transistor 105, one of the source and drain of the transistor 106, and the other electrode of the capacitor 109 is a node NC. The wiring which connects one of the source and drain of the transistor 104, one electrode of the capacitor 109, and the circuit block 110 is a node NP.

[0083] The node NP can be in a floating state, and the display device included in the circuit block 110 operates in accordance with the potential of the node NP.

[0084] In the circuit 11, first, first data (weight: W) is written to the node NA. At this time, the other electrode of the capacitor 107 is supplied with "V ref ", and "W-V ref " is held in the capacitor 107. Next, the node NA is made to be in a floating state, and second data (data: D) is supplied to the node NB.

[0085] At this time, when the capacitance value of the capacitor 107 is C 107 and the capacitance value of the node NA is C NA , the potential of the node NA is W + (C 107 / (C 107 +C NA )) x (D-V ref ). Here, if the value of C 107 is increased and C NA becomes a negligible value, the potential of the node NA is "W+D-Vref Thus, since one embodiment of the present application easily increases the total area of the capacitor 107 and increases the capacitance value (C 107 ), it is possible to efficiently perform an addition operation on data.

[0086] Therefore, if "W" = "D", "V ref " = 0 V, and C 107 is sufficiently larger than C NA , the potential of the node NA approaches "2D". That is, it is possible to supply the third data ("2D") to the node NA, which is a potential that is about twice the output of the source driver 12.

[0087] In addition, in the pixel 10, when the first data "W" is written to the node NA, "W" is written to the node NP. At this time, "V ref " is supplied to the other electrode of the capacitor 109, and the capacitor 109 is held at "W-V ref ". Subsequently, the node NP is made to be in a floating state, and the third data ("2D") is supplied to the node NC.

[0088] At this time, the capacitance value of the capacitor 109 is C 109 , and the capacitance value of the node NP is C NP . Therefore, the potential of the node NP is W + (C 109 / (C 109 +C NP )) x (2D-V ref ). Here, if the value of C 109 is increased and C NP becomes a negligible value, the potential of the node NP is "W + 2D - V ref ".

[0089] Therefore, if "W" = "D", "V ref " = 0 V, and C 109 is sufficiently larger than C NP , the potential of the node NP approaches "D + 2D" = "3D". That is, it is possible to supply the fourth data ("3D") to the node NP, which is a potential that is about three times the output of the source driver 12.

[0090] Furthermore, the pixel 10 can perform an operation different from the above. When the third data "2D" is written to the node NA, "2D" is written to the node NP. At this time, "V ref " is supplied to the other electrode of the capacitor 109, and the capacitor 109 is held at "2D-V ref ". Subsequently, the node NP is made to be in a floating state, and the third data ("2D") is supplied to the node NC.

[0091] At this time, the capacitance value of the capacitor 109 is C 109 The capacitance value of the node NP is C NP At this time, the potential of the node NP is 2D + (C 109 / (C 109 +C NP )) x (2D - V ref ). Here, if the value of C 109 is increased and C NP becomes a negligible value, the potential of the node NP is "2D + 2D - V ref ".

[0092] Therefore, if "W" = "D", "V ref " = 0 V, and C 109 is sufficiently larger than C NP , the potential of the node NP approaches "2D + 2D" = "4D". That is, the fourth data ("4D") which is a potential about four times as large as the output of the source driver 12 can be supplied to the node NP.

[0093] By this action, a high voltage can be generated even if a general driver IC is used. For example, a liquid crystal device which requires a high voltage when controlling the gradation or the like can be driven. In addition, the voltage supplied from the source driver 12 to drive a general liquid crystal device, a light emitting device, or the like can be reduced to about 1 / 3 to 1 / 4, and thus the display device can be made low in power consumption.

[0094] Further, as the first data (weight: W), correction data can also be supplied. For example, by adding luminance correction data to the image data, a deviation in luminance unique to the display device can be corrected. Further, since the luminance can be corrected for each pixel, it can be used for HDR display. In addition, in the case where a light emitting device is used as the display device, the display quality is affected by a threshold voltage deviation of a driving transistor, and thus threshold voltage correction data of the transistor can also be supplied as the first data (weight: W) to improve the display quality. Note that the first data (weight: W) and the second data (data: D) can also be exchanged with each other.

[0095] In one embodiment of the present application, as described above, the data potential generated in the circuit 11 is supplied to the predetermined pixel 10 to determine the potential of the node NP. By sequentially performing such an operation on the pixels 10 [m, 1] to [m, n], the potential of the node NP of each pixel 10 can be determined. That is, different image data can be supplied to each pixel 10.

[0096] The nodes NA, NB, NC, and NP are used as storage nodes. Data can be written to each node by turning on the transistor connected to the node. Further, the data can be held in each node by turning off the transistor. By using a transistor having extremely low off-state current as the transistor, leakage current can be suppressed, and thus the potential of each node can be held for a long time. The transistor can use, for example, a transistor including a metal oxide in a channel formation region (hereinafter referred to as an OS transistor).

[0097] Specifically, as any or all of the transistors 101, 102, 103, 104, 105, and 106, an OS transistor is preferably used. Further, an OS transistor can be used for the constituent elements included in the circuit block 110. Alternatively, when operation is performed in a range where the amount of leakage current is allowed, a transistor including Si in a channel formation region (hereinafter referred to as an Si transistor) can be used. Further, an OS transistor and an Si transistor can be used in combination. As the Si transistor, a transistor including amorphous silicon, a transistor including crystalline silicon (microcrystalline silicon, low-temperature polysilicon, monocrystalline silicon), or the like can be given.

[0098] As a semiconductor material for an OS transistor, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more, and further preferably 3 eV or more can be used. Typical examples of the metal oxide include an oxide semiconductor containing indium, and for example, a CAAC-OS or a CAC-OS described later can be used. In a CAAC-OS, atoms constituting a crystal are stable, and the CAAC-OS is suitable for a transistor or the like in which reliability is emphasized. A CAC-OS has a high mobility characteristic and is suitable for a transistor or the like which is driven at high speed.

[0099] Since the semiconductor layer of an OS transistor has a large band gap, the OS transistor has extremely low off-state current characteristics of several yA / μm (current value per channel width of 1 μm). Unlike an Si transistor, an OS transistor has characteristics in which collision ionization, avalanche breakdown, short channel effects, and the like do not occur, and thus a highly reliable circuit can be formed. Further, an electric characteristic deviation due to unevenness in crystallinity, which is caused by an Si transistor, is less likely to occur in an OS transistor.

[0100] As a semiconductor layer in an OS transistor, for example, a film represented by "In-M-Zn-based oxide" containing indium, zinc, and M (aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium, or the like) can be used.

[0101] When the oxide semiconductor that constitutes the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of metal elements of a sputtering target used for forming an In-M-Zn oxide film is preferably In > M and Zn > M. The atomic ratio of metal elements of such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, or the like. Note that the atomic ratio of the formed semiconductor layer can vary within a range of ±40 % of the atomic ratio of metal elements of the above sputtering target.

[0102] As the semiconductor layer, an oxide semiconductor having a low carrier density is used. For example, as the semiconductor layer, an oxide semiconductor having a carrier density of 1 x 10 17 / cm 3 Hereinafter, it is preferable that the carrier density be 1 x 10 15 / cm 3 Hereinafter, it is more preferable that the carrier density be 1 x 10 13 / cm 3 Hereinafter, it is further preferable that the carrier density be 1 x 10 11 / cm 3 Hereinafter, it is still further preferable that the carrier density be less than 1 x 10 10 / cm 3 and be 1 x 10 -9 / cm 3 The above oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and thus can be said to have stable characteristics.

[0103] Note that the present application is not limited to the above description, and a material having a suitable composition can be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of a transistor required. In addition, the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, and the like of the semiconductor layer are preferably set as appropriate so that the semiconductor characteristics of a transistor required are obtained.

[0104] When the oxide semiconductor that constitutes the semiconductor layer contains silicon or carbon, which is one of Group 14 elements, the number of oxygen vacancies increases, which makes the semiconductor layer n-type. Thus, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to be 2 x 10 18 atoms / cm 3 Hereinafter, it is preferable that the concentration of silicon or carbon be 2 x 1017 atoms / cm 3 The following.

[0105] In addition, when an alkali metal and an alkaline earth metal are bonded to the oxide semiconductor, carriers are sometimes generated, which increases the off-state current of the transistor. Therefore, the concentration of an alkali metal or an alkaline earth metal in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to be 1 x 10 18 atoms / cm 3 The following is preferable: 2 x 10 16 atoms / cm 3 The following.

[0106] In addition, when the oxide semiconductor included in the semiconductor layer contains nitrogen, electrons serving as carriers are generated, the carrier density increases, and the oxide semiconductor easily becomes n-type. As a result, a transistor using an oxide semiconductor containing nitrogen easily has a normally-on characteristic. Therefore, the concentration of nitrogen in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5 x 10 18 atoms / cm 3 The following.

[0107] In addition, when the oxide semiconductor included in the semiconductor layer contains hydrogen, hydrogen reacts with oxygen bonded to a metal atom to generate water, and thus oxygen vacancies are sometimes formed in the oxide semiconductor. In the case where the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Furthermore, a defect in which hydrogen enters an oxygen vacancy is sometimes used as a donor to generate electrons serving as carriers. In addition, a part of hydrogen is sometimes bonded to oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen easily has a normally-on characteristic.

[0108] A defect in which hydrogen enters an oxygen vacancy can be used as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Therefore, in the oxide semiconductor, evaluation is sometimes performed not in terms of the donor concentration but in terms of the carrier concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, the carrier concentration in a state where an electric field is not applied is sometimes used instead of the donor concentration. That is, the "carrier concentration" described in this specification and the like can be referred to as the "donor concentration".

[0109] Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by secondary ion mass spectrometry is lower than 1 x 10 20 atoms / cm 3 , preferably lower than 1 x 10 19 atoms / cm 3 , more preferably lower than 5 x 1018 atoms / cm 3 , further preferably lower than 1 x 10 18 atoms / cm 3 By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be given.

[0110] In addition, the semiconductor layer can have a non-single-crystal structure, for example. The non-single-crystal structure includes a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a c-axis aligned crystal, a polycrystal structure, a microcrystal structure, or an amorphous structure, for example. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0111] The oxide semiconductor film of the amorphous structure has, for example, an atomic arrangement without order and does not have a crystal component. Alternatively, the oxide film of the amorphous structure is, for example, a complete amorphous structure and does not have a crystal portion.

[0112] Further, the semiconductor layer can be a mixed film of two or more of a region having an amorphous structure, a region having a microcrystal structure, a region having a polycrystal structure, a region having a CAAC-OS, and a region having a single-crystal structure. The mixed film has, for example, a single-layer structure or a stacked-layer structure including two or more of the above regions.

[0113] One embodiment of a CAC (Cloud-Aligned Composite)-OS of a non-single-crystal semiconductor layer will be described below.

[0114] The CAC-OS refers to a structure in which elements included in an oxide semiconductor are unevenly distributed, for example. The size of a material including elements unevenly distributed is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a size close thereto. Note that in the following, a state in which one or a plurality of metal elements are unevenly distributed in an oxide semiconductor and a region including the metal elements is mixed in a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a size close thereto, is referred to as a mosaic or patch-like state.

[0115] The oxide semiconductor preferably contains at least indium. In particular, indium and zinc are preferably contained. In addition to the above, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, and the like can be further contained.

[0116] For example, CAC-OS (in CAC-OS, the In-Ga-Zn oxide can be referred to as CAC-IGZO, in particular) means that the material is divided into an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or an indium-zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) and a gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or a gallium-zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) and the like, and the InO X1 or In X2 Zn Y2 O Z2 are uniformly distributed in the film (hereinafter, also referred to as cloud-like).

[0117] In other words, CAC-OS is a composite oxide semiconductor having a region in which GaO X3 is the main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is the main component mixed together. In this specification, for example, when the atomic ratio of In to element M in a first region is higher than the atomic ratio of In to element M in a second region, the In concentration in the first region is higher than that in the second region.

[0118] Note that IGZO is a general term, and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, an InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number) is given.

[0119] The above-described crystalline compound has a single crystal structure, a polycrystal structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in the a-b plane in a non-aligned manner.

[0120] On the other hand, the CAC-OS is related to the material composition of the oxide semiconductor. The CAC-OS refers to a composition in which a region mainly containing Ga and a region mainly containing In are observed in some parts and dispersed in a mosaic pattern. Thus, in the CAC-OS, the crystal structure is not a primary factor.

[0121] The CAC-OS does not include a stacked structure of two or more films having different compositions. For example, it does not include a structure of two layers of a film mainly containing In and a film mainly containing Ga.

[0122] Note that a clear boundary between a region mainly containing GaO X3 and a region mainly containing In X2 Zn Y2 O Z2 or InO X1 is not observed.

[0123] In the case where one or more kinds of metal elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained in the CAC-OS in place of gallium, the CAC-OS refers to a composition in which a region mainly containing the metal element and a region mainly containing In are observed in some parts and dispersed in a mosaic pattern.

[0124] The CAC-OS can be formed, for example, by a sputtering method without intentionally heating a substrate. In the case where the CAC-OS is formed by a sputtering method, as a deposition gas, one or more kinds selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas can be used. Further, it is preferable that the proportion of the flow rate of the oxygen gas in the total flow rate of the deposition gas at the time of deposition be lower, for example, the proportion of the flow rate of the oxygen gas be set to be higher than or equal to 0 % and lower than 30 %, preferably higher than or equal to 0 % and lower than or equal to 10 %.

[0125] The CAC-OS has a characteristic that a clear peak is not observed when measured by an Out-of-plane method of one of X-ray diffraction (XRD) measurement methods using θ / 2θ scanning. That is, according to the X-ray diffraction measurement, it is found that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0126] In addition, in an electron diffraction pattern of the CAC-OS obtained by irradiation of an electron beam with a beam diameter of 1 nm (also referred to as a nanobeam), a bright ring-shaped region (ring-shaped region) and a plurality of bright spots in the ring-shaped region are observed. Thus, from the electron diffraction pattern, it is known that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

[0127] In addition, for example, in the CAC-OS of an In-Ga-Zn oxide, from an EDX mapping image obtained by energy dispersive X-ray spectroscopy (EDX), it is confirmed that a region having GaO X3 as a main component and a region having In X2 Zn Y2 O Z2 or InO X1 as a main component are unevenly distributed and mixed.

[0128] The structure of the CAC-OS is different from that of the IGZO compound in which metal elements are uniformly distributed, and has a property different from that of the IGZO compound. In other words, the CAC-OS has a structure in which a region having GaO X3 or the like as a main component and a region having In X2 Zn Y2 O Z2 or InO X1 as a main component are separated from each other and the regions having each element as a main component are in a mosaic pattern.

[0129] Here, the region having In X2 Zn Y2 O Z2 or InO X1 as a main component has higher conductivity than the region having GaO X3 or the like as a main component. In other words, when a carrier flows through the region having In X2 Zn Y2 O Z2 or InO X1 as a main component, the conductivity of an oxide semiconductor is exhibited. Thus, when the region having In X2 Zn Y2 O Z2 or InO X1 as a main component is distributed in a cloud shape in the oxide semiconductor, a high field effect mobility (μ) can be achieved.

[0130] On the other hand, the region having GaO X3 or the like as a main component has higher insulating properties than the region having In X2Zn Y2 O Z2 or InO X1 region. In other words, when a region mainly containing GaO X3 , etc. is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0131] Therefore, when CAC-OS is used for a semiconductor element, high on-state current (I X3 ) and high field-effect mobility (μ) can be achieved by the complementary action of the insulating properties of GaO X2 , etc. and the conductivity of In Y2 Zn Z2 O X1 or InO on .

[0132] In addition, a semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is suitable for a material for constituting various semiconductor devices.

[0133] Further, in the display device of one embodiment of the present application, as Figure 3A indicated, components other than the capacitor 107 of the circuit 11 can be provided in the source driver 12. With this structure, narrow bezel design can be achieved.

[0134] When the pixel circuit is monolithically integrated with the source driver 12 on a substrate, a stacked structure having a region in which components of the source driver 12 and the circuit 11 overlap each other can be used. With this structure, the design freedom and electrical characteristics of the components of the circuit 11 can be improved.

[0135] Further, although Figure 1 an example in which the circuit 11 is provided over each column is described, as Figure 3B indicated, a selection circuit 16 can be provided between the circuit 11 and the pixel 10 and one circuit 11 can be used to write data to the pixels of a plurality of columns. With this structure, the number of circuits 11 can be reduced, and thus narrow bezel design can be achieved. Note that although Figure 3B an example in which three columns of pixels are written using one circuit 11 in combination with one selection circuit 16 is described, the number of columns can be determined within the range allowed for the writing time.

[0136] Further, as Figure 3C indicated, the capacitor 107 can not be provided in the display region and can be provided outside the display region together with the circuit 11. In this structure, a stacked structure having a region in which the circuit 11 and the capacitor 107 overlap each other can be used. With this structure, the aperture ratio of the pixel 10 can be improved.

[0137] Further, as shown in FIG. 1 1, the capacitor 107 can be mounted in the source driver 12. In this structure, a stacked structure having an overlapping region of the source driver 12 and the capacitor 107 can be employed. By employing this structure, narrow frame can be achieved. Figure 3D

[0138] Further, as shown in FIG. 12, the capacitor 107 can be provided outside the display region, and the circuit 11 can be mounted in the source driver 12. In this structure, a stacked structure having an overlapping region of the source driver 12 and the circuit 11 can be employed. By employing this structure, narrow frame can be achieved and the aperture ratio of the pixel can be improved. Figure 3E

[0139] Further, as shown in FIG. 13, the circuit 11 and the capacitor 107 can be mounted in the source driver 12. In this structure, a stacked structure having an overlapping region of the source driver 12, the circuit 11 and the capacitor 107 can be employed. Alternatively, a stacked structure having overlapping regions of the source driver 12, the circuit 11 and the capacitor 107 can be employed. By employing this structure, narrow frame can be achieved. Figure 3F

[0140] Since the transistors 101, 102 and 103 included in the circuit 11 are provided outside the display region, they are not easily limited in size, and can have a larger channel width than the transistors provided in the pixel. By using a transistor having a large channel width, the charge / discharge time of the wiring 125 and the like can be shortened, and thus the frame rate can be easily improved. Further, it is easy to apply to a high-definition display having a large number of pixels and a short horizontal period.

[0141] Further, by using an OS transistor as the transistors 101, 102 and 103, the withstand voltage of the circuit 11 can be improved, and stable operation can be performed even when the voltage generated by performing addition on data is several tens of V. Alternatively, when the transistors 101, 102 and 103 are Si transistors provided in an IC chip, higher-speed operation can be performed. Note that in the case where the transistors 101, 102 and 103 are provided in an IC chip, the transistors can also be OS transistors.

[0142] As shown in FIG. 14, the circuit 11 can be provided in a region along one side of the display region 15 and in a region along the other side opposite to the one side. Figure 4

[0143] ​​​​Here, the circuit 11 provided at one side of the display region 15 is the circuit 11a. The operation of the circuit 11a is controlled by signals supplied from the wirings 121a, 122a. The circuit 11a is electrically connected to the source driver 12a. Further, the circuit 11 provided at the other side opposite to the side of the display region 15 is the circuit 11b. The operation of the circuit 11b is controlled by signals supplied from the wirings 121b, 122b. In addition, the circuit 11b is electrically connected to the source driver 12b.

[0144] The circuit 11a and the circuit 11b operate in a manner that the same data is output at the same timing. That is, the same data is output from the source drivers 12a, 12b at the same timing, and the same operation signal is supplied to the wirings 121a and 121b or the wirings 122a and 122b at the same timing.

[0145] By performing the above operation, the circuit 11a and the circuit 11b can be operated simultaneously and output the same data to the wiring 125. Thereby, the charging and discharging of the wiring 125 can be performed at high speed, and it is easy to cope with a display device in which the number of pixels is large and the horizontal period is short, a large display device in which the parasitic capacitance of the wiring 125 is large, and the like.

[0146] Next, the operation of the circuit 11 and the pixel 10 will be described with reference to the timing chart shown in FIG. 6. Figure 5 The timing chart shown in FIG. 6 explains a method of supplying a data potential which is about three times as large as the data potential output from the source driver to the display device by the operation of the circuit 11 and the pixel 10.

[0147] Note that, in the following description, a high potential is denoted as "H", and a low potential is denoted as "L". Further, the weight supplied to the pixel 10[1] is denoted as "W[1]", and the image data is denoted as "D[1]". The weight supplied to the pixel 10[2] is denoted as "W[2]", and the image data is denoted as "D[2]". As "V ref ", for example, 0 V, a GND potential, or a specific reference potential can be used.

[0148] Note that, here, detailed changes caused by the structure of the circuit, the timing of the operation, and the like are not taken into account in the distribution, coupling, or loss of the potential. The change in the potential caused by the capacitive coupling using the capacitor depends on the capacitance ratio of the capacitor and the constituent elements connected thereto, but for the sake of convenience of explanation, the capacitance values of the constituent elements are assumed to be sufficiently small values.

[0149] At time Tl, when "W[1]" is supplied to the wiring 126, and the potential of the wiring 121 is "H", the potential of the wiring 122 is "L", the potential of the wiring 123[1] is "H", and the potential of the wiring 124[1] is "L", the transistor 103 is turned on, and the potential of the node NB is "V ref ". This operation is a reset operation for performing the following addition operation (capacitive coupling operation).

[0150] Additionally, transistors 101 and 104 are turned on, and the potential of wiring 126 is written to node NA. Furthermore, the potential of node NA is written to node NP[1]. This operation is the writing of weights in circuit 11 and pixel 10, and the potentials of nodes NA and NP[1] are "W[1]".

[0151] At time T2, when the potential of wiring 121 is “L”, the potential of wiring 122 is “L”, the potential of wiring 123[1] is “L”, and the potential of wiring 124[1] is “L”, transistors 101, 103, and 104 are not turned on. At this time, node NA and node NP[1] remain “W[1]”. In addition, capacitors 107 and 109 remain “W[1]-V”. ref ".

[0152] At time T3, when “D[1]” is supplied to wiring 126 and the potential of wiring 121 is “L”, the potential of wiring 122 is “H”, the potential of wiring 123[1] is “L”, and the potential of wiring 124[1] is “H”, transistor 102 is turned on. At this time, the potential of node NB is “D[1]”, and “D[1]” is added to node NA according to the capacitance ratio of node NB and node NA. This operation is the addition operation of circuit 11, and the potential of node NA is “W[1]+(D[1]-V”. ref )'". At this time, if "V ref If '=0, then the potential of node NA is 'W[1]+D[1]'.

[0153] Furthermore, at pixel 10, transistor 105 is turned on. At this time, the potential of node NC is “W[1]+D[1]'”, and “(W[1]+D[1]')'” is added to node NP[1] according to the capacitance ratio of node NC[1] and node NP[1]. This operation is the additive operation of pixel 10, and the potential of node NP[1] is “W[1]+(W[1]+D[1]'-V”. ref )'". At this time, if "V ref If '=0, then the potential of node NP[1] is "W[1]+(W[1]+D[1]')'". The potential of node NP[1] is supplied to the display device for display.

[0154] Here, when W[1] = D[1], the capacitance of node NA is sufficiently smaller than the capacitance of node NB, and the capacitance of node NP[1] is sufficiently smaller than the capacitance of node NC[1], "W[1] + (W[1] + D[1]')'" is a value close to "3D[1]". Thus, a data potential approximately three times that output by the source driver can be supplied to the display device.

[0155] At time T4, the potentials of the lines 121, 122, 123[l], 124[l] are made "L", the transistors 102, 105 are rendered non-conductive, and the potential of the node NP[l] is held until the operation of the next frame, and the display continues. The above is an explanation of the operation of the pixel 10[l].

[0156] By causing the pixel 10[2] to operate in the same manner at times T5 to T8, display of "W[2]+(W[2]+D[2]')" is performed in the pixel 10[2].

[0157] Next, the operation of the circuit 11 is explained. Figure 6 The timing chart shown in Fig. 6 explains a method of supplying a data potential which is about four times the data potential output from the source driver to the display device by the operation of the circuit 11 and the pixel 10.

[0158] At time Tl, when "W[l]" is supplied to the line 126 and the potential of the line 121 is "H", the potential of the line 122 is "L", the potential of the line 123[l] is "L", and the potential of the line 124[l] is "L", the transistor 103 is rendered conductive, and the potential of the node NB is "V ref ". This operation is a reset operation for the subsequent addition operation (capacitive coupling operation).

[0159] At time T2, when the potential of the line 121 is "L", the potential of the line 122 is "L", the potential of the line 123[l] is "L", and the potential of the line 124[l] is "L", the transistors 101, 103 are rendered non-conductive. At this time, the node NA holds "W[l]". Further, the capacitor 107 holds "W[l]-V ref ". This operation is a write operation of the weight of the circuit 11.

[0160] At time T3, when "D[l]" is supplied to the line 126 and the potential of the line 121 is "L", the potential of the line 122 is "H", the potential of the line 123[l] is "H", and the potential of the line 124[l] is "L", the transistor 102 is rendered conductive. At this time, the potential of the node NB is "D[l]", and "D[l]'" according to the capacitance ratio of the node NB and the node NA is added to the node NA. This operation is an addition operation of the circuit 11, and the potential of the node NA is "W[l]+(D[l]-V ref )". At this time, if "V ref " = 0, the potential of the node NA is "W[l]+D[l]'".

[0161] Further, the transistors 104, 106 are rendered conductive, and the potential of the node NA is written to the node NP[l]. In addition, "V ref" is written into the node NC. This operation is a reset operation for the weight writing operation and the capacitive coupling operation of the pixel 10, and the potential of the node NP[1] is "W[1]+D[1]'".

[0162] At time T4, when the potential of the wiring 121 is "L", the potential of the wiring 122 is "L", the potential of the wiring 123[1] is "L", and the potential of the wiring 124[1] is "L", the transistors 102, 104, and 106 are non-conductive, and the node NP[1] is held at "W[1]+D[1]'".

[0163] At time T5, when the potential of the wiring 121 is "L", the potential of the wiring 122 is "L", the potential of the wiring 123[1] is "L", and the potential of the wiring 124[1] is "H", the transistor 105 is conductive. At this time, the potential "W[1]+D[1]'" of the node NA is written into the node NC[1], and "(W[1]+D[1]')" is added to the node NP[1] according to the capacitance ratio of the node NC[1] to the node NP[1].

[0164] This operation is an addition operation of the pixel 10, and the potential of the node NP[1] is "(W[1]+D[1]')" + "(W[1]+D[1]'" - V ref )'". ref At this time, if "V ref " = 0, the potential of the node NP[1] is "W[1]+D[1]"+"(W[1]+D[1]')"". The potential of the node NP[1] is supplied to the display device to perform display.

[0165] In this case, in the case where W[1] = D[1], the capacitance of the node NA is sufficiently smaller than the capacitance of the node NB, and the capacitance of the node NP[1] is sufficiently smaller than the capacitance of the node NC[1], "W[1]+D[1]"+"(W[1]+D[1]')" is a value close to "4D[1]". Thus, it is possible to supply the display device with a data potential which is about four times the data potential output from the source driver.

[0166] At time T6, when the potentials of the wirings 121, 122, 123[1], and 124[1] are "L", the transistors 102 and 105 are non-conductive, and the potential of the node NP[1] is held until the operation of the next frame to continue display. The above is a description of the operation of the pixel 10[1].

[0167] By causing the pixel 10[2] to perform the same operation at times T7 to T12, it is possible to perform display corresponding to "W[2]+D[2]"+"(W[2]+D[2]')" in the pixel 10[2].

[0168] Figures 7A-7Cis an example of a structure that can be used for the circuit block 110 and that includes a light emitting device as a display element.

[0169] Figure 7A The illustrated structure includes the transistor 111, the capacitor 113, and the light emitting device 114. One of the source and drain of the transistor 111 is electrically connected to one electrode of the light emitting device 114. One electrode of the light emitting device 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to the node NP.

[0170] The other of the source and drain of the transistor 111 is electrically connected to the wiring 128. The other electrode of the light emitting device 114 is electrically connected to the wiring 129. The wirings 128 and 129 have a function of supplying a power supply. For example, the wiring 128 can supply a high-potential power supply. Further, the wiring 129 can supply a low-potential power supply.

[0171] In the structure, Figure 7A In the illustrated structure, current flows through the light emitting device 114 when the potential of the node NP is higher than the threshold voltage of the transistor 111. Thus, the light emitting device 114 sometimes starts to emit light when the weight (W) is written to the node NP.

[0172] In addition, as Figure 7B illustrated, one electrode of the light emitting device 114 can be electrically connected to the wiring 128, and the other electrode of the light emitting device 114 can be electrically connected to the other of the source and drain of the transistor 111. This structure can also be used for other circuit blocks 110 that include the light emitting device 114.

[0173] Figure 7C is a structure in which the transistor 112 is added to the structure of Figure 7A One of the source and drain of the transistor 112 is electrically connected to one of the source and drain of the transistor 111. The other of the source and drain of the transistor 112 is electrically connected to one electrode of the light emitting device 114. The gate of the transistor 112 is electrically connected to the wiring 127. The wiring 127 can have a function of a signal line that controls conduction of the transistor 112.

[0174] In this structure, current flows through the light emitting device 114 when the potential of the node NP is higher than the threshold voltage of the transistor 111 and the transistor 112 is turned on. Thus, the light emitting device 114 can start to emit light at an arbitrary timing after the addition of the weight (W) and the data (D).

[0175] Figure 7D is a structure in which the transistor 112 is added to the structure of Figure 7AThe structure of the additional transistor 115 is described. One of the source and drain of transistor 115 is electrically connected to one of the source and drain of transistor 111. The other of the source and drain of transistor 115 is electrically connected to wiring 131. The gate of transistor 115 is electrically connected to wiring 132. Wiring 132 may function as a signal line to control the conduction of transistor 115.

[0176] Wiring 131 can be electrically connected to a supply source with a specific potential, such as a reference potential. By supplying a specific potential to one of the source and drain terminals of transistor 111 from wiring 131, the writing of image data can be stabilized. Additionally, the emission timing of the light-emitting device 114 can also be controlled.

[0177] Furthermore, wiring 131 can be connected to circuit 120 and can function as a monitoring line. Circuit 120 can have one or more functions, such as serving as a power source for the specific potential, acquiring the electrical characteristics of transistor 111, and generating correction data.

[0178] Figures 8A-8D This is an example of a structure that can be used in circuit block 110 and as a display device including a liquid crystal device.

[0179] Figure 8A The structure shown includes a capacitor 116 and a liquid crystal device 117. One electrode of the liquid crystal device 117 is electrically connected to one electrode of the capacitor 116. One electrode of the capacitor 116 is electrically connected to the node NP.

[0180] The other electrode of capacitor 116 is electrically connected to wiring 133. The other electrode of liquid crystal device 117 is electrically connected to wiring 134. Wiring 133 and 134 have the function of supplying power. For example, wiring 133 and 134 can supply reference potentials such as GND and 0V or any potential.

[0181] Alternatively, it can be like Figure 8B As shown, capacitor 116 is omitted. As described above, an OS transistor can be used as the transistor connected to node NP. Since the leakage current of the OS transistor is extremely small, the display can be maintained for a long time even without omitting capacitor 116, which is used as a holding capacitor. Furthermore, not limited to the transistor structure, omitting capacitor 116 is also effective when shortening the display period using high-speed operation such as field-sequence drive. Omitting capacitor 116 can increase the aperture ratio. In addition, the pixel transmittance can be increased.

[0182] exist Figure 8A and Figure 8BIn the structure shown, the operation of the liquid crystal device 117 is started when the potential of the node NP is set to be higher than the operation threshold value of the liquid crystal device 117. Thus, display operation is sometimes started when the weight is written to the node NP, resulting in a limitation in the use of the structure. However, in a transmissive liquid crystal display device, for example, by also turning off the back light until the addition operation of the weight (W) and the data (D) is completed, even if unnecessary display operation is performed, the unnecessary display can be suppressed from being seen.

[0183] Figure 8C is a structure in which the transistor 118 is added to the structure of Figure 8A . One of the source and drain of the transistor 118 is electrically connected to one of the electrodes of the capacitor 116. The other of the source and drain of the transistor 118 is electrically connected to the node NP. The gate of the transistor 118 is electrically connected to the wiring 136. The wiring 136 can have a function of a signal line for controlling the conduction of the transistor 118.

[0184] In this structure, the liquid crystal device 117 is applied with the potential of the node NP while the transistor 118 is in conduction. Thus, the operation of the liquid crystal device can be started at an arbitrary timing after the addition operation of the weight (W) and the data (D).

[0185] In addition, since the potentials supplied to the capacitor 116 and the liquid crystal device 117 continue to be held in a state where the transistor 118 is not in conduction, it is preferable to reset the potentials supplied to the capacitor 116 and the liquid crystal device 117 before rewriting the image data. In this reset, for example, a reset potential is supplied to the wiring 125, and at the same time, the transistor 104 and the transistor 118 are made to be in conduction.

[0186] Figure 8D is a structure in which the transistor 119 is added to the structure of Figure 8C . One of the source and drain of the transistor 119 is electrically connected to one of the electrodes of the liquid crystal device 117. The other of the source and drain of the transistor 119 is electrically connected to the wiring 131. The gate of the transistor 119 is electrically connected to the wiring 135. The wiring 135 can have a function of a signal line for controlling the conduction of the transistor 119.

[0187] The circuit 120 electrically connected to the wiring 131 can have the same function as that of the circuit 120 described in Figure 7D , and can also have a function of resetting the potentials supplied to the capacitor 116 and the liquid crystal device 117.

[0188] Figures 9A-9C shows a specific example of the wiring for supplying "V ref " in the pixel 10 shown in Figure 2 . As shown in Figure 9A , when a light emitting device is used as a display device, the wiring 128 can be used as a wiring for supplying "Vref The wiring of “V”. Because “V” ref "Preferred voltages are 0V, GND, or low voltage, so wiring 128 also has the function of supplying at least one of these voltages. Additionally, 'V' can be supplied to wiring 128 when data is written to node NP." ref ", and supplies a high-potential power supply to wiring 128 when the light-emitting device 114 emits light. Additionally, such as Figure 9B As shown, the wiring 129 supplying low potential can be used as a supply for "V". ref The wiring.

[0189] like Figure 9C As shown, when a liquid crystal device is used as a display device, wiring 133 can be used to supply "V" ref Alternatively, wiring 134 can also be used. Note that the supply of "V" can be set regardless of the type of display device. ref "Dedicated public cabling".

[0190] Furthermore, in one aspect of the invention, such as Figure 10 As shown, transistors can also be configured with a back gate. Figure 10 The diagram shows a structure where the back gate and front gate are electrically connected, which improves the on-state current. Additionally, Figure 10 The diagram illustrates a structure where the back gate is electrically connected to wiring capable of supplying a constant potential, which can control the threshold voltage of the transistor. Furthermore, the transistors included in circuit block 110 may also be provided with a back gate.

[0191] Next, we will explain the simulation results regarding the operation of pixels. Figure 11 The structure of the pixel (PIX) and circuit 11 used for simulation is shown. It is assumed that the number of pixels is 4, used as circuit block 110. Figure 8A The structure shown (liquid crystal device and capacitor) is illustrated. The voltage changes of node NP of each pixel are simulated in operation with the input voltage set to about three times (hereinafter referred to as operation 1) and operation with the input voltage increased to about four times (hereinafter referred to as operation 2).

[0192] The parameters used for the simulation of Operation 1 are as follows: transistor dimensions are L / W = 3μm / 100μm (transistors Tr1, Tr2, Tr3) and L / W = 3μm / 50μm (transistors Tr4, Tr5, Tr6); capacitor C1 has a capacitance of 500pF; capacitor C2 has a capacitance of 5pF; capacitor Cs has a capacitance of 500fF; and liquid crystal device Clc has a capacitance of 500fF. Furthermore, as the voltage applied to the transistor gates, "H" is set to +15V and "L" is set to -15V.

[0193] The parameters for the simulation of Operation 2 are as follows: transistor size L / W = 1 μm / 50 μm (transistors Trl, Tr2, Tr3), L / W = 3 μm / 100 μm (transistors Tr4, Tr5, Tr6); capacitance value of capacitor Cl, 100 pF; capacitance value of capacitor C2, 10 pF; capacitance value of capacitor Cs, 50 fF; capacitance value of liquid crystal device Clc, 50 fF. Further, as the voltage applied to the gate of the transistor, "H" is set to +15 V and "L" is set to -20 V.

[0194] Note that, in order to obtain more accurate simulation results, it is preferable that the resistor Rl equivalent to the parasitic resistance and the capacitor C3 equivalent to the parasitic capacitance are mounted in the same number as the pixels to the wiring PL connecting the circuit 11 and the pixel PIX. In this simulation, the parasitic capacitance (sum of C3) of the wiring PL is set to 0 F and the resistance (sum of Rl) of the wiring PL is set to 0 Ω, so as to verify the basic operation of the circuit 11 and the pixel PIX. Note that, as the circuit simulation software, SPICE is used.

[0195] Figure 12 is a timing chart for the simulation of Operation 1. Further, Figure 13 is a timing chart for the simulation of Operation 2. As to both Operation 1 and Operation 2, the following operation is verified: after writing data for positive polarity operation to the pixels PIX[1] to [4], writing operation of data for negative polarity operation. Here, as the parameters common to Operation 1 and Operation 2, the weight (+W) and the data (+D) are both +5 V and the weight (-W) and the data (-D) are both -5 V. In addition, V ref , VCOM, TCOM are all 0 V.

[0196] Figure 14 and Figure 15 are the simulation results of Operation 1 and Operation 2, respectively, the horizontal axis indicates time (sec) and the vertical axis indicates the voltage (V) of the node NP. Each figure shows the change in the voltage of the node NP at the time of the writing operation to the pixels PIX[1] to [4] with the time axis.

[0197] Although it can be considered to be affected by the charge distribution due to the feedthrough caused by the capacitance between the gate and the drain of the transistor and the capacitance of the series-connected capacitor, it can be confirmed that the input voltage can be boosted by about 2.5 times in the positive polarity operation of Operation 1 and by about 2.8 times in the negative polarity operation; the input voltage can be boosted by about 3.3 times in the positive polarity operation of Operation 2 and by about 3.4 times in the negative polarity operation. By improving the electrical characteristics of the transistor and reducing the parasitic capacitance, a higher voltage can be generated.

[0198] According to the simulation results above, the effect of one embodiment of the present application can be confirmed.

[0199] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes and the like.

[0200] (Embodiment 2)

[0201] This embodiment mode describes a structure example of a display device using a liquid crystal device and a structure example of a display device using a light emitting device. Note that description of the components, operation, and functions of the display device described in Embodiment 1 is omitted in this embodiment mode.

[0202] The adder circuit and the pixel described in Embodiment 1 can be used in the display device described in this embodiment mode. Note that the scan line driver circuit described below corresponds to a gate driver, and the signal line driver circuit corresponds to a source driver.

[0203] Figures 16A-16C A structure of a display device which can be manufactured using one embodiment of the present application is shown.

[0204] In Figure 16A the first substrate 4001, the display portion 215 is sealed with the sealant 4005 and the second substrate 4006.

[0205] In Figure 16A the scan line driver circuit 221a, the signal line driver circuit 231a, the signal line driver circuit 232a, and the common line driver circuit 241a each include a plurality of integrated circuits 4042 provided over the printed board 4041. The integrated circuits 4042 are formed of single crystal semiconductor or polycrystal semiconductor. The common line driver circuit 241a has a function of supplying a predetermined potential to the wires 128, 129, 133, 134, and the like shown in Embodiment 1.

[0206] Various signals and potentials are supplied to the scan line driver circuit 221a, the common line driver circuit 241a, the signal line driver circuit 231a, and the signal line driver circuit 232a through an FPC 4018.

[0207] The integrated circuits 4042 included in the scan line driver circuit 221a and the common line driver circuit 241a have a function of supplying a selection signal to the display portion 215. The integrated circuits 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a have a function of supplying image data to the display portion 215. The integrated circuits 4042 are mounted in a region different from a region surrounded by the sealant 4005 on the first substrate 4001.

[0208] Note that there is no particular limitation on the connection method of the integrated circuit 4042, and a wire bonding method, a COG (Chip On Glass) method, a TCP (Tape Carrier Package) method, a COF (Chip On Film) method, or the like can be used.

[0209] Figure 16B An example in which the integrated circuits 4042 included in the signal line driver circuits 231a and 232a are mounted by the COG method is shown. In addition, by forming part or all of the driver circuits over a substrate over which the display portion 215 is formed, a system-on-panel can be obtained.

[0210] Figure 16B An example in which the scan line driver circuit 221a and the common line driver circuit 241a are formed over a substrate over which the display portion 215 is formed is shown. By simultaneously forming the driver circuits and the pixel circuits in the display portion 215, the number of components can be reduced. Thus, the productivity can be increased.

[0211] In addition, in Figure 16B , the sealing material 4005 is provided so as to surround the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a provided over the first substrate 4001. The second substrate 4006 is provided over the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a. Thus, the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a are sealed with the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0212] Although an example in which the signal line driver circuits 231a and 232a are separately formed and mounted to the first substrate 4001 is shown in Figure 16B , one embodiment of the present application is not limited to this structure. The scan line driver circuit can be separately formed and mounted, or part of the signal line driver circuit or part of the scan line driver circuit can be separately formed and mounted. In addition, as shown in Figure 16C , the signal line driver circuits 231a and 232a can be formed over a substrate over which the display portion 215 is formed.

[0213] Furthermore, a display device sometimes includes a panel in which a display element is in a sealed state and a module in which an IC or the like including a controller is mounted in the panel.

[0214] In addition, the display portion and the scan line driver circuit provided over the first substrate include a plurality of transistors. As the transistors, the transistors shown in the above embodiments can be used.

[0215] The structures of the transistors included in the peripheral drive circuit and the transistors included in the pixel circuit of the display portion can be the same or different. The transistors included in the peripheral drive circuit can all have the same structure or can be combined with two or more structures. Similarly, the transistors included in the pixel circuit can all have the same structure or can be combined with two or more structures.

[0216] In addition, an input device 4200 can be provided over the second substrate 4006. The structure of the display device illustrated in FIG. 4A is capable of functioning as a touch panel. Figures 16A-16C The structure of the display device illustrated in FIG. 4A is capable of functioning as a touch panel.

[0217] The sensing element (also referred to as a sensor element) included in the touch panel of one embodiment of the present application is not particularly limited. As the sensing element, various sensors capable of detecting the approach or contact of a detection object such as a finger or a stylus can be used.

[0218] As a mode of the sensor, for example, various modes such as an electrostatic capacity method, a resistance method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.

[0219] In this embodiment, a touch panel including a sensing element of the electrostatic capacity method is described as an example.

[0220] As the electrostatic capacity method, a surface type electrostatic capacity method, a projection type electrostatic capacity method, or the like is used. As the projection type electrostatic capacity method, a self-capacitance method, a mutual-capacitance method, or the like is used. The mutual-capacitance method is preferably used because multi-point sensing can be performed at the same time.

[0221] The touch panel of one embodiment of the present application can have various structures such as a structure in which a display device and a sensing element are attached to each other, a structure in which an electrode or the like included in a sensing element is provided in one or both of a substrate supporting a display element and a counter substrate.

[0222] Figure 17A and Figure 17B An example of a touch panel is described. Figure 17A is a perspective view of the touch panel 4210. Figure 17B is a perspective view of the input device 4200. Note that only typical components are illustrated for clarity.

[0223] The touch panel 4210 has a structure in which a display device and a sensing element are attached to each other.

[0224] The touch panel 4210 includes an input device 4200 and a display device which are provided to overlap with each other.

[0225] Input device 4200 includes substrate 4263, electrode 4227, electrode 4228, multiple wirings 4237, multiple wirings 4238, and multiple wirings 4239. For example, electrode 4227 may be electrically connected to wiring 4237 or wiring 4239. Additionally, electrode 4228 may be electrically connected to wiring 4238. FPC 4272b may be electrically connected to each of the multiple wirings 4237, 4238, and 4239. FPC 4272b may be equipped with IC 4273b.

[0226] Alternatively, a touch sensor may be disposed between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is disposed between the first substrate 4001 and the second substrate 4006, an optical touch sensor utilizing a photoelectric conversion element may be used in addition to an electrostatic capacitive touch sensor.

[0227] Figure 18A and Figure 18B yes Figure 16B The cross-sectional view of the portion shown by the dashed lines N1-N2. Figure 18A and Figure 18B The display device shown includes an electrode 4015, which is electrically connected to the terminals of the FPC 4018 via an anisotropic conductive layer 4019. Additionally, in Figure 18A and Figure 18B In this process, electrode 4015 is electrically connected to wiring 4014 in the openings formed in insulating layer 4112, insulating layer 4111 and insulating layer 4110.

[0228] Electrode 4015 and first electrode layer 4030 are formed using the same conductive layer, and wiring 4014 and source and drain electrodes of transistors 4010 and 4011 are formed using the same conductive layer.

[0229] Furthermore, the display section 215 and the scan line driving circuit 221a disposed on the first substrate 4001 include a plurality of transistors, in Figure 18A and Figure 18B The image shows transistor 4010 in display unit 215 and transistor 4011 in scan line drive circuit 221a. Although Figure 18A and Figure 18B The transistors 4010 and 4011 are shown as bottom-gate transistors, but top-gate transistors can also be used.

[0230] exist Figure 18A and Figure 18B In this configuration, an insulating layer 4112 is provided on transistors 4010 and 4011. Additionally, in... Figure 18B In the middle, a partition wall 4510 is formed on the insulating layer 4112.

[0231] Further, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. Further, the transistor 4010 and the transistor 4011 include an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can be used as a back gate electrode.

[0232] Further, Figure 18A and Figure 18B The display device illustrated in FIG. 4A includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same step as the gate electrode of the transistor 4010 and an electrode formed in the same step as the source and drain electrodes. These electrodes overlap with each other with the insulating layer 4103 interposed therebetween.

[0233] In general, the capacitance of a capacitor provided in a pixel portion is set so that the capacitor can hold a charge for a specified period, taking into account the leakage current of a transistor provided in the pixel portion, for example. The capacitance of the capacitor can be set taking into account the off-state current of a transistor electrically connected to the capacitor, for example.

[0234] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. Figure 18A This is an example of a liquid crystal display device in which a liquid crystal element is used as a display element. In Figure 18A In this embodiment, the liquid crystal element 4013 as a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 used as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 overlaps with the second electrode layer 4031 with the liquid crystal layer 4008 interposed therebetween.

[0235] As the liquid crystal device 4013, a liquid crystal device using various modes can be used. For example, a liquid crystal device using a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti-Ferroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS (Vertical Alignment In-Plane-Switching) mode, a guest-host mode, or the like can be used.

[0236] In addition, a normally black liquid crystal display device, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode, can be used for the liquid crystal display device of this embodiment. As the vertical alignment mode, a MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

[0237] A liquid crystal device is an element that controls transmission or non-transmission of light using an optical modulation effect of liquid crystal. The optical modulation effect of liquid crystal is controlled by an electric field (a horizontal electric field, a vertical electric field, or a tilted direction electric field) applied to the liquid crystal. As the liquid crystal used for the liquid crystal device, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a high-molecular dispersion type liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.

[0238] Although Figure 18AAn example of a liquid crystal display device with a vertical electric field is shown, but a liquid crystal display device with a horizontal electric field can also be used in one aspect of the present invention. In the case of a horizontal electric field, a liquid crystal exhibiting a blue phase can be used without an alignment film. The blue phase is a type of liquid crystal phase, referring to the phase that appears just before the cholesteric liquid crystal transitions to a homogeneous phase when the temperature is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition containing at least 5 wt% of a chiral reagent is used in the liquid crystal layer 4008 to broaden the temperature range. The liquid crystal composition containing the blue-phase liquid crystal and the chiral reagent has a fast response speed and is optically isotropic. Furthermore, the liquid crystal composition containing the blue-phase liquid crystal and the chiral reagent does not require alignment processing and has low viewing angle dependence. Additionally, since no alignment film is required and friction processing is unnecessary, electrostatic damage caused by friction processing can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced.

[0239] The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and it is provided to control the spacing (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers can also be used.

[0240] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a coloring layer (color filter), a polarizing component, a phase difference component, and an anti-reflection component can be appropriately provided as needed. For example, circular polarization utilizing a polarizing substrate and a phase difference substrate can also be used. Additionally, backlighting or sidelighting can be used as the light source. Micro-LEDs can also be used as the aforementioned backlighting or sidelighting.

[0241] exist Figure 18A In the display device shown, a light-shielding layer 4132, a coloring layer 4131 and an insulating layer 4133 are disposed between a substrate 4006 and a second electrode layer 4031.

[0242] Examples of materials suitable for use in the light-shielding layer include carbon black, titanium black, metals, metal oxides, or composite oxides comprising solid solutions of multiple metal oxides. The light-shielding layer can also be a film containing a resin material or a thin film of an inorganic material such as a metal. Alternatively, a laminated film containing a material for a coloring layer can be used for the light-shielding layer. For example, a laminated structure can be used consisting of a film containing a material for a coloring layer that allows light of a certain color to pass through and a film containing a material for a coloring layer that allows light of other colors to pass through. By using the same material for the coloring layer and the light-shielding layer, the process can be simplified, in addition to using the same equipment, which is therefore preferable.

[0243] As a material that can be used for the colored layer, a metal material, a resin material, a resin material containing a pigment or a dye, or the like can be given. The light-blocking layer and the colored layer can be formed in the same manner as the formation of the above-described layers. For example, an inkjet method or the like can be used.

[0244] In addition, Figure 18A and Figure 18B The display device illustrated in FIG. 41A includes an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer through which impurity elements are unlikely to penetrate is used. By sandwiching the semiconductor layer of the transistor with the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented.

[0245] Further, as a display element included in a display device, a light-emitting element can be used. As the light-emitting element, an EL element utilizing electroluminescence, for example, can be used. The EL element has a layer containing a light-emitting organic compound (also referred to as EL layer) between a pair of electrodes. When voltage is applied across the pair of electrodes, holes injected from the anode electrode and electrons injected from the cathode electrode are recombined, and thus the light-emitting substance contained in the EL layer emits light.

[0246] The EL element is classified into an organic EL element and an inorganic EL element depending on whether the light-emitting material is an organic compound or an inorganic compound.

[0247] In the organic EL element, by application of voltage, electrons are injected from one electrode into the EL layer, and holes are injected from the other electrode into the EL layer. By recombination of these carriers (electrons and holes), a light-emitting organic compound forms an excited state, and emits light when returning to a ground state from the excited state. Due to this mechanism, such a light-emitting element is called a current-excitation light-emitting element.

[0248] The EL layer can include, in addition to a light-emitting compound, a substance having a high hole- injecting property, a substance having a high hole-transport property, a hole-blocking material, a substance having a high electron-transport property, a substance having a high electron-injecting property, or a substance having a bipolar property (a substance having both a high hole-transport property and a high electron-transport property).

[0249] The EL layer can be formed by a method such as an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, or a coating method.

[0250] An inorganic EL element is classified into a dispersed inorganic EL element and a thin film inorganic EL element according to its element structure. The dispersed inorganic EL element includes a light emitting layer in which particles of a light emitting material are dispersed in a binder, and its light emitting mechanism is donor-acceptor recombination type light emission using a donor level and an acceptor level. The thin film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers, and the dielectric layers sandwiching the light emitting layer are sandwiched between electrodes, and its light emitting mechanism is localized light emission using an inner shell electron transition of a metal ion. Note that an organic EL element is described here as a light emitting device.

[0251] At least one of a pair of electrodes of the light emitting device can be transparent in order to extract light emission. A transistor and a light emitting device are formed over a substrate, and a top emission structure in which light emission is extracted from a surface on the opposite side of the substrate, a bottom emission structure in which light emission is extracted from a surface on the substrate side, and a dual emission structure in which light emission is extracted from both surfaces can be employed as the light emitting device.

[0252] Figure 19 This is an example of a light emitting display device (also referred to as an "EL display device") in which a light emitting device is used as a display device. The light emitting device 4513 used as a display device is electrically connected to the transistor 4010 provided in the display portion 215. Although the light emitting device 4513 has a stacked structure of a first electrode layer 4030, a light emitting layer 4511, and a second electrode layer 4031, the structure is not limited thereto. The structure of the light emitting device 4513 can be changed as appropriate depending on the direction in which light is extracted from the light emitting device 4513 or the like.

[0253] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material, form an opening portion in the first electrode layer 4030, and form the side surface of the opening portion into an inclined surface having a continuous curvature.

[0254] The light emitting layer 4511 can be formed using one layer or a stacked layer of a plurality of layers.

[0255] The light emitting color of the light emitting device 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like depending on a material included in the light emitting layer 4511.

[0256] As a method of realizing color display, there are a method of combining a light-emitting device 4513 whose emission color is white and a colored layer, and a method of providing a light-emitting device 4513 whose emission color is different for each pixel. The former method has higher productivity than the latter method. On the other hand, in the latter method, a light-emitting layer 4511 needs to be formed for each pixel, so it has lower productivity than the former method. However, in the latter method, a light-emitting color with higher color purity than the former method can be obtained. By providing the light-emitting device 4513 with a microcavity structure in the latter method, the color purity can be further improved.

[0257] The light-emitting layer 4511 can also contain an inorganic compound such as a quantum dot. For example, by using a quantum dot for the light-emitting layer, it can also be used as a light-emitting material.

[0258] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting device 4513, a protective layer can also be formed on the second electrode layer 4031 and the partition wall 4510. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (Diamond Like Carbon), or the like can be formed. Furthermore, a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealing agent 4005 and is sealed. In this way, in order not to be exposed to external gas, it is preferable to use a protective film (an adhesive film, an ultraviolet-cured resin film, or the like) with high airtightness and little outgassing, a cover material, or the like for packaging (encapsulation).

[0259] As the filler 4514, an ultraviolet-cured resin or a heat-cured resin such as PVC (polyvinyl chloride), an acrylic resin, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene-vinyl acetate) can be used in addition to an inert gas such as nitrogen or argon. The filler 4514 can also contain a desiccant.

[0260] As the sealing agent 4005, a glass material such as a glass powder or a resin material such as a curing resin that cures at room temperature, a photocuring resin, a heat-curing resin, or the like can be used. The sealing agent 4005 can also contain a desiccant.

[0261] In addition, as needed, an optical film such as a polarizing plate or a circularly polarizing plate (including an elliptically polarizing plate), a phase difference plate (λ / 4 plate, λ / 2 plate), a color filter, or the like can be appropriately provided on the light-emitting device light exit surface. Furthermore, an antireflection film can be provided on the polarizing plate or the circularly polarizing plate. For example, an anti-glare treatment, which is a treatment for reducing reflected glare by diffusing reflected light using the surface unevenness, can be performed.

[0262] By incorporating microcavity structures into light-emitting devices, it is possible to extract light with high color purity. Furthermore, by combining microcavity structures with color filters, reflected glare can be reduced, thereby improving image visibility.

[0263] Regarding the first electrode layer and the second electrode layer (also known as the pixel electrode layer, common electrode layer, counter electrode layer, etc.) that apply voltage to the display device, their light transmittance and reflectivity can be selected according to the direction of light extraction, the location of the electrode layer, and the pattern structure of the electrode layer.

[0264] As the first electrode layer 4030 and the second electrode layer 4031, transparent conductive materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0265] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 may be formed from one or more of the following metals, alloys, and nitrides: tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag).

[0266] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also known as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof composed of two or more of aniline, pyrrole, and thiophene.

[0267] Furthermore, since transistors are easily damaged by static electricity, etc., it is preferable to provide a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using non-linear components.

[0268] Note that, as Figure 19 As shown, a stacked structure with overlapping regions of transistors and capacitors in the height direction can also be used. For example, by arranging transistors 4011 and 4022, which form the driving circuit in an overlapping manner, a narrow bezel display device can be realized. Furthermore, by arranging transistors 4010, 4023, capacitors 4020, etc., that form the pixel circuit in a manner that partially includes the overlapping region, the aperture ratio and resolution can be improved. Furthermore, in Figure 18A The middle shows the Figure 18B The liquid crystal display device shown is an example of using a multilayer structure, but this structure can also be applied to... Figure 20A The EL display device shown.

[0269] Further, in the pixel circuit, a conductive film having high light transmittance to visible light is used as an electrode and a wiring, and thus light transmittance in the pixel can be increased, and thus the aperture ratio can be substantially increased. Further, since the semiconductor layer also has light transmittance when an OS transistor is used, the aperture ratio is further increased. This is also effective when a transistor or the like does not employ a stacked structure.

[0270] Further, a display device can be configured by combining a liquid crystal display device and a light emitting device.

[0271] The light emitting device is provided on the side opposite to the display surface or on the end portion of the display surface. The light emitting device has a function of supplying light to the display device. The light emitting device is called a backlight.

[0272] Here, the light emitting device can include a plate-shaped or film-shaped light guide portion (also referred to as a light guide plate), and a plurality of light emitting devices which emit light of different colors. By providing the light emitting devices near the side surface of the light guide portion, light can be emitted from the side surface of the light guide portion. The light guide portion includes a mechanism for changing the light path (also referred to as a light extraction mechanism), and thus the light emitting device can uniformly irradiate light to the pixel portion of the display panel. Alternatively, a structure in which the light emitting device is provided directly below the pixel without the light guide portion can be employed.

[0273] The light emitting device preferably includes light emitting devices of three colors of red (R), green (G), and blue (B). Further, a light emitting device of white (W) can be included. As the light emitting devices, light emitting diodes (LEDs) are preferably used.

[0274] Further, the light emitting device is preferably a light emitting device having extremely high color purity in which the full width at half maximum (FWHM) of an emission spectrum is 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and still more preferably 20 nm or less. Note that the smaller the full width at half maximum of the emission spectrum, the better, and for example, can be 1 nm or more. Thus, when color display is performed, display with high color reproducibility can be performed.

[0275] Further, the light emitting device of red is preferably an element in which the peak wavelength of an emission spectrum is in a range of 625 nm or more and 650 nm or less. Further, the light emitting device of green is preferably an element in which the peak wavelength of an emission spectrum is in a range of 515 nm or more and 540 nm or less. The light emitting device of blue is preferably an element in which the peak wavelength of an emission spectrum is in a range of 445 nm or more and 470 nm or less.

[0276] The display device drives the pixels in synchronization with the time when the light emitting devices of the three colors are made to emit light in sequence, and color display is performed by the successive-adding color mixing method. This driving method can also be referred to as a field sequential driving method.

[0277] The field sequential driving method can display a bright color image. In addition, a smooth moving image can be displayed. Furthermore, by using the above-described driving method, since it is not necessary to constitute one pixel by a plurality of sub-pixels of different colors, the effective reflection area (also referred to as effective display area or aperture ratio) of one pixel can be enlarged, and bright display can be performed. Moreover, since it is not necessary to provide a color filter in the pixel, the transmittance of the pixel can be improved, and brighter display can be performed. In addition, the manufacturing process can be simplified, and thus the manufacturing cost can be reduced.

[0278] Figure 20B 、 Figure 20A is an example of a cross-sectional view of a display device capable of field sequential driving. A backlight unit capable of emitting light of RGB colors is provided on the substrate 4001 side of the display device. Note that in the field sequential driving method, since the color is displayed by time division of light emission of RGB colors, a color filter is not necessary.

[0279] Figure 20B The backlight unit 4340a shown has a structure in which a plurality of light emitting devices 4342 are provided under the pixel with a diffusion plate 4352 interposed therebetween. The diffusion plate 4352 has a function of diffusing light emitted from the light emitting devices 4342 to the substrate 4001 side to make the luminance uniform in the display portion plane. A polarizing plate can also be provided as necessary between the light emitting devices 4342 and the diffusion plate 4352. In addition, the diffusion plate 4352 can not be provided if not necessary. Further, the light shielding layer 4132 can also be omitted.

[0280] The backlight unit 4340a can realize bright display since a larger number of light emitting devices 4342 can be mounted. In addition, a light guide plate is not necessary, and there is an advantage that the light from the light emitting devices 4342 is less likely to be lost in efficiency. Note that a lens 4344 for light diffusion can also be provided in the light emitting devices 4342 as necessary.

[0281] Figure 20B The backlight unit 4340b shown has a structure in which a light guide plate 4341 is provided under the pixel with a diffusion plate 4352 interposed therebetween. A plurality of light emitting devices 4342 are provided at the end portion of the light guide plate 4341. The light guide plate 4341 has a concave-convex shape on the side opposite to the diffusion plate 4352, and can scatter the guided light with the concave-convex shape to emit the light in the direction of the diffusion plate 4352.

[0282] The light emitting devices 4342 can be fixed to a printed circuit board 4347. Note that in the case of the backlight unit 4340b, the light emitting devices 4342 can be fixed to the light guide plate 4341. Figure 21AThe light emitting devices 4342 of each color of RGB are arranged in the depth direction as illustrated in FIG. 34B. Alternatively, the light emitting devices 4342 of each color of RGB can be arranged in the depth direction as illustrated in FIG. 34C. Further, a reflective layer 4348 which reflects visible light can be provided on the side of the light guide plate 4341 opposite the light emitting devices 4342.

[0283] The backlight unit 4340b can be low cost and thin because the number of light emitting devices 4342 can be reduced.

[0284] As the liquid crystal device, a light scattering type liquid crystal device can be used. As the light scattering type liquid crystal device, an element including a composite of a liquid crystal and a polymer is preferably used. For example, a polymer dispersed type liquid crystal device can be used. Alternatively, a polymer network type liquid crystal (PNLC) element can be used.

[0285] The light scattering type liquid crystal device has a structure in which a liquid crystal portion is provided in a three-dimensional network structure of a resin portion sandwiched between a pair of electrodes. As a material for the liquid crystal portion, for example, a nematic liquid crystal can be used. Further, a photocurable resin can be used as the resin portion. The photocurable resin can use, for example, a monofunctional monomer such as an acrylate or a methacrylate; a multifunctional monomer such as a diacrylate, a triacrylate, a dimethacrylate, or a trimethacrylate; or a polymerizable compound in which the above substances are mixed.

[0286] The light scattering type liquid crystal device performs display by transmitting or scattering light using anisotropy of the refractive index of the liquid crystal material. Further, the resin portion can also have anisotropy of the refractive index. When the liquid crystal molecules are aligned in a certain direction according to a voltage applied to the light scattering type liquid crystal device, a direction in which a difference in the refractive index between the liquid crystal portion and the resin portion becomes small is generated, and light incident along the direction is transmitted without being scattered in the liquid crystal portion. Thus, the light scattering type liquid crystal device appears to be in a transparent state from the direction. On the other hand, when the liquid crystal molecules are randomly aligned according to the voltage applied, the difference in the refractive index between the liquid crystal portion and the resin portion does not change greatly, and thus incident light is scattered in the liquid crystal portion. Thus, the light scattering type liquid crystal device becomes an opaque state regardless of the viewing direction.

[0287] Figure 20A is a structure in which the liquid crystal device 4013 of the display device of Figure 20A is replaced with a light scattering type liquid crystal device 4016. The light scattering type liquid crystal device 4016 includes a composite layer 4009 having a liquid crystal portion and a resin portion, an electrode layer 4030, and an electrode layer 4031. The constituent elements of the field sequential driving are the same as those of Figure 21B , and when the light scattering type liquid crystal device 4016 is used, an alignment film and a polarizing plate are not needed. Note that the shape of the spacer 4035 in the drawing is spherical, but can be columnar.

[0288] Figure 20B Showing will Figure 20B The liquid crystal device 4013 of the display device is replaced with a light-scattering type liquid crystal device 4016. Figures 22A-22E The structure shown is preferably designed to operate in a mode where light is transmitted when no voltage is applied to the light-scattering liquid crystal device 4016, but is scattered when a voltage is applied. By employing this structure, it can become a transparent display device in its normal state (non-display state). In this case, color display can be performed when the scattered light is applied.

[0289] Figure 21B Show Figures 22A-22E The illustration shows a modified example of the display device. Note that in... Figure 21B In order to make it easier to understand, the Chinese text uses... Figure 22A The diagram shows only a portion of the constituent elements, omitting other constituent elements.

[0290] Figure 22B The structure shows a substrate 4001 used as a light guide plate. An uneven shape can also be provided on the outer surface of the substrate 4001. This structure eliminates the need for a separate light guide plate, thus reducing manufacturing costs. Furthermore, since there is no light attenuation due to the light guide plate, the light emitted by the light-emitting device 4342 can be utilized efficiently.

[0291] Figure 22C The structure of incident light near the end of composite layer 4009 is shown. By utilizing total internal reflection at the interfaces between composite layer 4009 and substrate 4006 and between composite layer 4009 and substrate 4001, light can be emitted from the light-scattering liquid crystal device to the outside. The resin portion of composite layer 4009 uses a material with a refractive index greater than that of substrates 4001 and 4006.

[0292] Note that the light-emitting device 4342 is not only located on one side of the display device, but also, as... Figure 22D The light-emitting device 4342 can also be positioned on two opposite sides. Furthermore, it can be positioned on three or four sides. By placing the light-emitting device 4342 on multiple sides, light attenuation can be compensated for, and it can also be used for large-area display devices.

[0293] Figure 22E The diagram illustrates a structure in which light emitted from the light-emitting device 4342 is guided to the display device via a mirror 4345. This structure allows for efficient total internal reflection of light because light can be easily guided to the display device at a specific angle.

[0294] Figure 21BThe structure of the composite layer 4009, including layers 4003 and 4004, is shown. One of layers 4003 and 4004 is a support such as a glass substrate, while the other can be formed from an inorganic film, an organic resin coating film, or a thin film. The resin portion of the composite layer 4009 uses a material with a higher refractive index than layer 4004. Similarly, layer 4004 uses a material with a higher refractive index than layer 4003.

[0295] A first interface is formed between composite layer 4009 and layer 4004, and a second interface is formed between layer 4004 and layer 4003. Through this structure, light that does not undergo total internal reflection at the first interface undergoes total internal reflection at the second interface and can return to composite layer 4009. Therefore, the light emitted by light-emitting device 4342 can be utilized efficiently.

[0296] Notice, Figures 22A-22E and Figure 23A1 The structures can be combined with each other.

[0297] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0298] (Implementation Method 3)

[0299] In this embodiment, an example of a transistor that can be used instead of the transistors shown in the above embodiments will be described with reference to the accompanying drawings.

[0300] One embodiment of the display device of the present invention can be manufactured using transistors of various forms, such as bottom-gate transistors or top-gate transistors. Therefore, the semiconductor layer material or transistor structure used can be easily replaced to accommodate existing production lines.

[0301] Bottom-gate transistor

[0302] Figure 23A1 A cross-sectional view along the channel length of a channel-protected transistor 810, one of the bottom-gate transistors, is shown. Figure 23A2 In this embodiment, transistor 810 is formed on substrate 771. Furthermore, transistor 810 includes an electrode 746 on substrate 771, separated by an insulating layer 772. Additionally, a semiconductor layer 742 is included on electrode 746, separated by an insulating layer 726. Electrode 746 can be used as a gate electrode. Insulating layer 726 can be used as a gate insulating layer.

[0303] Additionally, an insulating layer 741 is included in the channel formation region of the semiconductor layer 742. Furthermore, electrodes 744a and 744b are included on the insulating layer 726 in contact with a portion of the semiconductor layer 742. Electrode 744a can be used as one of the source electrode and the drain electrode. Electrode 744b can be used as the other of the source electrode and the drain electrode. A portion of electrode 744a and a portion of electrode 744b are formed on the insulating layer 741.

[0304] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 on the channel formation region, the semiconductor layer 742 can be prevented from being exposed during the formation of electrodes 744a and 744b. This prevents the channel formation region of the semiconductor layer 742 from being etched during the formation of electrodes 744a and 744b. According to one aspect of the present invention, a transistor with excellent electrical characteristics can be realized.

[0305] Additionally, transistor 810 includes an insulating layer 728 on electrodes 744a, 744b and insulating layer 741, and an insulating layer 729 on insulating layer 728.

[0306] When an oxide semiconductor is used in semiconductor layer 742, it is preferable to use a material capable of abstracting oxygen from a portion of semiconductor layer 742 to generate oxygen vacancies in at least the portions of electrodes 744a and 744b that are in contact with semiconductor layer 742. The carrier concentration in the region of semiconductor layer 742 where oxygen vacancies are generated increases, and this region becomes n-type, forming an n-type region (n... + (Layer). Therefore, this region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, tungsten, titanium, etc. can be cited as examples of materials that can abstract oxygen from the semiconductor layer 742 to generate oxygen vacancies.

[0307] By forming source and drain regions in semiconductor layer 742, the contact resistance between electrodes 744a and 744b and semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor, such as field-effect mobility and threshold voltage, can be optimized.

[0308] When a semiconductor such as silicon is used for semiconductor layer 742, it is preferable to provide layers that are used as n-type or p-type semiconductors between semiconductor layer 742 and electrode 744a and between semiconductor layer 742 and electrode 744b. The layers used as n-type or p-type semiconductors can be used as the source region or drain region of a transistor.

[0309] The insulating layer 729 is preferably formed of a material that prevents impurities from diffusing into the transistor from the outside or reduces the diffusion of impurities. Alternatively, the insulating layer 729 may be omitted if necessary.

[0310] Figure 23B1The transistor 811 is different from the transistor 810 in that the electrode 723 serving as a back gate electrode is included over the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746.

[0311] In general, a back gate electrode is formed using a conductive layer and is provided so that a channel formation region of a semiconductor layer is interposed between the gate electrode and the back gate electrode. Thus, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be the same as that of the gate electrode, or can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0312] Either the electrode 746 or the electrode 723 can be used as a gate electrode. Thus, either the insulating layer 726, the insulating layer 728, or the insulating layer 729 can be used as a gate insulating layer. In addition, the electrode 723 can be provided between the insulating layer 728 and the insulating layer 729.

[0313] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as a "gate electrode", the electrode 746 is referred to as a "back gate electrode". In addition, when the electrode 723 is used as a "gate electrode", the transistor 811 can be regarded as one of top-gate transistors. Furthermore, one of the electrode 746 and the electrode 723 is sometimes referred to as a "first gate electrode", and the other is sometimes referred to as a "second gate electrode".

[0314] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween and setting the potentials of the electrode 746 and the electrode 723 to be the same, a region through which a carrier in the semiconductor layer 742 flows is more expanded in a film thickness direction, so that the amount of movement of the carrier increases. As a result, the on-state current of the transistor 811 increases, and the field-effect mobility is also increased.

[0315] Thus, the transistor 811 is a transistor with a large on-state current relative to the size. That is, the size of the transistor 811 can be reduced relative to the on-state current required. According to one embodiment of the present application, the size of a transistor can be reduced. Thus, according to one embodiment of the present application, a semiconductor device with high integration can be achieved.

[0316] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, the gate electrode and the back gate electrode have a function of preventing an electric field generated outside the transistor from affecting the semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity or the like). In addition, when the back gate electrode is formed to be larger than the semiconductor layer so that the semiconductor layer is covered with the back gate electrode, the electric field shielding function can be improved.

[0317] Furthermore, by using a conductive film with light-shielding properties to form the back gate electrode, light can be prevented from entering the semiconductor layer from the back gate electrode side. This prevents light degradation of the semiconductor layer and degradation of electrical characteristics such as threshold voltage drift in the transistor.

[0318] According to one aspect of the present invention, a transistor with high reliability can be realized. Furthermore, a semiconductor device with high reliability can be realized.

[0319] Figure 23A1 Is with Figure 23B2 A cross-sectional view along the channel length of a channel-protected transistor 820 with a different structure. Transistor 820 has a structure substantially the same as transistor 810, except that insulating layer 741 covers the end of semiconductor layer 742. In an opening formed by selectively removing a portion of insulating layer 741 overlapping semiconductor layer 742, semiconductor layer 742 is electrically connected to electrode 744a. Additionally, in other openings formed by selectively removing a portion of insulating layer 741 overlapping semiconductor layer 742, semiconductor layer 742 is electrically connected to electrode 744b. The region of insulating layer 741 overlapping the channel formation region can be used as a channel protection layer.

[0320] Figure 23C1 The transistor 821 shown differs from the transistor 820 in that it includes an electrode 723 on the insulating layer 729, which can be used as a back gate electrode.

[0321] By providing the insulating layer 741, the exposure of the semiconductor layer 742 generated during the formation of electrodes 744a and 744b can be prevented. Therefore, the thinning of the semiconductor layer 742 during the formation of electrodes 744a and 744b can be prevented.

[0322] Furthermore, compared to transistors 810 and 811, the distances between electrodes 744a and 746, and between electrodes 744b and 746, are longer in transistors 820 and 821. Therefore, the parasitic capacitance generated between electrodes 744a and 746 can be reduced. Additionally, the parasitic capacitance generated between electrodes 744b and 746 can also be reduced. According to one aspect of the present invention, a transistor with excellent electrical characteristics can be provided.

[0323] Figure 23C2 This is a cross-sectional view along the channel length of a channel-etched transistor 825, which is a bottom-gate transistor. In transistor 825, the insulating layer 729 is not used to form electrodes 744a and 744b. Therefore, a portion of the semiconductor layer 742 exposed during the formation of electrodes 744a and 744b is sometimes etched. On the other hand, since the insulating layer 729 is not provided, the transistor's productivity can be improved.

[0324] Figures 24A1-24C2 The transistor 826 shown is different from the transistor 820 in that the electrode 723 serving as a back gate electrode is provided over the insulating layer 729.

[0325] Figure 24B2 Cross-sectional views taken along channel width directions of the transistors 810, 811, 820, 821, 825, and 826, respectively.

[0326] In the structure shown in FIG. 8B, the gate electrode and the back gate electrode are connected to each other, whereby the potentials of the gate electrode and the back gate electrode are the same. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode. Figure 24C2 Figure 25A1 In the structure shown in FIG. 8B, the gate electrode and the back gate electrode are connected to each other, whereby the potentials of the gate electrode and the back gate electrode are the same. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0327] In the channel width direction, the lengths of the gate electrode and the back gate electrode are larger than that of the semiconductor layer 742, and the semiconductor layer 742 is entirely sandwiched between the insulating layers 726, 741, 728, and 729 and covered with the gate electrode and the back gate electrode.

[0328] With this structure, the semiconductor layer 742 included in the transistor can be surrounded by the electric field of the gate electrode and the back gate electrode.

[0329] A device structure of a transistor in which the semiconductor layer 742 forming a channel formation region is surrounded by the electric field of the gate electrode and the back gate electrode, like the transistor 821 and the transistor 826, can be referred to as a Surrounded channel (S-channel) structure.

[0330] With the S-channel structure, the semiconductor layer 742 can be effectively subjected to the electric field for inducing a channel formation by one or both of the gate electrode and the back gate electrode, whereby the current drivability of the transistor is improved, and thus a higher on-state current characteristic can be obtained. Further, since the on-state current can be increased, the transistor can be miniaturized. Further, with the S-channel structure, the mechanical strength of the transistor can be improved.

[0331] [Top-gate transistor]

[0332] Figure 25A2 The transistor 842 shown is one of top-gate transistors. The electrode 744a and the electrode 744b are electrically connected to the semiconductor layer 742 in openings formed in the insulating layer 728 and the insulating layer 729.

[0333] ​In addition, a portion of the insulating layer 726 which does not overlap with the electrode 746 is removed, and impurities are introduced into the semiconductor layer 742 with the electrode 746 and the remaining insulating layer 726 as masks, whereby an impurity region can be formed in the semiconductor layer 742 in a self-alignment manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end portion of the electrode 746. The impurity concentration of the region of the semiconductor layer 742 into which impurities are introduced through the insulating layer 726 is lower than that of the region of the semiconductor layer 742 into which impurities are not introduced through the insulating layer 726. Thus, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 which does not overlap with the electrode 746.

[0334] Figure 25B1 The transistor 843 illustrated in FIG. 8A is different from the transistor 842 in that it includes the electrode 723. The transistor 843 includes the electrode 723 formed over the substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. The electrode 723 can be used as a back gate electrode.

[0335] In addition, as in the transistors 844 and 845 illustrated in FIGS. 8B and 8C, the insulating layer 726 can be removed from the region which does not overlap with the electrode 746. Figure 25B2 Figure 25C1 In addition, as in the transistors 846 and 847 illustrated in FIGS. 8D and 8E, the insulating layer 726 can not be removed. Figure 25C2 Figures 26A1-26C2

[0336] In the transistors 842 to 847, impurities can be introduced into the semiconductor layer 742 with the electrode 746 as a mask after the formation of the electrode 746, whereby an impurity region can be formed in the semiconductor layer 742 in a self-alignment manner. According to one embodiment of the present application, a transistor with excellent electric characteristics can be implemented. In addition, according to one embodiment of the present application, a semiconductor device with high integration can be implemented.

[0337] Figure 27A FIG. 9A is a cross-sectional view of the channel width direction of the transistors 842, 843, 844, 845, 846, and 847.

[0338] The transistors 843, 845, and 847 have the S-channel structure described above. However, the transistors 843, 845, and 847 are not necessarily provided with the S-channel structure.

[0339] The present embodiment can be implemented in combination with the structures described in other embodiments and the like as appropriate.

[0340] (Embodiment 4) ​​​

[0341] As electronic devices to which one embodiment of the present application can be applied, a display device, a personal computer, an image storage device and an image reproduction device provided with a recording medium, a mobile phone, a game machine including a portable game machine, a portable data terminal, an electronic book reader, a camera such as a video camera or a digital camera, a goggle-type display (head-mounted display), a navigation system, an audio reproduction device (a car audio system, a digital audio player, or the like), a copier, a facsimile machine, a printer, a multifunction printer, an automatic teller machine (ATM), and a vending machine can be given. FIG. 27 illustrates specific examples of these electronic devices.

[0342] Figure 27B is a digital camera including a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display portion 965, an operation key 966, a zoom button 968, a lens 969, and the like. With the use of the display device of one embodiment of the present application for the display portion 965, display of various images can be performed.

[0343] Figure 27C is a digital sign including a large display portion 922. For example, the digital sign is provided with the large display portion 922 on a side surface of a column 921. With the use of the display device of one embodiment of the present application for the display portion 922, display with high display quality can be performed.

[0344] Figure 27D is a mobile phone including a housing 951, a display portion 952, an operation button 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, and the like. The mobile phone includes a touch sensor in the display portion 952. All operations such as making a call or inputting text can be performed by touching the display portion 952 with a finger or a stylus. In addition, the housing 951 and the display portion 952 have flexibility and can be used with being bent as illustrated. With the use of the display device of one embodiment of the present application for the display portion 952, display of various images can be performed.

[0345] Figure 27E is a video camera including a first housing 901, a second housing 902, a display portion 903, an operation key 904, a lens 905, a connection portion 906, a speaker 907, and the like. The operation key 904 and the lens 905 are provided in the first housing 901, and the display portion 903 is provided in the second housing 902. With the use of the display device of one embodiment of the present application for the display portion 903, display of various images can be performed.

[0346] Figure 27Fis a television set including a housing 971, a display portion 973, an operation key 974, a speaker 975, a communication terminal 976, and a photosensor 977. The display portion 973 is provided with a touch sensor, and input operation can be performed. By using the display device of one embodiment of the present application for the display portion 973, display of various images can be performed.

[0347] ​ is a portable data terminal including a housing 911, a display portion 912, a speaker 913, and a camera 919. Data can be inputted or outputted by the touch panel function of the display portion 912. By using the display device of one embodiment of the present application for the display portion 912, display of various images can be performed.

[0348] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes and the like.

[0349] [Explanation of Symbols]

[0350] 10: pixel, 11: circuit, 11a: circuit, 11b: circuit, 12: source driver, 12a: source driver, 12b: source driver, 13: gate driver, 15: display region, 16: selection circuit, 20: circuit, 101: transistor, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 107: capacitor, 108: capacitor, 109: capacitor, 110: circuit block, 111: transistor, 112: transistor, 113: capacitor, 114: light emitting device, 115: transistor, 116: capacitor, 117: liquid crystal device, 118: transistor, 119: transistor, 120: circuit, 121: wiring, 121a: wiring, 121b: wiring, 122: wiring, 122a: wiring, 122b: wiring, 123: wiring, 124: wiring, 125: wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 130: wiring, 131: wiring, 132: wiring, 133: wiring, 134: wiring, 135: wiring, 136: wiring, 215: display portion, 221a: scan line driver circuit, 231a: signal line driver circuit, 232a: signal line driver circuit, 241a: common line driver circuit, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 771: substrate, 772: insulating layer, 810: transistor, 811: transistor, 820: transistor, 821: transistor, 825: transistor, 826: transistor, 842: transistor, 843: transistor, 844: transistor, 845: transistor, 846: transistor, 847: transistor, 901: housing, 902: housing, 903: display portion, 904: operation key, 905: lens, 906: connection portion, 907: speaker, 911: housing, 912: display portion, 913: speaker, 919: camera, 921: column, 922: display portion, 951: housing, 952: display portion, 953: operation button, 954: external connection terminal, 955: speaker, 956: microphone, 957: camera, 961: housing, 962: shutter button, 963: microphone, 965: display portion, 966: operation key, 967: speaker, 968: zoom knob, 969: lens, 971: housing, 973: display portion, 974: operation key, 975: speaker, 976: communication connection terminal, 977: photosensor, 4001: substrate, 4003: layer, 4004: layer, 4005: sealing agent, 4006: substrate, 4008: liquid crystal layer, 4009: composite layer, 4010: transistor, 4011: transistor, 4013: liquid crystal device, 4014: wiring4015: electrode, 4016: light-scattering liquid crystal device, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020: capacitor, 4021: electrode, 4022: transistor, 4023: transistor, 4030: electrode layer, 4031: electrode layer, 4032: insulating layer, 4033: insulating layer, 4035: spacer, 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: insulating layer, 4104: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: colored layer, 4132: light-blocking layer, 4133: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode, 4228: electrode, 4237: wiring, 4238: wiring, 4239: wiring, 4263: substrate, 4272b: FPC, 4273b: IC, 4340a: back light unit, 4340b: back light unit, 4341: light guide plate, 4342: light-emitting device, 4344: lens, 4345: mirror, 4347: printed circuit board, 4348: reflective layer, 4352: diffusion plate, 4510: partition wall, 4511: light-emitting layer, 4513: light-emitting device, 4514: filler

Claims

1. A display device, comprising: First circuit; as well as The pixel is electrically connected to the first circuit. The pixel includes a second circuit and a display device. The first circuit is configured to add the first data and the second data, each supplied from the source driver, to generate the third data. The second circuit is configured to add the first data and the third data to generate fourth data and is configured to display an image based on the fourth data. The first circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor. One of the source and drain terminals of the first transistor is electrically connected to the pixel. One of the source and drain terminals of the first transistor is electrically connected to one electrode of the first capacitor. The other electrode of the first capacitor is electrically connected to one of the source and drain electrodes of the second transistor. One of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor. The other of the source and drain of the first transistor is electrically connected to the other of the source and drain of the second transistor. The other of the source and drain terminals of the first transistor is electrically connected to the output wiring from the source driver. The gate of the first transistor is electrically connected to the gate of the third transistor. The pixel includes the first capacitor in the area overlapping with the first circuit. The second circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor. One of the source and drain terminals of the fourth transistor is electrically connected to one electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to one of the source and drain electrodes of the fifth transistor. One of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor. The other of the source and drain of the fourth transistor is electrically connected to one electrode of the first capacitor. The other of the source and drain of the fifth transistor is electrically connected to one electrode of the first capacitor, and The gate of the fourth transistor is electrically connected to the gate of the sixth transistor.

2. The display device according to claim 1, The pixel includes a seventh transistor, a third capacitor, and a light-emitting device that serves as the display device. The gate of the seventh transistor is electrically connected to one of the source and drain of the fourth transistor. One of the source and drain of the seventh transistor is electrically connected to one electrode of the light-emitting device. One electrode of the light-emitting device is electrically connected to one electrode of the third capacitor. Furthermore, the other electrode of the third capacitor is electrically connected to the gate of the seventh transistor.

3. The display device according to claim 1, The pixel includes a third capacitor and a liquid crystal device, which serves as the display device. One electrode of the liquid crystal device is electrically connected to one of the source and drain electrodes of the fourth transistor. Furthermore, one electrode of the third capacitor is electrically connected to one electrode of the liquid crystal device.

4. The display device according to claim 1, Each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor contains a metal oxide in its channel formation region. The metal oxide contains In, Zn, and M. Furthermore, M is at least one of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

5. The display device according to claim 1, The channel widths of the first transistor, the second transistor, and the third transistor are each larger than the channel widths of the fourth transistor, the fifth transistor, and the sixth transistor.

6. An electronic device, comprising: The display device according to claim 1; as well as camera.

Images