Methods, devices, chips, and media for reading and writing data in FIFO memory

Abstract

This application discloses a method, apparatus, chip, and medium for reading and writing data in a FIFO memory, relating to the field of storage systems. The method includes interleaving data reading and writing from two single-port memories when no read / write conflict exists; and when a read / write conflict exists, a read-first approach is adopted, and then data is interleaved from the two single-port memories again in the next clock cycle, except that the written data is delayed by one clock cycle. Therefore, this method solves the problem of read / write conflict and realizes the function of FIFO data reading and writing; using two single-port memories enables simultaneous data reading and writing, thus realizing the function of simultaneous read / write of dual-port memories; and because the area of ​​single-port memories is small, chip area optimization can be achieved; furthermore, no clock multiplication is required, so the FIFO memory of this application can operate at higher frequencies.

Description

Technical Field

[0001] This application relates to the field of storage systems, and in particular to a method, apparatus, chip, and medium for reading and writing data in a FIFO memory. Background Technology

[0002] With the development of modern chip technology, chip integration density is increasing exponentially. For chip development, optimizing performance, power consumption, and area (PPA) is best achieved through careful design of the various basic unit libraries used in chip development. First-In-First-Out (FIFO) memory, as a fundamental unit in chip design, is used extensively. Therefore, optimizing FIFOs is significant for improving chip PPA. A FIFO is a system cache; the data stored first in the FIFO is the first to be read.

[0003] In previous technical solutions, FIFOs were designed based on two-port RAM (TPRAM). However, TPRAM occupies a relatively large area on the chip, leading to increased chip cost and manufacturing process complexity. Since single-port RAM (SPRAM) has a smaller area than TPRAM, SPRAM is often used in practical engineering to implement FIFO functionality. Currently, when using SPRAM to implement FIFO functionality, a small buffer FIFO is added before and after the SPRAM. This buffer uses the gap between the FIFO read enable / write enable signals to pre-write or read the necessary data, thus avoiding read / write conflicts. However, if the read / write enable signals remain continuous, read / write conflicts cannot be avoided, and the FIFO's data read / write functionality cannot be achieved.

[0004] Therefore, it is evident that how to implement FIFO data reading and writing functions based on SPRAM is a technical problem that urgently needs to be solved by those in the field. Summary of the Invention

[0005] The purpose of this application is to provide a method, apparatus, chip, and medium for reading and writing data in a FIFO memory, for implementing the function of reading and writing data in a FIFO based on SPRAM.

[0006] To address the aforementioned technical problems, this application provides a method for reading and writing data from a FIFO memory, applied to a chip containing two single-port memories, wherein the two single-port memories are derived from a dual-port memory; the method includes:

[0007] When performing read / write operations, determine whether data to be read or written is from the same single-port memory within the same clock cycle;

[0008] If not, data is read and written interleaved from the two single-port memories;

[0009] If so, a first target single-port memory is obtained from the two single-port memories, wherein the first target single-port memory is a single-port memory that is expected to read or write data in the same clock cycle; the first target single-port memory is controlled to read data in the current clock cycle; in the next clock cycle of the current clock cycle, data is interleaved from the two single-port memories to read and write data, wherein the data to be written is the data expected to be written in the current clock cycle.

[0010] Preferably, after interleaving read / write data from the two single-port memories in the next clock cycle of the current clock cycle, the method further includes:

[0011] Get the status of the read enable signal and the write enable signal;

[0012] Determine whether the read enable signal and the write enable signal are continuously valid;

[0013] If not, then stop interleaving read data and write latency data from the two single-port memories;

[0014] Starting from the point where reading and writing data interleaved from the two single-port memories ceases, a second target single-port memory is retrieved from the two single-port memories based on the state of the read enable signal and the state of the write enable signal, and any unwritten data is written to the second target single-port memory.

[0015] Preferably, the second target single-port memory is determined based on the number of unwritten data and the read / write operation status of each single-port memory in the previous clock cycle of the current clock cycle.

[0016] Preferably, the two single-port memories are single-port memory A and single-port memory B. The step of retrieving the second target single-port memory from the two single-port memories based on the state of the read enable signal and the state of the write enable signal, and writing the unwritten data to the second target single-port memory, includes:

[0017] When the write enable signal is 0 and the read enable signal is 1, or when both the write enable signal and the read enable signal are 0, the unwritten data is determined to be the data expected to be written in the previous clock cycle of the current clock cycle.

[0018] If the single-port memory A is a read operation in the previous clock cycle of the current clock cycle, then the second target single-port memory is determined to be the single-port memory A; the data to be written in the previous clock cycle of the current clock cycle is written to the single-port memory A;

[0019] If the single-port memory B is in a read operation in the previous clock cycle of the current clock cycle, then the second target single-port memory is determined to be the single-port memory B; and the data to be written in the previous clock cycle of the current clock cycle is written to the single-port memory B.

[0020] Preferably, the two single-port memories are single-port memory A and single-port memory B. The step of retrieving the second target single-port memory from the two single-port memories based on the state of the read enable signal and the state of the write enable signal, and writing the unwritten data to the second target single-port memory, includes:

[0021] When the write enable signal is 1 and the read enable signal is 0, the unwritten data is determined to be the data expected to be written in the current clock cycle and the data expected to be written in the previous clock cycle of the current clock cycle.

[0022] The second target single-port memory is determined to be the single-port memory A and the single-port memory B;

[0023] If the single-port memory A is performing a read operation in the previous clock cycle of the current clock cycle, the data expected to be written in the current clock cycle is simultaneously written to the single-port memory A, and the data expected to be written in the previous clock cycle of the current clock cycle is written to the single-port memory B.

[0024] Preferably, determining whether data is to be read or written from the same single-port memory within the same clock cycle includes:

[0025] Within the same clock cycle, acquire the value of the least significant bit of the read pointer and the value of the least significant bit of the write pointer;

[0026] If the value of the least significant bit of the read pointer is equal to the value of the least significant bit of the write pointer and the read enable signal and the write enable signal are both valid, then data to be read or written from the same single-port memory is determined within the same clock cycle.

[0027] Conversely, it is determined that data to be read or written is not from the same single-port memory within the same clock cycle.

[0028] Preferably, the method further includes:

[0029] After determining that data to be read or written from the same single-port memory is within the same clock cycle, a read / write conflict flag is added;

[0030] After the step of obtaining the second target single-port memory from the two single-port memories according to the state of the read enable signal and the state of the write enable signal, and writing the unwritten data to the second target single-port memory, the read-write conflict flag is removed.

[0031] To address the aforementioned technical problems, this application also provides a device for reading and writing data from a FIFO memory, applied to a chip containing two single-port memories, wherein the two single-port memories are obtained by splitting a dual-port memory; the device includes:

[0032] The judgment module is used to determine whether data to be read or written from the same single-port memory is within the same clock cycle when performing read and write operations; if not, the first read and write module is triggered; if so, the acquisition module, control module, and second read and write module are triggered.

[0033] The first read / write module is used to interleave read and write data from the two single-port memories;

[0034] The acquisition module is used to acquire a first target single-port memory from the two single-port memories, wherein the first target single-port memory is a single-port memory that expects to read and write data in the same clock cycle;

[0035] The control module is used to control the first target single-port memory to read data in the current clock cycle;

[0036] The second read / write module is used to interleave read and write data from the two single-port memories in the next clock cycle of the current clock cycle, wherein the data to be written is the data expected to be written in the current clock cycle.

[0037] To address the aforementioned technical problems, this application also provides a chip, comprising:

[0038] Memory, used to store computer programs;

[0039] A processor, used to execute the computer program, implements the steps of the above-described method for reading and writing data from a FIFO memory.

[0040] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned method for reading and writing data from a FIFO memory.

[0041] This application provides a method for reading and writing data in a FIFO memory, applied to a chip containing two single-port memories, which are derived from a dual-port memory. The method includes: when performing a read / write operation, determining whether data needs to be read or written from the same single-port memory within the same clock cycle; if not, interleaving read / write data from the two single-port memories; if so, obtaining a first target single-port memory from the two single-port memories, wherein the first target single-port memory is the single-port memory expected to be read or written in the same clock cycle; controlling the first target single-port memory to read data in the current clock cycle; and interleaving read / write data from the two single-port memories in the next clock cycle, wherein the data to be written is the data expected to be written in the current clock cycle. Therefore, this method uses two single-port memories to achieve simultaneous data reading and writing, thus realizing the function of simultaneous data reading and writing of a dual-port memory. Furthermore, since the area of ​​a single-port memory is much smaller than that of a dual-port memory, even if a dual-port memory is split into two single-port memories, the final FIFO memory designed with two single-port memories still has a smaller area than the FIFO memory designed with two single-port memories. Therefore, the FIFO memory of this application can optimize chip area. Secondly, under normal circumstances, a single-port memory can only write data or write data within the same clock cycle. If a single-port memory expects to read or write data in the same clock cycle, a read-write conflict will occur. Therefore, in this application, after obtaining the single-port memory where a read-write conflict occurs, a read-first approach is adopted, and then data is interleaved between the two single-port memories in the next clock cycle, except that the written data is delayed by one clock cycle. This solves the read-write conflict problem and realizes the FIFO read-write function. Finally, the method of this application does not require clock multiplication, which is beneficial for timing convergence and back-end implementation, enabling the FIFO memory to operate at higher frequencies.

[0042] In addition, this application also provides a device, chip, and computer-readable storage medium for reading and writing data in a FIFO memory, which have the same or corresponding technical features as the aforementioned method for reading and writing data in a FIFO memory, and have the same effect. Attached Figure Description

[0043] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A schematic diagram of a FIFO implementation scheme based on SPRAM design provided for an embodiment of this application;

[0045] Figure 2 A flowchart illustrating a method for reading and writing data in a FIFO memory, as provided in this application embodiment;

[0046] Figure 3 A read / write timing diagram of a SPRAM-based FIFO when no read / write conflict occurs, provided as an embodiment of this application;

[0047] Figure 4 A structural diagram of a device for reading and writing data from a FIFO memory provided in an embodiment of this application;

[0048] Figure 5 This is a structural diagram of a chip provided in another embodiment of this application;

[0049] Figure 6 A flowchart illustrating a method for implementing FIFO functionality based on SPRAM, provided in an embodiment of this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0051] The core of this application is to provide a method, apparatus, chip, and medium for reading and writing data in a FIFO memory, which can be used to implement the function of reading and writing data in a FIFO based on SPRAM.

[0052] FIFO memory is a system cache; the data stored in the FIFO first is read out first. TPRAM's read and write ports are independent, while SPRAM has only one set of control ports, making simultaneous read and write impossible. Therefore, in this embodiment, the TPRAM is split into two smaller SPRAMs. The ports of each SPRAM are time-division multiplexed, and the two SPRAMs achieve continuous read and write to the TPRAM through ping-pong or data interleaving, thus realizing the FIFO function. It should be noted that interleaving is a technique used in communication systems for data processing. An interleaver, in essence, is a device that maximizes the alteration of information structure without changing the information content. Information is distributed in various channels according to a certain pattern for read and write operations. Figure 1This is a schematic diagram illustrating a FIFO implementation scheme based on SPRAM design, provided as an embodiment of this application. For example... Figure 1 As shown, it mainly consists of four parts: write cache module 1, read / write control module 2, valid read data judgment module 3, and two SPRAM chips.

[0053] (1) The write cache module sends the write enable and write data to the read-write control module with a delay of 1 clock cycle (i.e., a delay of 1 clock cycle), and the read-write control module decides whether to use the data with a delay of 1 clock cycle.

[0054] (2) The read / write control module is the core of this design. It maps write enable and read enable to wr_ptr and rd_ptr, and then converts them into read / write control signals for the two SPRAMs based on the current read / write status. It determines whether to write the original write data or write data with a 1-clock delay based on the current write enable, read enable, wr_ptr and rd_ptr.

[0055] (3) Valid read data judgment module, based on the chip select signal and write enable signal of the two SPRAMs, determines which SPRAM has valid read data output;

[0056] (4) Two SPRAM chips are used for interleaving read and write operations.

[0057] The key to the feasibility of this application's solution lies in replacing the function of TPRAM by interleaving the read and write operations of two SPRAM chips.

[0058] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. This application provides a method for reading and writing data to a FIFO memory, applied to a chip containing two single-port memories, wherein the two single-port memories are obtained by splitting a dual-port memory. Figure 2 A flowchart illustrating a method for reading and writing data in a FIFO memory, as provided in this application embodiment, is shown below. Figure 2 As shown, the method includes:

[0059] S10: When performing a read / write operation, determine whether data to be read or written is from the same single-port memory within the same clock cycle; if not, proceed to step S11; if yes, proceed to steps S12 to S14.

[0060] S11: Interleaved reading and writing of data from two single-port memories;

[0061] S12: Obtain the first target single-port memory from the two single-port memories;

[0062] Among them, the first target single-port memory is a single-port memory that expects to read and write data in the same clock cycle;

[0063] S13: Control the first target single-port memory to read data in the current clock cycle;

[0064] S14: Interleave read and write data from the two single-port memories in the next clock cycle of the current clock cycle;

[0065] The data to be written is the data expected to be written in the current clock cycle.

[0066] In this embodiment, two SPRAMs are used instead of TPRAM. Since SPRAM has only one set of control ports, simultaneous read and write operations are not possible. Therefore, during read / write operations, if data to be read or written (here, "to be read / written" refers to data to be read and data to be written) is not from the same single-port memory within the same clock cycle, no read / write conflict will occur; otherwise, a read / write conflict is considered to have occurred. Assume the two SPRAMs are SPRAM_A and SPRAM_B, with a FIFO depth of 8, and the address ranges of the write pointer wr_ptr and read pointer rd_ptr are [0, 7]. Since the FIFO depth is 8, the depths of both SPRAM_A and SPRAM_B are 4. Figure 3 This application provides a timing diagram for reading and writing a SPRAM-based FIFO when no read / write conflict occurs. Figure 3 In the SPRAM configuration, FIFO read enable -rden, FIFO write enable -wren, FIFO write data -wrdata, write pointer -wr_ptr, read pointer -rd_ptr, SPRAM chip select signal -csb, SPRAM write enable signal -wen, SPRAM write address -addr, SPRAM write data -data, SPRAM read data -q. For example... Figure 3 As shown, starting from time T2, eight data entries are continuously written to the FIFO; starting from time T3, eight data entries are continuously read from the FIFO. When the write enable is pulled high, wr_ptr increments accordingly, and when the read enable is pulled high, rd_ptr increments accordingly. wr_ptr[0] is used to determine which SPRAM to write to, and wr_ptr[N-1:1] is used to determine which address of the SPRAM to write to. The same applies to reading. In this way, writing data is actually storing it sequentially into SPRAM_A / SPRAM_B / SPRAM_A / SPRAM_B, and reading data is reading it sequentially into SPRAM_B / SPRAM_A / SPRAM_B / SPRAM_A. That is, reading and writing alternate between the two SPRAMs. This situation is called "read-write interleaving". In this way, SPRAM can be used to replace TPRAM to implement the FIFO function.

[0067] Besides read-write interleaving, when both FIFO read and write are enabled and wr_ptr[0] = rd_ptr[0], both read and write operations point to the same SPRAM, and read-write interleaving cannot continue. This situation is called "read-write conflict". In this case, a read-first strategy is adopted, rd_ptr increments normally, and the conflicting SPRAM, i.e., the first target SPRAM, only responds to read operations. The write data uses data delayed by 1 clock cycle, and the write is performed in the next clock cycle, incrementing wr_ptr. Since wr_ptr[0] and rd_ptr[0] are not equal in the next clock cycle after the conflict, it is equivalent to returning to the "read-write interleaving" state. The only difference is that the write data uses data delayed by 1 clock cycle, and this state can be called "read-write interleaving-conflict" (CLASH_RW).

[0068] This embodiment provides a method for reading and writing data in a FIFO memory, applied to a chip containing two single-port memories, which are derived from a dual-port memory. The method includes: when performing a read / write operation, determining whether data needs to be read or written from the same single-port memory within the same clock cycle; if not, interleaving read / write data from the two single-port memories; if so, obtaining a first target single-port memory from the two single-port memories, wherein the first target single-port memory is the single-port memory expected to be read or written in the same clock cycle; controlling the first target single-port memory to read data in the current clock cycle; and interleaving read / write data from the two single-port memories in the next clock cycle, wherein the data to be written is the data expected to be written in the current clock cycle. Therefore, this method uses two single-port memories to achieve simultaneous data reading and writing, thus realizing the function of simultaneous data reading and writing of a dual-port memory. Furthermore, since the area of ​​a single-port memory is much smaller than that of a dual-port memory, even if a dual-port memory is split into two single-port memories, the final FIFO memory designed with two single-port memories still has a smaller area than the FIFO memory designed with two single-port memories. Therefore, the FIFO memory in this embodiment can optimize chip area. Secondly, under normal circumstances, a single-port memory can only write data or write data within the same clock cycle. If a single-port memory expects to read or write data in the same clock cycle, a read-write conflict will occur. Therefore, in this embodiment, after obtaining the single-port memory where a read-write conflict occurs, a read-first approach is adopted, and then data is interleaved between the two single-port memories in the next clock cycle, except that the written data is delayed by one clock cycle. This solves the read-write conflict problem and realizes the FIFO read-write function. Finally, the method in this embodiment does not require clock frequency multiplication, which is beneficial for timing convergence and back-end implementation, enabling the FIFO memory to operate at higher frequencies.

[0069] Based on the above embodiments, when entering the "read-write interleaving-conflict" state, reading and writing can still proceed normally, but the write data is delayed by one clock cycle. To eliminate the one-cycle delay and restore the normal interleaved read-write state, a preferred implementation is that, after interleaving read and write data from the two single-port memories in the next clock cycle of the current clock cycle, the method for reading and writing data to the FIFO memory further includes:

[0070] Get the status of the read enable signal and the write enable signal;

[0071] Determine whether the read enable signal and write enable signal are continuously valid;

[0072] If not, then stop interleaving read data and write latency data from the two single-port memories;

[0073] Starting from the point where reading and writing data interleaved between the two single-port memories ceases, the second target single-port memory is retrieved from the two single-port memories based on the state of the read enable signal and the state of the write enable signal, and the unwritten data is written to the second target single-port memory; wherein, the second target single-port memory is determined based on the number of unwritten data and the read and write operation status of each single-port memory in the previous clock cycle of the current clock cycle.

[0074] The read enable signal and write enable signal are either 0 or 1. This is illustrated using two single-port memories, SPRAM_A and SPRAM_B. Tables 1 to 4 show the SPRAM states corresponding to different read and write enable signal states. Specifically, Table 1 shows the SPRAM states when both write enable and read enable are 1 after entering the "read-write interleaved-conflict" state; Table 2 shows the SPRAM states when both write enable and read enable are 0 after entering the "read-write interleaved-conflict" state; Table 3 shows the SPRAM states when both write enable and read enable are 0 after entering the "read-write interleaved-conflict" state; and Table 4 shows the SPRAM states when both write enable and read enable are 1 after entering the "read-write interleaved-conflict" state.

[0075] Table 1 shows the SPRAM states when write enable = 1 and read enable = 1 after entering the "read-write interleaved-conflict" state.

[0076]

[0077]

[0078] Table 2 shows the SPRAM states when the write enable is 0 and the read enable is 1 after entering the "read-write interleaved-conflict" state.

[0079]

[0080] Table 3 shows the SPRAM states when write enable = 0 and read enable = 0 after entering the "read-write interleaved-conflict" state.

[0081]

[0082] Table 4 shows the SPRAM states when the write enable is 1 and the read enable is 0 after entering the "read-write interleaved-conflict" state.

[0083]

[0084]

[0085] In this embodiment, the read enable signal and write enable signal are either 1 or 0. As shown in Table 1, conflict state 1: During clock cycle T4, write enable = 1 and read enable = 1, thus maintaining the "read-write interleaving-conflict" (CLASH_RW) state. Interleaved read and write operations are possible, but the written data will be delayed by one clock cycle. Discontinuous read and write enable signals refer to situations where neither the read enable signal nor the write enable signal is entirely 1. In Tables 2 to 4, if neither the read enable signal nor the write enable signal is entirely 1, i.e., the read enable signal and the write enable signal are discontinuous, then interleaved read and write operations cannot be performed as shown in Table 1. However, this can be used as an opportunity to eliminate delayed data writes and restore the normal interleaved read and write state.

[0086] To eliminate data delays, unwritten data can be written to the SPRAM based on the states of the read enable and write enable signals. It's important to note that the unwritten data here includes data that is delayed in being written, or data expected to be written in the current clock cycle, determined specifically by the states of the read enable and write enable signals. The SPRAM_A or SPRAM_B to which unwritten data is written is determined based on the read / write operation states of SPRAM_A and SPRAM_B in the previous clock cycle. As shown in Table 2, time T4 is considered the current clock cycle. In the previous clock cycle, T3, SPRAM_A performed a write operation and SPRAM_B performed a read operation. Therefore, in the current clock cycle T4, SPRAM_A performs a read operation and SPRAM_B performs a write operation, achieving read / write interleaving.

[0087] This embodiment eliminates delayed data, enabling a return to normal interleaved read / write operations.

[0088] In practice, to restore the normal read-write interleaving state, a preferred implementation involves retrieving the second target single-port memory from the two single-port memories based on the state of the read enable signal and the state of the write enable signal, and writing the unwritten data to the second target single-port memory, including:

[0089] When the write enable signal is 0 and the read enable signal is 1, or when both the write enable signal and the read enable signal are 0, the unwritten data is determined to be the data expected to be written in the previous clock cycle of the current clock cycle.

[0090] If a read operation is performed on single-port memory A in the previous clock cycle of the current clock cycle, then the second target single-port memory is determined to be single-port memory A; the data to be written in the previous clock cycle of the current clock cycle is written to single-port memory A.

[0091] If a read operation is performed on single-port memory B in the previous clock cycle of the current clock cycle, then the second target single-port memory is determined to be single-port memory B; the data to be written in the previous clock cycle of the current clock cycle is written to single-port memory B.

[0092] A write enable signal and a read enable signal of 0 indicate that the signal is not pulled high; a write enable signal and a read enable signal of 1 indicate that the signal is pulled high. The situation described in this embodiment can be explained in conjunction with Tables 2 and 3 above. As shown in Tables 2 and 3, conflict state 2: In clock cycle T4, if write enable = 0 and read enable = 1, or write enable = 0 and read enable = 0, theoretically, write enable = 0 and no data should be written. However, because delayed data has been used previously, there will still be one clock cycle of data to be written. This action is called "delayed write" (WR_DLY). Furthermore, write enable = 0 at this time, indicating that there is no new data to be written on the FIFO port. In this way, all the data to be written in the FIFO has been written to the SPRAM, thus exiting the "read-write interleaving-conflict" state and returning to the normal read-write state.

[0093] The above embodiments describe one method for restoring to a normal read-write interleaved state. This embodiment also provides another method for restoring to a normal read-write interleaved state, as follows: Based on the state of the read enable signal and the state of the write enable signal, a second target single-port memory is obtained from two single-port memories, and unwritten data is written to the second target single-port memory, including:

[0094] When the write enable signal is 1 and the read enable signal is 0, the data that has not been written is determined to be the data expected to be written in the current clock cycle and the data expected to be written in the previous clock cycle.

[0095] The second target single-port memory is determined to be single-port memory A and single-port memory B;

[0096] If a read operation is performed on single-port memory A in the previous clock cycle of the current clock cycle, the data expected to be written in the current clock cycle is simultaneously written to single-port memory A, and the data expected to be written in the previous clock cycle of the current clock cycle is written to single-port memory B.

[0097] Conflict State 3: As shown in Table 4, during clock cycle T4, write enable = 1 and read enable = 0. At this time, only write operations occur, and no read operations occur. Therefore, theoretically, only one SPRAM chip should be controlled. However, there are actually two data items to be written in the FIFO: the first is the delayed data from the previous clock cycle, WDATA_1DLY, and the second is the data to be written on the current port, WDATA. Taking advantage of the fact that only one SPRAM chip is controlled, the delayed data WDATA_1DLY is written to the address corresponding to the current wr_ptr, and the undelayed data WDATA is written to the address wr_ptr+1. This action is called "all write" (JUMP). In this way, the "read-write interleaving-conflict" state is exited using this gap, and normal read / write operation is restored.

[0098] In practice, to improve the efficiency of reading and writing data, a preferred implementation is to determine in advance whether data is to be read or written from the same SPRAM before reading or writing data. When making this determination, a preferred implementation includes determining whether data to be read or written from the same single-port memory within the same clock cycle, which includes:

[0099] Obtain the value of the least significant bit of the read pointer and the least significant bit of the write pointer within the same clock cycle;

[0100] When the value of the least significant bit of the read pointer is equal to the value of the least significant bit of the write pointer, and the read enable signal and the write enable signal are both valid, data to be read or written from the same single-port memory within the same clock cycle is determined.

[0101] Conversely, it indicates that data to be read or written is not from the same single-port memory within the same clock cycle.

[0102] The embodiment provided can determine whether there is a situation where data is to be read or written from the same single-port memory in the same clock cycle based on the least significant bit of the read pointer and write pointer, that is, whether a read-write conflict will occur.

[0103] In practice, to facilitate user awareness of read / write conflicts, a preferred implementation method for reading and writing data in a FIFO memory further includes:

[0104] After determining that data to be read or written from the same single-port memory within the same clock cycle is being read or written, a read / write conflict flag is added.

[0105] After retrieving the second target single-port memory from the two single-port memories based on the state of the read enable signal and the state of the write enable signal, and writing the unwritten data to the second target single-port memory, the read-write conflict flag is removed.

[0106] The read / write conflict flag is not limited. As shown in Tables 1 to 4 above, after a read / write conflict occurs, it is marked as 1 to indicate the existence of a read / write conflict. It should be noted that in Tables 1 to 4, clock cycle T2 represents the clock cycle in which a read / write conflict occurs. However, since the data written in clock cycles T3 and T4 is delayed, this state can be considered abnormal read / write data. Therefore, in Tables 1 to 4, the read / write conflict flag in T3 and T4 is still recorded as 1. After eliminating the delayed data, the read / write conflict flag can be removed. This removal does not completely cancel the read / write conflict flag; it only signifies that a read / write conflict does not exist. For example, after eliminating the data, the previous read / write conflict flag of 1 can be changed to 0 to represent that no read / write conflict exists.

[0107] The read / write conflict flag provided in this embodiment allows users to intuitively understand whether a read / write conflict exists.

[0108] The above embodiments have described in detail the method for reading and writing data to the FIFO memory. This application also provides embodiments of the apparatus and chip for reading and writing data to the FIFO memory. It should be noted that this application describes the embodiments of the apparatus from two perspectives: one is based on the functional modules, and the other is based on the hardware.

[0109] Figure 4 A structural diagram of a device for reading and writing data to a FIFO memory provided in an embodiment of this application. This embodiment, based on functional modules, includes:

[0110] The judgment module 10 is used to determine whether data to be read or written from the same single-port memory within the same clock cycle when performing read and write operations; if not, the first read and write module 11 is triggered; if so, the acquisition module 12, the control module 13, and the second read and write module 14 are triggered.

[0111] The first read / write module 11 is used for interleaved read / write of data from two single-port memories;

[0112] The acquisition module 12 is used to acquire a first target single-port memory from two single-port memories, wherein the first target single-port memory is a single-port memory that expects to read and write data in the same clock cycle;

[0113] Control module 13 is used to control the first target single-port memory to read data in the current clock cycle;

[0114] The second read / write module 14 is used to interleave read and write data from two single-port memories in the next clock cycle of the current clock cycle, wherein the data to be written is the data expected to be written in the current clock cycle.

[0115] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0116] The device for reading and writing data in the FIFO memory provided in this embodiment has corresponding technical features to the method for reading and writing data in the FIFO memory described above. The method for reading and writing data in the FIFO memory has been described in detail above, and the embodiment of the device for reading and writing data in the FIFO memory will not be described again here, but the effect is the same as above.

[0117] Figure 5 This is a structural diagram of a chip provided in another embodiment of this application. This embodiment is based on a hardware perspective, such as... Figure 5 As shown, the chip includes:

[0118] Memory 20 is used to store computer programs;

[0119] The processor 21 is configured to execute a computer program to implement the steps of the method for reading and writing data in the FIFO memory as described in the above embodiments.

[0120] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0121] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the FIFO memory read / write data method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the aforementioned FIFO memory read / write data method.

[0122] In some embodiments, the chip may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0123] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on the chip and may include more or fewer components than illustrated.

[0124] The chip provided in this application embodiment includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: the method of reading and writing data in the FIFO memory, with the same effect as above.

[0125] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiments.

[0126] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0127] The computer-readable storage medium provided in this application includes the aforementioned method for reading and writing data from a FIFO memory, with the same effect.

[0128] To enable those skilled in the art to better understand the present application, the following description is provided in conjunction with the appendix. Figure 6 The present application will be further described in detail with reference to specific embodiments. Figure 6 A flowchart illustrating a method for implementing FIFO functionality based on SPRAM, provided as an embodiment of this application. Figure 6 As shown, the method includes:

[0129] S15: Determine if a read / write conflict has occurred in the FIFO; if not, proceed to step S16; if yes, proceed to step S17.

[0130] S16: Interleaved reading and writing of data between two SPRAM chips;

[0131] S17: The enable for writing data to SPRAM is delayed by 1 clock cycle, and the written data is used after the 1-clock delay.

[0132] S18: Determine if the read / write enable is discontinuous; if not, return to step S17; if yes, proceed to step S19.

[0133] S19: Determine if write enable is high and read enable is low at this time; if not, proceed to step S20; if yes, proceed to step S21.

[0134] S20: Write the data after a 1-second delay, and return to step S15;

[0135] S21: Simultaneously write the data after a 1-beat delay and the current-beat data to the two SPRAMs respectively, and return to step S15.

[0136] In this embodiment, the TPRAM is replaced with two SPRAMs of half capacity. A read-write interleaving method is used, alternating read and write operations on the two SPRAMs. When a read-write conflict occurs, data is delayed by one clock cycle to continue the interleaved read-write operation, and then the conflict state is exited. Compared to traditional TPRAM-based FIFOs, the SPRAM-based FIFO in this embodiment effectively replaces the functionality of traditional TPRAM-based FIFOs, with timing and performance essentially identical to traditional TPRAM-based FIFOs, allowing for seamless user switching. Since SPRAM is much smaller than TPRAM, even if one TPRAM is split into two SPRAMs, the SPRAM solution still has a smaller area, giving this solution an area advantage. This embodiment supports continuous, back-to-back read and write operations, achieving a throughput close to 100% of the efficiency of traditional FIFOs, resulting in higher performance. It eliminates the need for clock multiplication, which is beneficial for timing convergence and back-end implementation, allowing operation at higher frequencies.

[0137] In summary, the SPRAM-based FIFO proposed in this application not only effectively replaces the traditional TPRAM-based FIFO function, but also has a smaller area, higher performance and operating frequency, and greater versatility. Furthermore, it should be noted that the FIFO implemented in this application is a non-prefetch FIFO, meaning that valid data is only received on the second clock cycle after the read enable is pulled high. If a prefetch FIFO is required in engineering practice, a prefetch buffer can be added at the output point, and data can be moved into the prefetch FIFO while the prefetch buffer is not empty.

[0138] The foregoing has provided a detailed description of the method, apparatus, chip, and medium for reading and writing data in a FIFO memory provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0139] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for reading and writing data from a FIFO memory, characterized by, The method is applied to a chip comprising two single-port memories, which are split from a double-port memory, and comprises: In the case of performing read / write operations, it is determined whether data to be read / written is from the same single-port memory in the same clock cycle; If not, interleaved read / write data is obtained from the two single-port memories; If yes, a first target single-port memory is obtained from the two single-port memories, wherein the first target single-port memory is the single-port memory of the data to be read / written in the same clock cycle; the first target single-port memory is controlled to read data in the current clock cycle; interleaved read / write data is obtained from the two single-port memories in the next clock cycle of the current clock cycle, wherein the write data is the data to be written in the current clock cycle; after the interleaved read / write data is obtained from the two single-port memories in the next clock cycle of the current clock cycle, the method further comprises: The state of a read enable signal and the state of a write enable signal are obtained; It is determined whether the read enable signal and the write enable signal are continuously valid; If not, the interleaved read data and the delayed write data from the two single-port memories are stopped; Since the interleaved read data and the delayed write data from the two single-port memories are stopped, a second target single-port memory is obtained from the two single-port memories according to the state of the read enable signal and the state of the write enable signal, and the data not written is written into the second target single-port memory.

2. The method of reading and writing data from the FIFO memory of claim 1, wherein, The second target single-port memory is determined according to the number of the data not written and the read / write operation status of each single-port memory in the last clock cycle of the current clock cycle.

3. The method of reading and writing data from the FIFO memory of claim 2, wherein, The two single-port memories are single-port memory A and single-port memory B, and the second target single-port memory obtained from the two single-port memories according to the state of the read enable signal and the state of the write enable signal and the data not written written into the second target single-port memory comprises: In the case that the write enable signal is 0 and the read enable signal is 1, or the write enable signal and the read enable signal are both 0, it is determined that the data not written is the data to be written in the last clock cycle of the current clock cycle; In the case that the single-port memory A is in read operation in the last clock cycle of the current clock cycle, it is determined that the second target single-port memory is the single-port memory A; the data to be written in the last clock cycle of the current clock cycle is written into the single-port memory A; In the case that the single-port memory B is in read operation in the last clock cycle of the current clock cycle, it is determined that the second target single-port memory is the single-port memory B; the data to be written in the last clock cycle of the current clock cycle is written into the single-port memory B.

4. The method of reading and writing data from the FIFO memory of claim 2, wherein, The two single-port memories are single-port memory A and single-port memory B, and the step of obtaining a second target single-port memory from the two single-port memories according to the state of the read enable signal and the state of the write enable signal and writing the unwritten data into the second target single-port memory comprises: In the case that the write enable signal is 1 and the read enable signal is 0, it is determined that the unwritten data is data to be written in the current clock cycle and data to be written in the last clock cycle of the current clock cycle; It is determined that the second target single-port memory is the single-port memory A and the single-port memory B; In the case that the single-port memory A is in a read operation in the last clock cycle of the current clock cycle, the data to be written in the current clock cycle is written into the single-port memory A and the data to be written in the last clock cycle of the current clock cycle is written into the single-port memory B.

5. The method of reading and writing data from the FIFO memory of claim 1, wherein, The step of determining whether data to be read and written is from the same single-port memory in the same clock cycle comprises: In the same clock cycle, the value of the least significant bit of a read pointer and the value of the least significant bit of a write pointer are obtained; In the case that the value of the least significant bit of the read pointer is equal to the value of the least significant bit of the write pointer and the read enable signal and the write enable signal are simultaneously effective, it is determined that data to be read and written is from the same single-port memory in the same clock cycle; Otherwise, it is determined that data to be read and written is not from the same single-port memory in the same clock cycle.

6. The method of reading and writing data from a FIFO memory according to any one of claims 1 to 5, wherein, The method further comprises: After it is determined that data to be read and written is from the same single-port memory in the same clock cycle, a read-write conflict flag is added; After the step of obtaining a second target single-port memory from the two single-port memories according to the state of the read enable signal and the state of the write enable signal and writing the unwritten data into the second target single-port memory, the read-write conflict flag is removed.

7. An apparatus for reading and writing data in a FIFO memory, characterized by The application is applied to a chip comprising two single-port memories, and the two single-port memories are obtained by splitting a dual-port memory; the device comprises: A judgment module is configured to determine whether data to be read and written is from the same single-port memory in the same clock cycle in the case of performing a read-write operation; if not, a first read-write module is triggered; if yes, an obtaining module, a control module and a second read-write module are triggered; The first read-write module is configured to interleave read-write data from the two single-port memories; The obtaining module is configured to obtain a first target single-port memory from the two single-port memories, wherein the first target single-port memory is the single-port memory of data to be read and written in the same clock cycle; The control module is configured to control the first target single-port memory to read data in a current clock cycle; The second read-write module is configured to interleave read and write data from the two single-port memories in a next clock cycle of the current clock cycle, wherein the write data is data to be written in the current clock cycle; After interleaving read and write data from the two single-port memories in the next clock cycle of the current clock cycle, the method further comprises: obtaining a state of a read enable signal and a state of a write enable signal; determining whether the read enable signal and the write enable signal are continuously valid; if not, stopping interleaving read data and write delayed data from the two single-port memories; starting from the step of stopping interleaving read data and write delayed data from the two single-port memories, obtaining a second target single-port memory from the two single-port memories according to the state of the read enable signal and the state of the write enable signal, and writing the data not written into the second target single-port memory.

8. A chip, characterized by comprise: a memory configured to store a computer program; a processor configured to implement the steps of the method for reading and writing data of the FIFO memory according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and the computer program is executed by the processor to implement the steps of the method for reading and writing data of the FIFO memory according to any one of claims 1 to 6.

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