Method for forming metal silicide

Abstract

The application discloses a metal silicide forming method, which comprises the following steps: providing a substrate, forming a gate dielectric layer on the substrate, forming a gate electrode on the gate dielectric layer, forming a side wall on the periphery of the gate electrode, and forming a heavily doped region in the substrate on both sides of the side wall; forming a first metal layer by sputtering deposition through a first target material, the first target material comprising nickel and platinum, and the first metal layer covering the exposed areas of the substrate, the gate dielectric layer, the gate electrode and the side wall; forming a second metal layer on the first metal layer by sputtering deposition through a second target material, the second target material comprising nickel and platinum, and the content of platinum in the second target material being higher than that in the first target material; and performing heat treatment to form metal silicide in the gate electrode and the heavily doped region. The first metal layer and the second metal layer are sequentially deposited on the substrate, the content of platinum in the target material used for depositing the first metal layer is less than that in the target material used for depositing the second metal layer, the silicon loss and the junction depth are reduced, and the reliability and yield of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for forming metal silicides. Background Technology

[0002] Metal silicides are metallic compounds formed by the reaction of metals (such as titanium (Ti), cobalt (Co), nickel platinum (NiPt), etc.) and silicon. Their electrical conductivity is between that of metals and silicon.

[0003] In the semiconductor manufacturing industry, self-aligned silicide (Salicide) refers to the formation of metal silicides by reacting with silicon in contact with a metal, while simultaneously reacting with dielectric materials that cannot be contacted (such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), etc.), thereby achieving self-alignment. Metal silicides are formed in the active region and gate of semiconductor devices to reduce sheet resistance and contact resistance.

[0004] Taking nickel silicide as an example, as semiconductor manufacturing processes become more advanced and refined, the feature size of semiconductor device structures is getting smaller and smaller. In the process of forming metal silicides, the thickness of the nickel-platinum layer formed is also getting thinner and thinner, and it is easy to agglomerate after heat treatment. In view of this, in related technologies, below the 40 nanometer (nm) process, the stability of nickel silicide can be improved by increasing the platinum content in the nickel-platinum target.

[0005] However, increasing the platinum content in the nickel-platinum target leads to severe silicon loss (especially in NOR flash memory devices), deeper junction depth, and affects the normal operation of the device, thereby reducing the device's reliability. Summary of the Invention

[0006] This application provides a method for forming metal silicides, which can solve the problem of severe silicon loss caused by increasing the platinum content in the nickel-platinum target material in the metal silicide fabrication process provided in the related technology. The method includes:

[0007] A substrate is provided, on which a gate dielectric layer is formed, a gate is formed on the gate dielectric layer, a sidewall is formed around the gate, and heavily doped regions are formed in the substrate on both sides outside the sidewall;

[0008] A first metal layer is formed by sputtering deposition using a first target material comprising nickel and platinum, and the first metal layer covers the substrate, the gate dielectric layer, the gate, and the exposed areas of the sidewalls.

[0009] A second metal layer is formed by sputtering deposition on the first metal layer using a second target, wherein the second target comprises nickel and platinum, and the platinum content in the second target is higher than the platinum content in the first target.

[0010] A heat treatment is performed to form metal silicides in the gate and the heavily doped region.

[0011] In some embodiments, the platinum content in the first target is less than 7%.

[0012] In some embodiments, the platinum content in the first target is less than 5%.

[0013] In some embodiments, the platinum content in the second target material is greater than 7%.

[0014] In some embodiments, the platinum content in the second target material is greater than 10%.

[0015] In some embodiments, the sidewall comprises, from the inside out, a first oxide layer, a first nitriding layer, a second oxide layer, and a second nitriding layer.

[0016] In some embodiments, an LDD-doped region is formed in the substrate between the gate and the heavily doped region, and a pocket implantation region is formed in the substrate between the gate and the LDD-doped region.

[0017] The technical solution of this application has at least the following advantages:

[0018] By sequentially depositing a first metal layer and a second metal layer on a substrate on which a semiconductor device is formed, wherein the platinum content in the target material used to deposit the first metal layer is less than the platinum content in the target material used to deposit the second metal layer, the silicon loss and push-in depth are reduced while ensuring the thermal stability of the formed metal silicide, thereby improving the reliability and yield of the device to a certain extent. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a method for forming metal silicides provided in an exemplary embodiment of this application;

[0021] Figures 2 to 5 This is a schematic diagram of the formation of a metal silicide provided in an exemplary embodiment of this application. Detailed Implementation

[0022] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0025] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0026] refer to Figure 1 It illustrates a flowchart of a method for forming metal silicides according to an exemplary embodiment of this application, which can be applied to the fabrication process of NOR flash memory devices, such as... Figure 1 As shown, the method includes:

[0027] Step S1: A substrate is provided, a gate dielectric layer is formed on the substrate, a gate is formed on the gate dielectric layer, a sidewall is formed around the gate, and heavily doped regions are formed in the substrate on both sides outside the sidewall.

[0028] refer to Figure 2 This shows a schematic cross-sectional view before the formation of the first metal layer. For example, as shown... Figure 2As shown, a gate dielectric layer 220 is formed on the substrate 210, a gate 230 is formed on the gate dielectric layer 220, and a sidewall is formed around the gate 230. The sidewall includes a first oxide layer 241, a first nitride layer 242, a second oxide layer 243, and a second nitride layer 244 from the inside to the outside.

[0029] Heavily doped regions 211 are formed in the substrates 210 on both sides of the sidewalls. Lightly doped drain (LDD) doped regions 212 are formed in the substrate 210 between the gate 230 and the heavily doped regions 211. Pocket implantation regions 213 are formed in the substrate 210 between the gate 230 and the LDD doped regions 212.

[0030] In this region, the impurity concentration in the heavily doped region 211 is greater than that in the LDD-doped region 212 and the pocket implantation region 213. The impurity types in the heavily doped region 211 and the LDD-doped region 212 are the same, while the impurity types in the heavily doped region 211 and the pocket implantation region 213 are different. For example, if the impurity types in the heavily doped region 211 and the LDD-doped region 212 are P (positive), then the impurity type in the pocket implantation region 213 is N (negative); if the impurity types in the heavily doped region 211 and the LDD-doped region 212 are N, then the impurity type in the pocket implantation region 213 is P.

[0031] Step S2: A first metal layer is formed by sputtering deposition of a first target material, the first target material including nickel and platinum, and the first metal layer covers the substrate, the gate dielectric layer, the gate and the exposed sidewall area.

[0032] refer to Figure 3 It shows a schematic cross-sectional view after the formation of the first metal layer. For example, as shown... Figure 3 As shown, the first metal layer 251 covers the substrate 210, the gate dielectric layer 220, the gate 230, and the exposed sidewall area. The platinum content in the first target is less than 7% (e.g., it can be less than 5%, including 5%). The first metal layer 251 is formed by sputtering deposition using a first target with a low platinum content. During subsequent heat treatment, the platinum in the first metal layer 251 preferentially reacts with the silicon (Si) in the substrate 210 compared to nickel. Due to its lower platinum content, silicon loss is also lower, the push-in depth is shallower, and the impact on the device is smaller.

[0033] Step S3: A second metal layer is formed by sputtering deposition on the first metal layer using a second target material. The second target material includes nickel and platinum, and the platinum content in the second target material is higher than the platinum content in the first target material.

[0034] refer to Figure 4 This shows a schematic cross-sectional view after the formation of the second metal layer. For example, as shown... Figure 4As shown, a second metal layer 252 is formed on the first metal layer 251. The platinum content in the second target is greater than 7% (e.g., it can be greater than 10%, including 10%). The second metal layer 252 is formed by sputtering deposition using a second target with a high platinum content, ensuring the thermal stability of the metal silicide and preventing agglomeration during subsequent heat treatment.

[0035] Step S4 involves heat treatment to form metal silicides in the gate and heavily doped regions.

[0036] refer to Figure 5 It shows a schematic cross-sectional view after the formation of metal silicide. For example... Figure 5 As shown, after heat treatment, metal silicide 253 (which is nickel silicide) is formed in the gate 230 and the heavily doped region 211.

[0037] In summary, in the embodiments of this application, by sequentially depositing a first metal layer and a second metal layer on a substrate on which a semiconductor device is formed, wherein the platinum content in the target material used to deposit the first metal layer is less than the platinum content in the target material used to deposit the second metal layer, the thermal stability of the formed metal silicide is ensured, while silicon loss and push-in depth are reduced, thereby improving the reliability and yield of the device to a certain extent.

[0038] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for forming a metal silicide, characterized in that, include: A substrate is provided, on which a gate dielectric layer is formed, a gate is formed on the gate dielectric layer, a sidewall is formed around the gate, and heavily doped regions are formed in the substrate on both sides outside the sidewall; A first metal layer is formed by sputtering deposition using a first target material comprising nickel and platinum, and the first metal layer covers the substrate, the gate dielectric layer, the gate, and the exposed areas of the sidewalls. A second metal layer is formed by sputtering deposition on the first metal layer using a second target, wherein the second target comprises nickel and platinum, and the platinum content in the second target is higher than the platinum content in the first target. A heat treatment is performed to form metal silicides in the gate and the heavily doped region.

2. The method according to claim 1, characterized in that, The platinum content in the first target material is less than 7%.

3. The method according to claim 2, characterized in that, The platinum content in the first target material is less than 5%.

4. The method according to claim 2, characterized in that, The platinum content in the second target material is greater than 7%.

5. The method according to claim 4, characterized in that, The platinum content in the second target material is greater than 10%.

6. The method according to any one of claims 1 to 5, characterized in that, The sidewall, from the inside out, comprises a first oxide layer, a first nitriding layer, a second oxide layer, and a second nitriding layer.

7. The method according to claim 6, characterized in that, An LDD-doped region is formed in the substrate between the gate and the heavily doped region, and a pocket implantation region is formed in the substrate between the gate and the LDD-doped region.

Images