A method for fabricating a parasitic Zener diode

Abstract

This invention provides a method for fabricating a parasitic Zener diode. First and second P-wells are formed in a P-type epitaxial layer on an N-type buried oxide layer. A first STI region is formed on one side of the first P-well; a second STI region is formed on the side of the second P-well. A polysilicon layer is deposited and etched to remove the polysilicon layer outside the space between the first and second P-wells. The remaining area on the polysilicon layer is opened using photolithography. A P-type body region is formed in the P-type epitaxial layer between the first and second P-wells. A portion of the first polysilicon structure in the opened area is removed, and the remaining portion near the first STI region is formed as a second polysilicon structure. The remaining portion near the second STI region is formed as a third polysilicon structure. The gate oxide layer below the second and third polysilicon structures is removed. This invention uses P-type body region implantation in SNLDMOS to form the N+ and P-type body regions for use in Zener diodes, eliminating the need for additional photomasks, simplifying the process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a parasitic Zener diode. Background Technology

[0002] Zener diodes are commonly used protective device structures in semiconductor manufacturing processes. Their fabrication is generally achieved by adding Zener injection, which requires the addition of a corresponding mask. This makes the process complex and cumbersome, resulting in time and labor costs, and also reduces product yield due to the complexity of the process. Therefore, a new method is needed to solve the above problems. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating a parasitic Zener diode, which solves the problem that the fabrication of Zener diodes in the prior art requires Zener injection, resulting in a complex process.

[0004] To achieve the above and other related objectives, the present invention provides a method for fabricating a parasitic Zener diode, comprising at least:

[0005] Step 1: Provide a P-type epitaxial layer, wherein an N-type buried oxide layer is formed in the P-type epitaxial layer; a first P-well and a second P-well are formed in the P-type epitaxial layer above the N-type buried oxide layer, spaced apart from each other; a gate oxide layer is formed on the upper surface of the P-type epitaxial layer; a first STI region is formed on the side of the first P-well near the second P-well, and a second STI region is formed on the side of the second P-well near the first P-well, and connected to the second P-well.

[0006] Step 2: Deposit a polycrystalline silicon layer on the gate oxide layer;

[0007] Step 3: Etch the polysilicon layer to remove the polysilicon layer above the gate oxide layer and located between the first P-well and the second P-well; the remaining polysilicon layer forms the first polysilicon structure.

[0008] Step 4: Spin-coat photoresist and photolithographically open the region on the first polysilicon structure located between the first and second STI regions; then implant boron and arsenic into the P-type epitaxial layer between the first and second P-wells through the photolithographically opened region to form a P-type body region;

[0009] Step 5: Using the remaining photoresist as a mask, etch away a portion of the first polysilicon structure in the area where the photolithography was opened; the portion of the remaining first polysilicon structure near the first STI region is formed as a second polysilicon structure; the portion of the remaining first polysilicon structure near the second STI region is formed as a third polysilicon structure.

[0010] Step 6: Remove any remaining photoresist;

[0011] Step 7: Etch away the gate oxide layers located outside the second and third polysilicon structures respectively; and form a first N+ region in the P-type body region between the second and third polysilicon structures; then perform annealing.

[0012] Preferably, in step one, the bottom of the first P-well and the second P-well are located on the upper surface of the N-type buried oxide layer, and the top of each is flush with the upper surface of the P-type epitaxial layer.

[0013] Preferably, in step one, a first N-well and a second N-well are formed in the P-type epitaxial layer on the N-type buried oxide layer; wherein the first N-well is located on the side of the first P-well away from the second P-well, and the first N-well and the first P-well are spaced apart from each other; the second N-well is located on the side of the second P-well away from the first P-well, and the second N-well and the second P-well are spaced apart from each other.

[0014] Preferably, in step one, the bottom of the first N-well and the second N-well are located on the upper surface of the N-type buried oxide layer, and the top of each is flush with the upper surface of the P-well epitaxial layer.

[0015] Preferably, in step one, a third STI region is provided between the first N-well and the first P-well; a fourth STI region is provided between the second P-well and the second N-well; the third and fourth STI regions are both located on top of the P-type epitaxial layer below the gate oxide layer.

[0016] Preferably, the P-type epitaxial layers on both sides of the N-type buried oxide layer in step one are further provided with a P-type buried oxide layer.

[0017] Preferably, the energy of boron injection in step four is 200–450 K; the injection dose of boron is 1E13–1E14 / cm2.

[0018] Preferably, the energy of arsenic injected in step four is 5-50K; the dose of arsenic injected is 1E14-1E15 / cm2.

[0019] Preferably, in step seven, P+ regions are also formed on the top of the first P-well between the first and third STI regions and on the top of the second P-well between the second and fourth STI regions.

[0020] As described above, the parasitic Zener diode fabrication method of the present invention has the following beneficial effects: The present invention uses the P-type body region in SNLDMOS to implant and form the N+ region and the P-type body region; or forms the N+ region, the P-type body region and the P-well for use by the Zener diode, without the need to add an additional photomask; simulation results show that the breakdown voltage BV is about 5.6 to 6.4V, and the actual BV can be adjusted in the device. Therefore, the present invention can realize the fabrication of Zener diodes under simple process conditions, which can simplify the process. Attached Figure Description

[0021] Figures 1 to 7 The diagram shows a cross-sectional view of each step in forming a Zener diode in this invention. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] This invention provides a method for fabricating a parasitic Zener diode, comprising at least:

[0025] Step 1: Provide a P-type epitaxial layer, wherein an N-type buried oxide layer is formed in the P-type epitaxial layer; a first P-well and a second P-well are formed in the P-type epitaxial layer above the N-type buried oxide layer, spaced apart from each other; a gate oxide layer is formed on the upper surface of the P-type epitaxial layer; a first STI region is formed on the side of the first P-well near the second P-well, and a second STI region is formed on the side of the second P-well near the first P-well, and connected to the second P-well.

[0026] like Figure 1As shown, step one provides a P-type epitaxial layer (P-EPI), in which an N-type buried oxide layer (NBL) is formed; a first P-well 01 and a second P-well 02 are formed on the P-type epitaxial layer (P-EPI) above the N-type buried oxide layer (NBL); a gate oxide layer (GOX) is formed on the upper surface of the P-type epitaxial layer (P-EPI); a first STI region 05 is formed on the side of the first P-well 01 near the second P-well 02, which is connected to the first P-well; a second STI region 06 is formed on the side of the second P-well 02 near the first P-well 01, which is connected to the second P-well 02.

[0027] Furthermore, in step one of this embodiment, the bottom of the first P-well 01 and the second P-well 02 are respectively located on the upper surface of the N-type buried oxide layer (NBL), and the top of each is flush with the upper surface of the P-type epitaxial layer (P-EPI).

[0028] like Figure 1 As shown, in a further embodiment of the present invention, a first N-well 03 and a second N-well 04 are formed in the P-type epitaxial layer (P-EPI) on the N-type buried oxide layer (NBL) in step one of this embodiment; wherein the first N-well 03 is located on the side of the first P-well 01 away from the second P-well 02, and the first N-well 03 and the first P-well 01 are spaced apart from each other; the second N-well 04 is located on the side of the second P-well 02 away from the first P-well 01, and the second N-well 04 and the second P-well 02 are spaced apart from each other.

[0029] Furthermore, in step one of this embodiment, the bottom of the first N-well 03 and the second N-well 04 are located on the upper surface of the N-type buried oxide layer (NBL), and the top of each is flush with the upper surface of the P-well epitaxial layer (P-EPI).

[0030] In a further embodiment of the present invention, in step one, a third STI region 07 is provided between the first N-well 03 and the first P-well 01; a fourth STI region 08 is provided between the second P-well 02 and the second N-well 04; the third and fourth STI regions are both located on top of the P-type epitaxial layer (P-EPI) below the gate oxide layer (GOX).

[0031] like Figure 1 As shown, in this embodiment, the P-type buried oxide layer (PBL) is further provided in the P-type epitaxial layer (P-EPI) on both sides of the N-type buried oxide layer (NBL) in step one of this embodiment.

[0032] Step 2: Deposit a polycrystalline silicon layer on the gate oxide layer; such as Figure 2As shown, step two involves depositing a polysilicon layer on the gate oxide layer (GOX).

[0033] Step 3: Etch the polysilicon layer to remove the polysilicon layer above the gate oxide layer and located between the first P-well and the second P-well; the remaining polysilicon layer forms the first polysilicon structure; as shown. Figure 3 As shown, in step three, the polysilicon layer is etched to remove the polysilicon layer above the gate oxide layer (GOX) and located between the first P-well 01 and the second P-well 02; the remaining polysilicon layer forms the first polysilicon structure 09.

[0034] Step 4: Spin-coat photoresist and photolithographically open the region on the first polysilicon structure located between the first and second STI regions; then, implant boron and arsenic into the P-type epitaxial layer between the first and second P-wells through the photolithographically opened region to form a P-type body region; as shown Figure 4 As shown, this step involves spin-coating photoresist (PR) and photolithographically opening the region on the first polysilicon structure located between the first STI region 05 and the second STI region 06; then, boron and arsenic are implanted into the P-type epitaxial layer between the first and second P-wells through the photolithographically opened region to form a P-type body region (p-body).

[0035] Furthermore, in step four of this embodiment, the energy of boron injection is 200–450 K; the dose of boron injection is 1E13–1E14 / cm2.

[0036] Furthermore, in step four of this embodiment, the energy of arsenic injection is 5-50K; the dose of arsenic injection is 1E14-1E15 / cm2.

[0037] Step 5: Using the remaining photoresist as a mask, etch away a portion of the first polysilicon structure in the area where the photolithography was opened. The portion of the remaining first polysilicon structure near the first STI region forms a second polysilicon structure; the portion of the remaining first polysilicon structure near the second STI region forms a third polysilicon structure; as shown. Figure 5 As shown, in step five, using the remaining photoresist (PR) as a mask, a portion of the first polysilicon structure in the area where the photolithography was opened is etched away. Figure 5 It can be seen that the first polysilicon structure is divided into two parts, wherein the part of the first polysilicon structure remaining near the first STI region 05 is formed as the second polysilicon structure 10; and the part of the first polysilicon structure remaining near the second STI region 06 is formed as the third polysilicon structure 11.

[0038] Step 6: Remove any remaining photoresist; such as Figure 6 As shown, step six removes the remaining photoresist, exposing the second and third polysilicon structures.

[0039] Step 7: Etch away the gate oxide layers located outside the second and third polysilicon structures; and form a first N+ region in the P-type body region between the second and third polysilicon structures; then perform annealing. Figure 7 As shown, step seven involves etching away the gate oxide layer located outside the second polysilicon structure 10 and the third polysilicon structure 11, respectively; as Figure 7 As shown, only the gate oxide layer located under the second polysilicon structure and the gate oxide layer located under the third polysilicon structure are retained. A first N+ region 12 is formed in the P-type body region between the second and third polysilicon structures; then annealing is performed.

[0040] Furthermore, in step seven of this embodiment, a P+ region (P+) is formed on the top of the first P-well between the first and third STI regions and on the top of the second P-well between the second and fourth STI regions, respectively.

[0041] In summary, this invention uses the P-type body region in SNLDMOS to implant and form the N+ and P-type body regions; or forms the N+ region, P-type body region, and P-well for use in Zener diodes, without requiring additional photomasks. Simulation results show a breakdown voltage BV of approximately 5.6–6.4V, and the actual BV can be adjusted within the device. Therefore, this invention enables the fabrication of Zener diodes under simple process conditions, simplifying the manufacturing process. Thus, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a parasitic Zener diode, characterized in that, At least including: Step 1: Provide a P-type epitaxial layer, wherein an N-type buried oxide layer is formed in the P-type epitaxial layer; a first P-well and a second P-well are formed in the P-type epitaxial layer above the N-type buried oxide layer, spaced apart from each other; a gate oxide layer is formed on the upper surface of the P-type epitaxial layer; a first STI region is formed on the side of the first P-well near the second P-well, and a second STI region is formed on the side of the second P-well near the first P-well, and connected to the second P-well. Step 2: Deposit a polycrystalline silicon layer on the gate oxide layer; Step 3: Etch the polysilicon layer to remove the polysilicon layer above the gate oxide layer and located between the first P-well and the second P-well; the remaining polysilicon layer forms the first polysilicon structure. Step 4: Spin-coat photoresist and photolithographically open the region on the first polysilicon structure located between the first and second STI regions; then implant boron and arsenic into the P-type epitaxial layer between the first and second P-wells through the photolithographically opened region to form a P-type body region; Step 5: Using the remaining photoresist as a mask, etch away a portion of the first polysilicon structure in the area where the photolithography was opened; the portion of the remaining first polysilicon structure near the first STI region is formed as a second polysilicon structure; the portion of the remaining first polysilicon structure near the second STI region is formed as a third polysilicon structure. Step 6: Remove any remaining photoresist; Step 7: Etch away the gate oxide layers located outside the second and third polysilicon structures respectively; and form a first N+ region in the P-type body region between the second and third polysilicon structures; then perform annealing.

2. The method for fabricating a parasitic Zener diode according to claim 1, characterized in that: In step one, the bottom of the first P-well and the second P-well are located on the upper surface of the N-type buried oxide layer, and the top of each is flush with the upper surface of the P-type epitaxial layer.

3. The method for fabricating a parasitic Zener diode according to claim 1, characterized in that: In step one, a first N-well and a second N-well are formed in the P-type epitaxial layer on the N-type buried oxide layer; wherein the first N-well is located on the side of the first P-well away from the second P-well, and the first N-well and the first P-well are spaced apart from each other; the second N-well is located on the side of the second P-well away from the first P-well, and the second N-well and the second P-well are spaced apart from each other.

4. The method for fabricating a parasitic Zener diode according to claim 3, characterized in that: In step one, the bottom of the first N-well and the second N-well are located on the upper surface of the N-type buried oxide layer, and the top of each is flush with the upper surface of the P-well epitaxial layer.

5. The method for fabricating a parasitic Zener diode according to claim 4, characterized in that: In step one, a third STI region is provided between the first N-well and the first P-well; a fourth STI region is provided between the second P-well and the second N-well; the third and fourth STI regions are both located on top of the P-type epitaxial layer below the gate oxide layer.

6. The method for fabricating a parasitic Zener diode according to claim 1, characterized in that: In step one, a P-type buried oxide layer is also provided in the P-type epitaxial layers on both sides of the N-type buried oxide layer.

7. The method for fabricating a parasitic Zener diode according to claim 1, characterized in that: In step four, the energy for injecting boron is 200–450 K; the dose of injected boron is 1E13–1E14 / cm2.

8. The method for fabricating a parasitic Zener diode according to claim 1, characterized in that: In step four, the energy for injecting arsenic is 5–50 K; the dosage of injected arsenic is 1E14–1E15 / cm2.

9. The method for fabricating a parasitic Zener diode according to claim 5, characterized in that: In step seven, P+ regions are also formed on the top of the first P-well between the first and third STI regions and on the top of the second P-well between the second and fourth STI regions.

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