A wide input range pre-regulated power supply circuit

Abstract

This invention discloses a wide input range pre-regulated power supply circuit, belonging to the field of integrated circuits, including NMOS transistors MN1 to MN3, diodes D1 to D2, resistors R1 to R6, capacitors C1 to C2, and Zener transistors ZN1 to ZN6. The circuit's pre-regulated voltage is achieved through a Zener reference source, and its voltage is approximately equal to the breakdown voltage of Zener diode ZN6. NMOS transistors MN1 to MN3 are connected in series to increase the circuit's maximum input voltage. Diodes D1 and D2 are connected in series with Zener diode ZN1 to generate the gate bias voltage of NMOS transistor MN3. Resistor R1 puts Zener diode ZN1 into a breakdown state, and capacitor C1 provides filtering for the gate voltage of NMOS transistor MN3. Resistors R2, R3, and R4 put Zener diode ZN2 into a breakdown state and generate the gate bias voltages of NMOS transistors MN1 and MN2. Zener diodes ZN3, ZN4, and ZN5 clamp the gate-source voltages of NMOS transistors MN1, MN2, and MN3 to approximately 5V, respectively, to prevent the NMOS devices from failing due to gate-source breakdown. Resistor R5 limits the current in the main pre-regulated voltage path of the Zener diodes. Resistor R6 provides a DC load for the pre-regulated voltage, and capacitor C2 filters the pre-regulated voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a wide input range pre-regulated power supply circuit. Background Technology

[0002] The pre-regulator circuit is located between the mains power supply and the circuit it powers, serving as the secondary power source. Faced with excessive noise interference and fluctuating mains power, the pre-regulator module provides a buffer, significantly reducing power supply fluctuations. This technology can significantly improve the circuit's power supply rejection ratio and enhance its performance.

[0003] Currently, a pre-regulator circuit based on a Zener reference source is commonly used, such as... Figure 1 The circuit includes PMOS transistors MP1-MP3; NMOS transistors MN1-MN6; diodes D1-D3; resistors R1-R5; and capacitor C1. In this circuit, NMOS transistors MN1 and MN2, along with resistor R5, form a startup circuit, removing the circuit from its "degenerate" bias point. Transistors MN3, MN4, MP1, MP2, and resistor R3 form a simple differential pair device, providing bias to Zener diode Z1, causing it to reverse-bias and break down at a breakdown voltage of approximately 5.6V. Transistors MN6 and MN5 then add or subtract a threshold voltage V, respectively. THN Therefore, the output pre-regulated voltage is also around 5.6V; resistors R1, R2, and R4 are configured with appropriate operating points to shut down the start-up circuit; diodes D1, D2, and D3 conduct in one direction to ensure that the external EN voltage will not affect the pre-regulated circuit.

[0004] This technology has the following drawbacks:

[0005] (1) The pre-regulated output and the main power supply VIN are isolated only by NMOS transistor MN5. Due to the limited drain-source resistance of device MN5, the ability to suppress noise interference from the main power supply is severely affected, and the power supply rejection ratio is not high.

[0006] (2) The maximum input voltage of this technology is limited by the maximum withstand voltage of NMOS and PMOS devices, so the maximum input voltage range is relatively limited. Summary of the Invention

[0007] The purpose of this invention is to provide a wide input range pre-regulated power supply circuit to solve the problems existing in the current pre-regulated technology.

[0008] To solve the above-mentioned technical problems, the present invention provides a wide input range pre-regulated power supply circuit, including NMOS transistors MN1 to MN3, diodes D1 to D2, resistors R1 to R6, capacitors C1 to C2, and Zener transistors ZN1 to ZN6;

[0009] The second terminal of resistor R1 is connected to the positive terminal of diode D1, the negative terminal of diode D1 is connected to the positive terminal of diode D2, and the negative terminal of diode D2 is connected to the negative terminal of Zener diode ZN1.

[0010] The second end of resistor R2 is connected to the first end of resistor R3, the second end of resistor R3 is connected to the first end of resistor R4, the second end of resistor R4 is connected to the negative terminal of Zener diode ZN2, and the positive terminal of Zener diode ZN2 is connected to both the positive terminal of diode D1 and the first end of capacitor C1.

[0011] The second terminal of resistor R5 is connected to the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 is simultaneously connected to the second terminal of resistor R2 and the negative terminal of Zener transistor ZN3. The source of NMOS transistor MN1 is simultaneously connected to the positive terminal of Zener transistor ZN3 and the drain of NMOS transistor MN2. The gate of NMOS transistor MN2 is simultaneously connected to the second terminal of resistor R3 and the negative terminal of Zener transistor ZN4. The source of NMOS transistor MN2 is simultaneously connected to the positive terminal of Zener transistor ZN4 and the drain of NMOS transistor MN3. The gate of NMOS transistor MN3 is simultaneously connected to the first terminal of capacitor C1 and the negative terminal of Zener transistor ZN5. The source of NMOS transistor MN3 is simultaneously connected to the positive terminal of Zener transistor ZN5 and the negative terminal of Zener transistor ZN6.

[0012] The first terminal of resistor R6 and the first terminal of capacitor C2 are both connected to the source of NMOS transistor MN3; the source of NMOS transistor MN3 outputs a pre-regulated voltage VZENER.

[0013] In one embodiment, the first terminals of resistor R1, resistor R2, and resistor R5 are all connected to the input voltage VIN.

[0014] In one embodiment, the positive terminal of the Zener diode ZN1, the second terminal of the capacitor C1, the positive terminal of the Zener diode ZN6, the second terminal of the resistor R6, and the second terminal of the capacitor C2 are all grounded.

[0015] In one embodiment, the NMOS transistors MN1 to MN3 are all thin-gate oxide transistors.

[0016] The wide input range pre-regulated power supply circuit provided by this invention has the following beneficial effects:

[0017] (1) The Zener diode is used as the pre-regulated power supply, and the linear regulation is good;

[0018] (2) The input voltage range can be flexibly adjusted and improved by changing the number of NMOS series, which enhances the applicability of this technology;

[0019] (3) The NMOS series structure can significantly improve the power supply rejection ratio of the circuit and improve the output accuracy of the pre-regulated power supply. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an existing pre-regulator circuit based on a Zener reference source.

[0021] Figure 2 This is a schematic diagram of a wide input range pre-regulated power supply circuit provided by the present invention.

[0022] Figure 3 This is a schematic diagram illustrating the technical principle of increasing the number of NMOS devices connected in series to improve the input voltage. Detailed Implementation

[0023] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the wide input range pre-regulated power supply circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0024] This invention provides a wide input range pre-regulated power supply circuit, the principle of which is as follows: Figure 2 As shown, the circuit includes the following components: thin gate oxide NMOS transistors MN1-MN3, diodes D1-D2, resistors R1-R6, capacitors C1-C2, and Zener transistors ZN1-ZN6.

[0025] Resistor R1 has its first terminal connected to the input voltage VIN, and its second terminal connected to the anode of diode D1. The cathode of diode D1 is connected to the anode of diode D2, and the cathode of diode D2 is connected to the cathode of Zener diode ZN1. The anode of Zener diode ZN1 is grounded. Resistor R2 has its first terminal connected to the input voltage VIN, and its second terminal connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the first terminal of resistor R4, and the second terminal of resistor R4 is connected to the cathode of Zener diode ZN2. The anode of Zener diode ZN2 is connected to both the anode of diode D1 and the first terminal of capacitor C1. The second terminal of capacitor C1 is grounded. Resistor R5 has its first terminal connected to the input voltage VIN and its second terminal connected to the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 is simultaneously connected to the second terminal of resistor R2 and the negative terminal of Zener transistor ZN3. The source of NMOS transistor MN1 is simultaneously connected to the positive terminal of Zener transistor ZN3 and the drain of NMOS transistor MN2. The gate of NMOS transistor MN2 is simultaneously connected to the second terminal of resistor R3 and the negative terminal of Zener transistor ZN4. The source of NMOS transistor MN2 is simultaneously connected to the positive terminal of Zener transistor ZN4 and the drain of NMOS transistor MN3. The gate of NMOS transistor MN3 is simultaneously connected to the first terminal of capacitor C1 and the negative terminal of Zener transistor ZN5. The source of NMOS transistor MN3 is simultaneously connected to the positive terminal of Zener transistor ZN5 and the negative terminal of Zener transistor ZN6. The positive terminal of Zener transistor ZN6 is grounded. Resistor R6 has its first terminal connected to the source of NMOS transistor MN3 and its second terminal grounded. Capacitor C2 has its first terminal connected to the source of NMOS transistor MN3 and its second terminal grounded. The source output pre-regulated voltage VZENER of NMOS transistor MN3.

[0026] The circuit's pre-regulated voltage is achieved through a Zener reference source, approximately equal to the breakdown voltage of Zener transistor ZN6, with a value between 5V and 6V. NMOS transistors MN1-MN3 are connected in series to increase the circuit's maximum input voltage. Diodes D1 and D2 are connected in series with Zener transistor ZN1 to generate the bias voltage for the gate of NMOS transistor MN3. Resistor R1 biases Zener transistor ZN1, causing it to enter a breakdown state. Capacitor C1 provides filtering for the gate voltage of NMOS transistor MN3. Resistors R2, R3, and R4 are connected to Zener transistor ZN2... The Zener diode ZN2 is connected in series to be in a breakdown state and used to generate the gate bias voltage of NMOS transistors MN1 and MN2; Zener diodes ZN3, ZN4, and ZN5 are used to clamp the gate-source voltage of NMOS transistors MN1, MN2, and MN3 to about 5V respectively to prevent the gate-source of NMOS devices from failing due to breakdown; resistor R5 is used to limit the current in the main path of the Zener diode pre-regulation to prevent the circuit from failing due to input surge current; resistor R6 provides a DC load for the pre-regulated voltage; and capacitor C2 is used to filter the pre-regulated voltage to improve the power supply rejection ratio.

[0027] This invention employs a Zener transistor biased in a breakdown state as the pre-regulated power supply, whose value is minimally affected by input voltage variations, exhibiting excellent linear regulation performance. Furthermore, the series connection of NMOS transistors increases the impedance between the input voltage VIN and the pre-regulated voltage VZENER, significantly improving the circuit's power supply rejection ratio. Simultaneously, this invention expands the input range of the pre-regulated circuit by connecting NMOS transistors MN1 to MN3 in series. The number of NMOS transistors connected in series can be flexibly adjusted to meet different input voltage requirements, as shown in the circuit structure below. Figure 3 As shown. Figure 3 Compared to Figure 2 Two NMOS transistors, MN4 and MN5, and gate-source voltage clamping Zener transistors, ZN7 and ZN8, are added in series. Resistors R7 and R8 are used to set the gate bias voltage of MN4 and MN5. Figure 3 Compared to Figure 2 The maximum input voltage can be significantly increased.

[0028] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A wide input range pre-regulator power supply circuit, characterized by, The NMOS tubes MN1-MN3, diodes D1-D2, resistors R1-R6, capacitors C1-C2, and Zener tubes ZN1-ZN6 are included. The second end of the resistor R1 is connected to the positive pole of the diode D1, the negative pole of the diode D1 is connected to the positive pole of the diode D2, and the negative pole of the diode D2 is connected to the negative pole of the Zener tube ZN1. The second end of the resistor R2 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the first end of the resistor R4, the second end of the resistor R4 is connected to the negative pole of the Zener tube ZN2, and the positive pole of the Zener tube ZN2 is connected to the positive pole of the diode D1 and the first end of the capacitor C1. The second end of the resistor R5 is connected to the drain of the NMOS tube MN1, the gate of the NMOS tube MN1 is connected to the second end of the resistor R2 and the negative pole of the Zener tube ZN3, the source of the NMOS tube MN1 is connected to the positive pole of the Zener tube ZN3 and the drain of the NMOS tube MN2, the gate of the NMOS tube MN2 is connected to the second end of the resistor R3 and the negative pole of the Zener tube ZN4, the source of the NMOS tube MN2 is connected to the positive pole of the Zener tube ZN4 and the drain of the NMOS tube MN3, and the gate of the NMOS tube MN3 is connected to the first end of the capacitor C1 and the negative pole of the Zener tube ZN5, the source of the NMOS tube MN3 is connected to the positive pole of the Zener tube ZN5 and the negative pole of the Zener tube ZN6. The first end of the resistor R6 and the first end of the capacitor C2 are both connected to the source of the NMOS tube MN3, and the source of the NMOS tube MN3 outputs a pre-stabilized voltage VZENER.

2. The wide input range pre-regulator power supply circuit of claim 1, wherein, The first end of the resistor R1, the first end of the resistor R2, and the first end of the resistor R5 are all connected to an input voltage VIN.

3. The wide input range pre-regulator power supply circuit of claim 1, wherein, The positive pole of the Zener tube ZN1, the second end of the capacitor C1, the positive pole of the Zener tube ZN6, the second end of the resistor R6, and the second end of the capacitor C2 are all connected to ground.

4. The wide input range pre-regulator power supply circuit of claim 1, wherein, The NMOS tubes MN1-MN3 are all thin-gate oxide tubes.

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