semiconductor devices

Abstract

The present invention provides a semiconductor device having improved frequency responsiveness related to the control of input capacitance and feedback capacitance. The semiconductor device includes a capacitance adjustment region. The capacitance adjustment region includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of control trench gates. The first semiconductor layer is provided as a surface layer on the upper surface of a semiconductor substrate. The second semiconductor layer is selectively provided on the upper surface side of the first semiconductor layer. The second semiconductor layer contacts the side surfaces of the plurality of control trench gates. The first semiconductor layer and the second semiconductor layer are electrically connected to the emitter electrode of the transistor. The control trench electrode of at least one control trench gate is electrically connected to the gate electrode of the transistor.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In the case of an IGBT (Insulated Gate Bipolar Transistor) driven by a gate having a trench MOS (Metal Oxide Semiconductor) structure, input capacitance and feedback capacitance are formed in the trench gate during driving. The input capacitance corresponds to the gate-emitter capacitance (C ge ) and the gate-collector capacitance (C gc ) and (C ge +C gc ), the feedback capacitance corresponds to the gate-collector capacitance (C gc In order to reduce the switching loss of the IGBT, the ratio between the input capacitance and the feedback capacitance is adjusted according to its application.

[0003] Patent Document 1 proposes a power semiconductor device in which a trench, a conductor, and an insulating film are arranged in a p-type semiconductor layer. In such a power semiconductor device, the built-in electrostatic capacitance between the gate and the emitter increases.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2013-201266

[0005] In the structure described in Patent Document 1, the added built-in capacitance has poor frequency responsiveness, and the generation of the built-in capacitance cannot follow the switching speed of the IGBT. Summary of the Invention

[0006] In order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor device having improved frequency responsiveness of input capacitance and feedback capacitance.

[0007] The semiconductor device according to the present invention comprises a semiconductor substrate, a transistor region, and a capacitance adjustment region. The transistor region is provided on the semiconductor substrate and includes a transistor. The capacitance adjustment region is provided on the semiconductor substrate. The capacitance adjustment region includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of control trench gates. The first semiconductor layer is provided as a surface layer on the upper surface of the semiconductor substrate. The second semiconductor layer is selectively provided on the upper surface side of the first semiconductor layer as a surface layer of the semiconductor substrate. The plurality of control trench gates each include a control trench insulating film and a control trench electrode. The control trench insulating film is formed on the inner wall of a trench that penetrates the second semiconductor layer from the upper surface of the semiconductor substrate and has a front end within the first semiconductor layer. The control trench electrode is formed within the trench through the control trench insulating film. The second semiconductor layer contacts the side surfaces of the plurality of control trench gates. The first semiconductor layer and the second semiconductor layer are electrically connected to the emitter electrode of the transistor. The control trench electrode of at least one of the plurality of control trench gates is electrically connected to the gate electrode of the transistor.

[0008] Effects of the Invention

[0009] According to the present invention, a semiconductor device having improved frequency responsiveness of input capacitance and feedback capacitance is provided.

[0010] The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0013] Figure 3 This is a partially enlarged plan view showing the structure of the IGBT region of the semiconductor device according to the first embodiment.

[0014] Figure 4 This is a cross-sectional view showing the structure of the IGBT region of the semiconductor device according to the first embodiment.

[0015] Figure 5 This is a cross-sectional view showing the structure of the IGBT region of the semiconductor device according to the first embodiment.

[0016] Figure 6 This is a partially enlarged plan view showing the structure of the diode region of the semiconductor device according to the first embodiment.

[0017] Figure 7This is a cross-sectional view showing the structure of the diode region of the semiconductor device according to the first embodiment.

[0018] Figure 8 This is a cross-sectional view showing the structure of the diode region of the semiconductor device according to the first embodiment.

[0019] Figure 9 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region and the diode region.

[0020] Figure 10 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region and the termination region.

[0021] Figure 11 It is a cross-sectional view showing the structure of the boundary portion between the diode region and the termination region.

[0022] Figure 12 This is a plan view showing the structure of a capacitance adjustment region of the semiconductor device according to the first embodiment.

[0023] Figure 13 This is a cross-sectional view showing the structure of a capacitance adjustment region of the semiconductor device according to the first embodiment.

[0024] Figure 14 This is a plan view showing the structure of a capacitance adjustment region according to a fourth modification of the first embodiment.

[0025] Figure 15 This is a plan view showing the structure of a capacitance adjustment region according to a fifth modification of the first embodiment.

[0026] Figure 16 This is a plan view showing the structure of the capacitance adjustment region according to the second embodiment.

[0027] Figure 17 This is a diagram showing the relationship between the voltage applied to the control trench electrode and the additional capacitance.

[0028] Figure 18 This is a plan view showing the structure of a capacitance adjustment region according to a first modification of the second embodiment.

[0029] Figure 19 This is a plan view showing the structure of a capacitance adjustment region according to a second modification of the second embodiment.

[0030] Figure 20 It is a plan view showing the structure of the capacitance adjustment region according to the third embodiment.

[0031] Figure 21 This is a cross-sectional view showing the structure of a capacitance adjustment region according to the third embodiment.

[0032] Figure 22It is a plan view showing the structure of the capacitance adjustment region according to the first modification of the third embodiment.

[0033] Figure 23 This is a plan view showing the structure of a capacitance adjustment region according to a second modification of the third embodiment.

[0034] Figure 24 This is a plan view showing the structure of a capacitance adjustment region according to a third modification of the third embodiment. DETAILED DESCRIPTION

[0035] <Implementation Method 1>

[0036] In the following description, n and p represent the conductivity type of the semiconductor. - It shows that the impurity concentration is lower than n. + shows that the impurity concentration is higher than n. Similarly, p - It shows that the impurity concentration is lower than p. + The impurity concentration is higher than that of p. The p-type and n-type layers shown below may be interchanged.

[0037] (1) Overall planar structure of semiconductor device

[0038] Figure 1 This is a top view showing an example of the structure of the semiconductor device 100 of embodiment 1. The semiconductor device 100 has an IGBT (Insulated Gate Bipolar Transistor) region 10 and a diode region 20 in one semiconductor substrate. The diode region 20 is adjacent to the IGBT region 10. A unit structure of multiple IGBTs (IGBT cells) is formed in the IGBT region 10, and a unit structure of multiple freewheeling diodes (diode cells) is formed in the diode region 20. The unit structure is a structure corresponding to the smallest unit of an element. The region including the IGBT region 10 and the diode region 20 is called a unit region. The semiconductor device 100 of embodiment 1 is an RC-IGBT (Reverse Conducting IGBT). The semiconductor substrate is formed of a semiconductor such as Si, or a so-called wide bandgap semiconductor such as SiC, GaN, or gallium oxide.

[0039] The IGBT region 10 and the diode region 20 have a stripe-like planar shape. The IGBT region 10 and the diode region 20 extend in one direction within the plane of the semiconductor substrate. The IGBT region 10 and the diode region 20 are arranged alternately in a direction perpendicular to their extending direction. This type of semiconductor device 100 is referred to as a "stripe-type" device.

[0040] Figure 21 is a plan view showing an example of the structure of a semiconductor device 101 according to Embodiment 1. Similar to the semiconductor device 100 , the semiconductor device 101 is an RC-IGBT including an IGBT region 10 and a diode region 20 within a single semiconductor substrate.

[0041] The diode region 20 has an island-like planar shape. Here, multiple diode regions 20 are arranged in the vertical and horizontal directions within the plane of the semiconductor substrate. The IGBT region 10 surrounds each of the multiple diode regions 20. Such a semiconductor device 101 is called an "island type."

[0042] The semiconductor devices 100 and 101 include, in addition to the IGBT region 10 and the diode region 20 , a termination region 30 , a pad region 40 , and a capacitance adjustment region 50 .

[0043] The pad region 40 is provided outside the cell region, that is, outside the IGBT region 10 and the diode region 20. Here, the pad region 40 is provided adjacent to the IGBT region 10. The pad region 40 is an area where control pads 41 for controlling the semiconductor device are provided. In other words, the control pads 41 are signal pads used to detect or control the state of the semiconductor substrate. For example, the control pads 41 include a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sensing diode pads 41d and 41e.

[0044] The current sensing pad 41a is a control pad for detecting the current flowing through the cell region and is electrically connected to the IGBT cells or diode cells in part of the cell region so that a current of a fraction to tens of thousands of the current flowing through the entire cell region flows through the pad.

[0045] The Kelvin emitter pad 41b and the gate pad 41c are control pads for applying a gate drive voltage for on / off control of the semiconductor device. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via p + The gate pad 41c is electrically connected to a gate trench electrode (not shown) of the IGBT cell.

[0046] Temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region. Temperature sensing diode pads 41d and 41e measure the voltage between the anode and cathode of the temperature sensing diode to measure the temperature of the semiconductor device.

[0047] The capacitance adjustment region 50 has the function of forming an additional capacitance between the gate and emitter or between the gate and collector of the IGBT. Figure 1 and Figure 2 , the capacitance adjustment region 50 is arranged in the pad region 40. The capacitance adjustment region 50 only needs to be within the region surrounded by the terminal region 30, and may be arranged in other regions such as the end portion of the IGBT region 10.

[0048] The terminal region 30 is configured to surround the combined area of ​​the cell region and the pad region 40. The terminal region 30 has a structure for maintaining the voltage resistance of the semiconductor device. Various structures can be appropriately selected for the voltage resistance maintenance structure. The voltage resistance maintenance structure is, for example, an FLR (Field Limiting Ring) or a VLD (Variation of Lateral Doping) formed on the surface layer of the first main surface side (upper surface side) of the semiconductor substrate. The FLR has a p-type terminal well layer (not shown) arranged in a manner surrounding the cell region. The VLD is configured to surround the cell region and has a p-type well layer (not shown) having a concentration gradient. The number of annular p-type terminal well layers 31 constituting the FLR and the concentration distribution of the p-type well layer constituting the VLD are appropriately selected according to the voltage resistance design of the semiconductor device. In addition, a p-type terminal well layer can be provided over almost the entire area of ​​the pad region 40. Alternatively, an IGBT cell or a diode cell can be provided in the pad region 40.

[0049] exist Figure 1 , three IGBT regions 10 and two diode regions 20 are shown. However, the number of IGBT regions 10 and diode regions 20 is not limited thereto. The number of IGBT regions 10 may be greater than or equal to four, or less than or equal to two. The number of diode regions 20 may be greater than or equal to three, or one. Figure 1 The diode region 20 shown in FIG. 1 is sandwiched between two IGBT regions 10. However, the arrangement of the IGBT region 10 and the diode region 20 is not limited to this. The semiconductor device 100 may also have Figure 1 The illustrated structure is a structure in which the arrangement of the IGBT region 10 and the diode region 20 is reversed. That is, one IGBT region 10 may be sandwiched between two diode regions 20. Alternatively, the same number of IGBT regions 10 and diode regions 20 may be disposed adjacent to each other.

[0050] exist Figure 2In the embodiment, a plurality of diode regions 20 are arranged in a matrix, with four columns in the horizontal direction and two rows in the vertical direction. However, the number and arrangement of the diode regions 20 are not limited to this. The semiconductor device 101 may also have a structure in which at least one diode region 20 is interspersed within the IGBT region 10. The diode regions 20 may be arranged in any manner as long as they are surrounded by the IGBT region 10.

[0051] (2) Structure of IGBT Region 10

[0052] Figure 3 This is a partially enlarged plan view showing the structure of the IGBT region 10 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 3 Will Figure 1 The semiconductor device 100 or Figure 2 Region 82 of semiconductor device 101 is shown enlarged.

[0053] The semiconductor devices 100 and 101 include an active trench gate 11 and a dummy trench gate 12 provided in the IGBT region 10 .

[0054] In the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 extend along the length direction of the IGBT region 10. In other words, the length direction of the active trench gate 11 and the dummy trench gate 12 of the semiconductor device 100 is located in the extension direction of the IGBT region 10. The length direction of the IGBT region 10 corresponds to Figure 3 left and right directions.

[0055] In the semiconductor device 101, the active trench gate 11 and the dummy trench gate 12 extend in one direction. For example, the active trench gate 11 and the dummy trench gate 12 extend in one direction. Figure 2 Extending in any direction of the up and down directions and the left and right directions.

[0056] The active trench gate 11 includes a gate trench insulating film 11b and a gate trench electrode 11a. The cross-sectional structure of the active trench gate 11 will be described in detail later. The gate trench insulating film 11b is formed along the inner wall of a trench formed in the depth direction from the first main surface (top surface) of the semiconductor substrate. The gate trench electrode 11a is formed within the trench through the gate trench insulating film 11b. The gate trench electrode 11a is electrically connected to the gate pad 41c (not shown).

[0057] The dummy trench gate 12 includes a dummy trench insulating film 12b and a dummy trench electrode 12a. The cross-sectional structure of the dummy trench gate 12 will be described in detail later, but the dummy trench insulating film 12b is formed along the inner wall of the trench formed in the depth direction from the first main surface of the semiconductor substrate. The dummy trench electrode 12a is formed inside the trench through the dummy trench insulating film 12b. The dummy trench electrode 12a is connected to the emitter electrode 6 (on the first main surface of the semiconductor device 100 or the semiconductor device 101) provided above the first main surface. Figure 3 Not shown in the figure, refer to Figure 4 ) electrical connection.

[0058] In the region where the active trench gate 11 is provided in the IGBT region 10, n is selectively provided as a surface layer on the first main surface side of the semiconductor substrate. + Type source layer 13 and p + Type contact layer 14. In embodiment 1, n + Type source layer 13 and p + The n type contact layers 14 are alternately arranged along the extending direction (length direction) of the active trench gate 11. The active trench gate 11 is arranged to cross the above n type contact layers 14. + Type source layer 13 and p + On both sides of the active trench gate 11 (in the direction perpendicular to the extension direction), n + The type source layer 13 is in contact with the gate trench insulating film 11b. + Type source layer 13 and p + The details of the type contact layer 14 will be described later.

[0059] In the region where the dummy trench gate 12 is provided in the IGBT region 10, a p-type semiconductor substrate is provided as a surface layer on the first main surface side. + Type contact layer 14. p + The type contact layer 14 is disposed between two adjacent dummy trench gates 12 .

[0060] exist Figure 3 In the embodiment, three dummy trench gates 12 are arranged next to the three active trench gates 11. Furthermore, three more active trench gates 11 are arranged next to the three dummy trench gates 12 (in the embodiment of FIG. Figure 3, the bottom one of the three active trench gates 11 is omitted). That is, the active trench gate group consisting of three active trench gates 11 and the dummy trench gate group consisting of three dummy trench gates 12 are alternately arranged. The number of active trench gates 11 included in one active trench gate group is not limited to three, as long as it is greater than or equal to one. In addition, the number of dummy trench gates 12 included in one dummy trench gate group is not limited to three, as long as it is greater than or equal to one. However, in the semiconductor device 100 and the semiconductor device 101, the dummy trench gate 12 is not required. That is, all the trench gates provided in the IGBT region 10 may be active trench gates 11.

[0061] Figure 4 1 is a cross-sectional view showing the structure of the IGBT region 10 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 4 Show Figure 3 The cross section is shown along line segment AA.

[0062] The semiconductor device 100 and the semiconductor device 101 include n in the IGBT region 10 + Type source layer 13, p + type contact layer 14, p-type base layer 15, n-type carrier storage layer 2, n - type drift layer 1, n-type buffer layer 3, p-type collector layer 16, active trench gate 11, dummy trench gate 12, interlayer insulating film 4, barrier metal 5, emitter electrode 6 and collector electrode 7.

[0063] One IGBT cell corresponds to, for example, a region divided by the active trench gate 11. The IGBT cell includes n + type source layer 13, p-type base layer 15, n-type carrier storage layer 2, n - type drift layer 1 , n-type buffer layer 3 , p-type collector layer 16 , active trench gate 11 , interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 and collector electrode 7 .

[0064] The first main surface of the semiconductor substrate of the IGBT region 10 corresponds to n + Type source layer 13 and p + The surface (upper surface) of the p-type contact layer 14. The second main surface of the semiconductor substrate of the IGBT region 10 corresponds to the surface (lower surface) of the p-type collector layer 16. The first main surface is the upper surface of the semiconductor substrate. The second main surface is the surface on the opposite side of the first main surface and is the lower surface of the semiconductor substrate. In other words, Figure 4 The semiconductor substrate corresponds to the + Type source layer 13 and p +The range from the upper surface of the p-type contact layer 14 to the lower surface of the p-type collector layer 16. The first principal surface side and the second principal surface side correspond to the so-called front side and back side, respectively.

[0065] n - The type drift layer 1 is formed as an inner layer of the semiconductor substrate. - The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity. The concentration of the n-type impurity is preferably greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+15 / cm 3 .n - The type drift layer 1 is derived from, for example, the structure of the substrate before each structure is formed on the first main surface side and the second main surface side of the semiconductor substrate.

[0066] The n-type carrier storage layer 2 has a - The n-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. The n-type carrier storage layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. - The concentration of n-type impurities is higher than that of n-type drift layer 1. The concentration of n-type impurities is preferably greater than or equal to 1.0E+13 / cm 3 and less than or equal to 1.0E+17 / cm 3 The n-type carrier accumulation layer 2 reduces conduction loss when current flows through the IGBT region 10 .

[0067] The p-type base layer 15 is provided on the first main surface side of the semiconductor substrate relative to the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11 b of the active trench gate 11 . When a gate driving voltage is applied to the gate trench electrode 11 a , a channel is formed in the p-type base layer 15 .

[0068] n + The n-type source layer 13 is provided on the first main surface side of the semiconductor substrate relative to the p-type base layer 15. + The p-type source layer 13 is selectively provided on the upper surface side of the p-type base layer 15 as a surface layer of the semiconductor substrate. + The surface (upper surface) of the type source layer 13 constitutes the first main surface of the semiconductor substrate of the IGBT region 10. + The n-type source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is preferably greater than or equal to 1.0E+17 / cm3 and less than or equal to 1.0E+20 / cm 3 In addition, n + The type source layer 13 is sometimes referred to as n + type emitter layer.

[0069] p + The p-type contact layer 14 is provided on the first main surface side of the semiconductor substrate relative to the p-type base layer 15. + The p-type contact layer 14 is selectively provided on the upper surface side of the p-type base layer 15 as a surface layer of the semiconductor substrate. + The p-type contact layer 14 is provided on the upper surface side of the p-type base layer 15 where the n-type contact layer 14 is not provided. + The region of the type source layer 13. + The surface (upper surface) of the p-type contact layer 14 constitutes the first main surface of the semiconductor substrate of the IGBT region 10. + The p-type contact layer 14 is a semiconductor layer containing boron, aluminum, or the like as a p-type impurity. + The concentration of the p-type impurity in the p-type contact layer 14 is higher than that in the p-type base layer 15. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+15 / cm 3 and less than or equal to 1.0E+20 / cm 3 .

[0070] The n-type buffer layer 3 is relatively - The n-type drift layer 1 is provided on the second main surface side of the semiconductor substrate. The n-type buffer layer 3 is, for example, phosphorus or protons (H + ) etc. as the semiconductor layer of n-type impurities. - The concentration of n-type impurities is higher than that of n-type drift layer 1. The concentration of n-type impurities is preferably greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+18 / cm 3 When the semiconductor device 100 is in the off state, the n-type buffer layer 3 reduces the occurrence of punch-through due to the extension of the depletion layer from the p-type base layer 15 toward the second main surface.

[0071] The p-type collector layer 16 is provided on the second main surface side of the semiconductor substrate relative to the n-type buffer layer 3. The surface (lower surface) of the p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+16 / cm 3 and less than or equal to 1.0E+20 / cm 3 .

[0072] The active trench gate 11 extends from the first main surface of the semiconductor substrate to the n +The p-type source layer 13, the p-type base layer 15 and the n-type carrier storage layer 2 penetrate to reach the n-type carrier storage layer 2. - Type drift layer 1.

[0073] The gate trench insulating film 11b is formed along the inner wall of the trench formed in the depth direction from the first main surface of the semiconductor substrate. + The p-type source layer 13 is in contact with the p-type base layer 15. The gate trench insulating film 11b is, for example, an oxide film.

[0074] The gate trench electrode 11a is formed inside the trench via the gate trench insulating film 11b. The bottom of the gate trench electrode 11a is connected to the n-type gate trench insulating film 11b via the gate trench insulating film 11b. - The gate trench electrode 11a is formed of, for example, conductive polysilicon. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b.

[0075] The dummy trench gate 12 extends the p + The p-type contact layer 14, the p-type base layer 15 and the n-type carrier storage layer 2 penetrate to reach the n-type - Type drift layer 1.

[0076] The dummy trench insulating film 12b is formed along the inner wall of the trench formed in the depth direction from the first main surface of the semiconductor substrate. The dummy trench insulating film 12b is, for example, an oxide film.

[0077] The dummy trench electrode 12a is formed inside the trench via the dummy trench insulating film 12b. - The dummy trench insulating film 12b on at least one side of the dummy trench insulating film 12b on both sides of the dummy trench electrode 12a is not in contact with the n type drift layer 1. + The dummy trench electrode 12a is in contact with the source layer 13. The dummy trench electrode 12a is formed of, for example, conductive polysilicon.

[0078] The interlayer insulating film 4 is provided on the gate trench electrode 11 a of the active trench gate 11 .

[0079] The barrier metal 5 is formed on the first main surface of the semiconductor substrate in the region where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 is formed of a metal containing titanium, such as Ti, TiN, or TiSi. Conductors containing titanium are, for example, titanium nitride and TiSi. TiSi is an alloy of titanium and silicon (Si). The barrier metal 5 and n + Type source layer 13, p + The barrier metal 5 and the n-type contact layer 14 and the dummy trench electrode 12a are in ohmic contact.+ Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are electrically connected.

[0080] The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 is preferably formed of, for example, an aluminum alloy (Al-Si alloy) containing aluminum and silicon. + Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are electrically connected.

[0081] The collector electrode 7 is provided on the p-type collector layer 16 . The collector electrode 7 is preferably formed of an aluminum alloy, similarly to the emitter electrode 6 . The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16 .

[0082] Figure 5 1 is a cross-sectional view showing the structure of the IGBT region 10 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 5 Show Figure 3 The cross section at line segment BB is shown.

[0083] Figure 5 The cross section shown is Figure 4 The difference between the shown sections is that no n + The type source layer 13 is formed as a surface layer on the first main surface side of the semiconductor substrate. Figure 3 As shown, n + The p-type source layer 13 is selectively provided on the upper surface side of the p-type base layer 15 .

[0084] The structure of the IGBT region 10 has been described above, but the structure of the IGBT region 10 is not limited to the above structure. + The p-type contact layer 14 and the p-type base layer 15 may be combined and defined as one p-type base layer.

[0085] The n-type carrier storage layer 2 and n - The n-type drift layer 1 can also be combined to form an n-type drift layer. The n-type carrier accumulation layer 2 is not essential, and an n-type carrier accumulation layer can also be provided in the place of the n-type carrier accumulation layer 2. - Type drift layer 1.

[0086] The n-type buffer layer 3 and n - The n-type drift layer 1 can also be combined to form an n-type drift layer. - The n-type drift layer 1 can also be combined to form an n-type drift layer. In addition, the n-type buffer layer 3 is not necessary, and an n-type buffer layer 3 can also be provided at the position of the n-type buffer layer 3. - Type drift layer 1.

[0087] The barrier metal 5 is not necessary. In the case where the barrier metal 5 is not provided, the emitter electrode 6 is provided at n + On the p-type source layer 13, + The barrier metal 5 may be provided only on the n-type contact layer 14 and on the dummy trench electrode 12a, and in ohmic contact with them. + The emitter electrode 6 is formed on an n-type semiconductor layer such as an n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be combined to form a single emitter electrode. An interlayer insulating film 4 may also be provided on a portion of the dummy trench electrode 12a. In this case, the emitter electrode 6 is electrically connected to the dummy trench electrode 12a at a certain region above the dummy trench electrode 12a.

[0088] The emitter electrode 6 may also be composed of multiple metal films, each of which may be composed of an aluminum alloy film or other metal films. For example, the emitter electrode 6 may be composed of an aluminum alloy film and a plated film. The plated film is formed, for example, by chemical plating or electrolytic plating. The plated film is, for example, a nickel (Ni) film. A tungsten film may also be formed in a small area, such as between adjacent interlayer insulating films 4. The emitter electrode 6 is formed by covering the tungsten film. Tungsten films have better filling properties than plated films, thus forming a good emitter electrode 6.

[0089] The collector electrode 7 may be made of an aluminum alloy and a plating film. The collector electrode 7 may have a structure different from that of the emitter electrode 6 .

[0090] (3) Structure of the diode region 20

[0091] Figure 6 This is a partially enlarged plan view showing the structure of the diode region 20 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 6 Will Figure 1 The semiconductor device 100 or Figure 2 Region 83 of semiconductor device 101 is shown enlarged.

[0092] The semiconductor device 100 and the semiconductor device 101 include a diode trench gate 21 provided in the diode region 20 .

[0093] The diode trench gate 21 extends in one direction. The diode trench gate 21 of the first embodiment extends in the same direction as the active trench gate 11 and the dummy trench gate 12 .

[0094] The diode trench gate 21 includes a diode trench insulating film 21b and a diode trench electrode 21a. The cross-sectional structure of the diode trench gate 21 will be described in detail later. The diode trench insulating film 21b is formed along the inner wall of a trench formed in the depth direction from the first main surface of the semiconductor substrate. The diode trench electrode 21a is formed within the trench via the diode trench insulating film 21b.

[0095] In the diode region 20, p is selectively provided as a surface layer on the first main surface side of the semiconductor substrate. + type contact layer 24 and p-type anode layer 25. In embodiment 1, p + The p-type contact layer 24 and the p-type anode layer 25 are alternately provided along the extending direction (length direction) of the diode trench gate 21. The diode trench gate 21 is formed to cross the p-type contact layer 24 and the p-type anode layer 25. + The p-type contact layer 24 and the p-type anode layer 25 are provided. + The p-type contact layer 24 and the p-type anode layer 25 are provided between two adjacent diode trench gates 21. + The details of the p-type contact layer 24 and the p-type anode layer 25 will be described later.

[0096] Figure 7 1 is a cross-sectional view showing the structure of the diode region 20 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 7 Show Figure 6 The cross section at line CC is shown.

[0097] The semiconductor device 100 and the semiconductor device 101 include a p-type diode in the diode region 20. + type contact layer 24, p-type anode layer 25, n-type carrier storage layer 2, n - Type drift layer 1, n-type buffer layer 3, n + type cathode layer 26, diode trench gate 21, barrier metal 5, emitter electrode 6 and collector electrode 7.

[0098] One diode cell corresponds to, for example, a region divided by the diode trench gate 21. The diode cell includes p + type contact layer 24, p-type anode layer 25, n-type carrier storage layer 2, n - Type drift layer 1, n-type buffer layer 3, n + type cathode layer 26, diode trench gate 21, barrier metal 5, emitter electrode 6 and collector electrode 7.

[0099] The first main surface of the semiconductor substrate of the diode region 20 corresponds to p +The first main surface of the diode region 20 is continuous from the first main surface of the IGBT region 10. The second main surface of the diode region 20 corresponds to the n + The second main surface of the semiconductor substrate of the diode region 20 is continuous from the second main surface of the IGBT region 10. Figure 7 The semiconductor substrate corresponds to the p + The upper surface of the n-type contact layer 24 extends from the upper surface to the n-type contact layer 24. + The range extends from the lower surface of the cathode layer 26 to the upper surface of the cathode layer 26.

[0100] n - The n-type drift layer 1 is formed as an inner layer of the semiconductor substrate. - n type drift layer 1 and IGBT region 10 - The n-type drift layer 1 is similarly provided between the first and second main surfaces of the semiconductor substrate. - n type drift layer 1 and IGBT region 10 - Similarly, the n-type drift layer 1 may also be derived from the structure of the substrate before each structure is formed on the first main surface side and the second main surface side of the semiconductor substrate. - The n-type drift layer 1 is formed continuously and integrally. In other words, the n-type drift layer 1 of the diode region 20 and the IGBT region 10 is formed continuously and integrally. - The type drift layer 1 is formed on the same semiconductor substrate.

[0101] The n-type carrier storage layer 2 has a - The n-type carrier accumulating layer 2 provided in the diode region 20 extends in the same plane as the n-type carrier accumulating layer 2 provided in the IGBT region 10. For example, the thickness and impurity concentration of the n-type carrier accumulating layer 2 in the diode region 20 are the same as those of the n-type carrier accumulating layer 2 in the IGBT region 10.

[0102] The p-type anode layer 25 is provided on the first main surface side of the semiconductor substrate relative to the n-type carrier storage layer 2. The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+12 / cm 3 and less than or equal to 1.0E+19 / cm 3The p-type impurity concentration of the p-type anode layer 25 is, for example, the same as the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10. When the p-type impurity concentrations are the same, the p-type anode layer 25 is formed simultaneously with the p-type base layer 15. Alternatively, for example, the p-type impurity concentration of the p-type anode layer 25 may be lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10. When the p-type impurity concentration of the p-type anode layer 25 is low, the amount of holes injected into the diode region 20 during diode operation is reduced. Consequently, recovery loss during diode operation is reduced.

[0103] p + The p-type contact layer 24 is provided on the first main surface side of the semiconductor substrate relative to the p-type anode layer 25. Figure 6 and the following Figure 8 As shown, p + The p-type contact layer 24 is selectively provided on the upper surface side of the p-type anode layer 25. Figure 7 In the CC section shown, p + The p-type contact layer 24 covers the entire surface of the p-type anode layer 25. In other words, in the diode region 20, the p + The p-type contact layer 24 is selectively provided on the upper surface side of the p-type anode layer 25 as a surface layer on the first main surface side of the semiconductor substrate. + The p-type contact layer 24 is a semiconductor layer containing boron, aluminum, or the like as a p-type impurity. + The concentration of the p-type impurity in the p-type contact layer 24 is higher than that of the p-type impurity in the p-type anode layer 25. The concentration of the p-type impurity is preferably greater than or equal to 1.0E+15 / cm 3 and less than or equal to 1.0E+20 / cm 3 .

[0104] The n-type buffer layer 3 is relatively - The n-type drift layer 1 is provided on the second main surface side of the semiconductor substrate. The n-type buffer layer 3 provided in the diode region 20 extends in the same plane as the n-type buffer layer 3 provided in the IGBT region 10. For example, the thickness and impurity concentration of the n-type buffer layer 3 in the diode region 20 are the same as those of the n-type buffer layer 3 in the IGBT region 10.

[0105] n + The n-type cathode layer 26 is provided on the second main surface side of the semiconductor substrate relative to the n-type buffer layer 3. + The surface (lower surface) of the cathode layer 26 constitutes the second main surface of the semiconductor substrate. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is preferably greater than or equal to 1.0E+16 / cm 3and less than or equal to 1.0E+21 / cm 3 .

[0106] The diode trench gate 21 extends p from the first main surface of the semiconductor substrate. + The p-type contact layer 24, the p-type anode layer 25 and the n-type carrier storage layer 2 penetrate to reach the n-type carrier storage layer 2. - Type drift layer 1.

[0107] The diode trench insulating film 21b is formed along the inner wall of a trench formed in the depth direction from the first main surface of the semiconductor substrate. The diode trench insulating film 21b is, for example, an oxide film.

[0108] The diode trench electrode 21a is formed inside the trench via the diode trench insulating film 21b. The bottom of the diode trench electrode 21a is connected to the n-type diode trench insulating film 21b via the diode trench insulating film 21b. - The diode trench electrode 21a is opposite to the type drift layer 1. The diode trench electrode 21a is formed of, for example, conductive polysilicon.

[0109] The barrier metal 5 is provided on the p + The barrier metal 5 is formed of a metal containing titanium, such as Ti, TiN, or TiSi, similar to the barrier metal 5 of the IGBT region 10. + The type contact layer 24 and the diode trench electrode 21a are in ohmic contact.

[0110] The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 is preferably formed of, for example, an aluminum alloy (Al-Si alloy), similar to the emitter electrode 6 of the IGBT region 10. The emitter electrode 6 is connected to the diode trench electrode 21a and the p-type diode via the barrier metal 5. + The type contact layer 24 is electrically connected.

[0111] The collector electrode 7 is provided at n + The collector electrode 7 is preferably formed of an aluminum alloy, similarly to the collector electrode 7 of the IGBT region 10. + The cathode layer 26 is in ohmic contact.

[0112] Figure 8 1 is a cross-sectional view showing the structure of the diode region 20 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 8 Show Figure 6 The cross section at line segment DD is shown.

[0113] Figure 8 The cross section shown is Figure 7 The cross section shown is different in that the p-type semiconductor substrate is not provided on the first main surface side. +Type contact layer 24. Figure 6 As shown, p + The p-type contact layer 24 is selectively provided on the upper surface side of the p-type anode layer 25. + In the region of the p-type contact layer 24, the first main surface of the semiconductor substrate corresponds to the surface (upper surface) of the p-type anode layer 25. Figure 8 In the cross section shown, one diode unit includes a p-type anode layer 25, an n-type carrier storage layer 2, and an n-type carrier storage layer 2. - Type drift layer 1, n-type buffer layer 3, n + type cathode layer 26, barrier metal 5, emitter electrode 6 and collector electrode 7.

[0114] The structure of the diode region 20 has been described above, but the structure of the diode region 20 is not limited to the above structure. + The p-type contact layer 24 and the p-type anode layer 25 can also be combined to form one p-type anode layer. + The concentration of the p-type impurities in the p-type contact layer 24 can be equal to that of the p-type impurities in the IGBT region 10. + The p-type impurities of the p-type contact layer 14 may be the same or different.

[0115] The n-type carrier storage layer 2 and n - The n-type drift layer 1 can also be combined to form an n-type drift layer. The n-type carrier accumulation layer 2 of the diode region 20 is not essential, and an n-type carrier accumulation layer 2 can also be provided at the position of the n-type carrier accumulation layer 2. - Even when the n-type carrier accumulating layer 2 is provided in the IGBT region 10 , it is not necessary to provide the n-type carrier accumulating layer 2 in the diode region 20 .

[0116] The n-type buffer layer 3 and n - The n-type drift layer 1 can also be combined to form an n-type drift layer. - The n-type drift layer 1 can also be combined to form an n-type drift layer. In addition, the n-type buffer layer 3 is not necessary, and an n-type buffer layer 3 can also be provided at the position of the n-type buffer layer 3. - Type drift layer 1.

[0117] n + The n-type cathode layer 26 may be provided in the entire diode region 20 or in a portion thereof. Although omitted from the figure, the semiconductor device 100 and the semiconductor device 101 may also include n-type cathode layer 26. + Type cathode layer 26 and p + The semiconductor layer of the second main surface of the semiconductor substrate constituting the diode region 20 is formed by alternating arrangement of the n-type cathode layer. +The p-type cathode layer 26 is formed by selectively implanting p-type impurities into a portion of the region. + Type cathode layer 26 and p + A diode in which semiconductor layers are alternately arranged with cathode layers is called an RFC (Relaxed Field of Cathode) diode.

[0118] The barrier metal 5 is not necessary. In the case where the barrier metal 5 is not provided, the emitter electrode 6 is provided on the p-type anode layer 25. + The emitter electrode 6 is formed on the contact layer 24 and on the diode trench electrode 21a, making ohmic contact therewith. An interlayer insulating film 4 may also be provided on a portion of the diode trench electrode 21a. In this case, the emitter electrode 6 is electrically connected to the diode trench electrode 21a at a certain region on the diode trench electrode 21a.

[0119] (4) Structure of the Boundary between the IGBT Region 10 and the Diode Region 20

[0120] Figure 9 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region 10 and the diode region 20 . Figure 9 Show Figure 1 or Figure 2 The cross section at line segment EE is shown.

[0121] The p-type collector layer 16 provided on the second main surface side of the IGBT region 10 extends from the boundary between the IGBT region 10 and the diode region 20 to the diode region 20 by a distance U1. Compared with the structure in which the p-type collector layer 16 does not extend to the diode region 20, n + The distance between the cathode layer 26 and the active trench gate 11 is increased. In such a structure, when the freewheeling diode is in operation, even if the gate drive voltage is applied to the gate trench electrode 11a, the current flows from the channel formed adjacent to the active trench gate 11 to the n-type cathode layer 26. + The current of the cathode layer 26 is reduced. The distance U1 is, for example, 100 μm. However, depending on the application of the semiconductor device 100 or the semiconductor device 101, the distance U1 may be 0 μm or a distance smaller than 100 μm.

[0122] (5) Structure of the terminal region 30

[0123] Figure 10 It is a cross-sectional view showing the structure of the boundary portion between the IGBT region 10 and the termination region 30 . Figure 10 Show Figure 1 or Figure 2 The cross section is shown at line segment FF. Figure 113 is a cross-sectional view showing the structure of the boundary portion between the diode region 20 and the termination region 30 . Figure 11 Show Figure 1 The cross section at line segment GG is shown.

[0124] The semiconductor device 100 and the semiconductor device 101 include a p-type termination well layer 31 and an n-type termination well layer 32 in the termination region 30 . + Type channel stop layer 32, n - type drift layer 1 , n-type buffer layer 3 , p-type terminal collector layer 16 a , interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 , terminal electrode 6 a , semi-insulating film 33 , terminal protection film 34 and collector electrode 7 .

[0125] In the above structure, the p-type end well layer 31 and n + Type channel stop layer 32, n - The n-type drift layer 1 , the n-type buffer layer 3 , and the p-type terminal collector layer 16 a are provided between the first main surface and the second main surface of the semiconductor substrate.

[0126] The first main surface of the semiconductor substrate in the terminal region 30 corresponds to n - type drift layer 1, p-type end well layer 31 and n + The first main surface of the termination region 30 is continuous with the first main surface of the IGBT region 10 or the diode region 20. The second main surface of the semiconductor substrate of the termination region 30 corresponds to the surface (lower surface) of the p-type termination collector layer 16a. The second main surface of the termination region 30 is continuous with the second main surface of the IGBT region 10 or the diode region 20.

[0127] n - n type drift layer 1 and IGBT region 10 and diode region 20 - The n type drift layer 1 is similarly provided between the first main surface and the second main surface of the semiconductor substrate. - A portion of the n-type drift layer 1 is exposed on the first main surface as a surface layer of the semiconductor substrate. - n type drift layer 1 and IGBT region 10 and diode region 20 - Similarly, the n type drift layer 1 may also be derived from the structure of the substrate before each structure is formed on the first main surface side or the second main surface side of the semiconductor substrate. - The n-type drift layer 1 is continuously and integrally formed. In other words, the n-type drift layer 1 of the terminal region 30, the IGBT region 10 and the diode region 20 is continuously and integrally formed. - The type drift layer 1 is formed on the same semiconductor substrate.

[0128] The p-type end well layer 31 is relatively close to the n - The p-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. The p-type end well layer 31 is provided in a manner covering the cell area when viewed from above. In embodiment 1, the three p-type end well layers 31 form a triple ring when viewed from above and surround the cell area. The three p-type end well layers 31 form an FLR. The number of p-type end well layers 31 is not limited to three. The number of p-type end well layers 31 is appropriately selected based on the withstand voltage design of the semiconductor device 100 or the semiconductor device 101. The p-type end well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is greater than or equal to 1.0E+14 / cm 3 and less than or equal to 1.0E+19 / cm 3 .

[0129] n + The channel stopper layer 32 has a - The type drift layer 1 is provided on the first main surface side of the semiconductor substrate. + The p-type channel stopper layer 32 is provided outside the p-type end well layer 31 in a plan view. + The p-type channel stopper layer 32 is provided so as to surround the p-type termination well layer 31 .

[0130] The n-type buffer layer 3 is relatively - The n-type buffer layer 3 provided in the terminal region 30 has the same structure as the n-type buffer layer 3 provided in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 provided in the terminal region 30 is formed continuously and integrally with the n-type buffer layer 3 provided in the IGBT region 10 or the diode region 20. - The n-type drift layer 1 can also be combined to form an n-type drift layer. In addition, the n-type buffer layer 3 is not necessary. An n-type buffer layer 3 can also be provided at the position of the n-type buffer layer 3. - Type drift layer 1.

[0131] P-type terminal collector layer 16a is provided on the second main surface side of the semiconductor substrate relative to n-type buffer layer 3. P-type terminal collector layer 16a has the same structure as p-type collector layer 16 provided in IGBT region 10. P-type terminal collector layer 16a is formed continuously and integrally with p-type collector layer 16 provided in IGBT region 10. Alternatively, p-type terminal collector layer 16a of terminal region 30 and p-type collector layer 16 of IGBT region 10 may be combined to form a single p-type collector layer.

[0132] like Figure 11As shown, the p-type terminal collector layer 16a extends from the boundary between the diode region 20 and the terminal region 30 to the diode region 20 by a distance U2. Compared with the structure in which the p-type terminal collector layer 16a does not extend to the diode region 20, n + The distance between the p-type cathode layer 26 and the p-type end well layer 31 is increased. This structure prevents the p-type end well layer 31 from functioning as the anode of the freewheeling diode. The distance U2 is, for example, 100 μm.

[0133] The interlayer insulating film 4 is provided on the first main surface of the semiconductor substrate. The interlayer insulating film 4 has a contact hole. The contact hole is connected to the p-type terminal well layer 31 and the n-type terminal well layer 31. + The position of the p-type channel stopper layer 32 is correspondingly arranged. + The surface of the channel stopper layer 32 is exposed from the contact hole.

[0134] The barrier metal 5 is disposed on the p-type terminal well layer 31 and the n-type terminal well layer 31. + Type channel stopper layer 32.

[0135] The emitter electrode 6 is electrically connected to the p-type termination well layer 31 near the IGBT region 10 or the diode region 20 via the barrier metal 5. The emitter electrode 6 of the termination region 30 is formed continuously and integrally with the emitter electrode 6 of the IGBT region 10 or the diode region 20.

[0136] The terminal electrode 6a is separated from the emitter electrode 6 and is provided outside the emitter electrode 6. The terminal electrode 6a is connected to the p-type terminal well layer 31 and the n-type terminal well layer 31 via the barrier metal 5 in the contact hole. + The channel stopper layer 32 is electrically connected to the substrate.

[0137] The semi-insulating film 33 is provided so as to electrically connect the emitter electrode 6 and the terminal electrode 6a. The semi-insulating film 33 is, for example, a semi-insulating silicon nitride film (sin SiN).

[0138] The terminal protection film 34 covers the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33. The terminal protection film 34 is formed of, for example, polyimide.

[0139] The collector electrode 7 is provided on the p-type terminal collector layer 16a, that is, on the second main surface of the semiconductor substrate. The collector electrode 7 of the terminal region 30 is formed continuously and integrally with the collector electrodes 7 of the IGBT region 10 and the diode region 20.

[0140] (6) Structure of the Capacitance Adjustment Region 50

[0141] Figure 121 is a plan view showing the structure of the capacitance adjustment region 50 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 12 The arrangement of semiconductor layers forming the first main surface of the semiconductor substrate is shown, and the interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 , and gate wiring 42 on the first main surface of the semiconductor substrate are shown through perspective.

[0142] The semiconductor devices 100 and 101 include a control trench gate 51 in the capacitance adjustment region 50 .

[0143] The control trench gate 51 extends in one direction. The control trench gate 51 of the first embodiment extends in the same direction as the active trench gate 11 and the dummy trench gate 12. However, the extending direction of the control trench gate 51 is not limited thereto.

[0144] The control trench gate 51 includes a control trench insulating film 51b and a control trench electrode 51a. The cross-sectional structure of the control trench gate 51 will be described in detail later. The control trench insulating film 51b is formed along the inner wall of a trench formed in the depth direction from the first main surface of the semiconductor substrate. The control trench electrode 51a is formed within the trench via the control trench insulating film 51b.

[0145] In the capacitance adjustment region 50, a p-type semiconductor layer 55 is provided as a surface layer on the first main surface side of the semiconductor substrate. In addition, an n-type semiconductor layer 55 is selectively provided on the p-type semiconductor layer 55. + Type source layer 53. + The type source layer 53 contacts both side surfaces of the control trench gate 51 and extends along the two side surfaces.

[0146] The interlayer insulating film 4 includes a plurality of contact holes 4a and 4b. Figure 12 In the embodiment, the interlayer insulating film 4 covers the area other than the contact holes 4a and 4b. The contact hole 4a is provided above the control trench electrode 51a at the end of the control trench gate 51. The control trench electrode 51a is exposed from the contact hole 4a. The contact hole 4b is provided between two adjacent control trench gates 51. + The p-type source layer 53 and the p-type semiconductor layer 55 are exposed from the contact hole 4b.

[0147] The gate wiring 42 covers the end of the control trench gate 51. The gate wiring 42 is electrically connected to the control trench electrode 51a via the contact hole 4a. Although not shown, the gate wiring 42 is electrically connected to the gate pad 41c and the gate trench electrode 11a. Therefore, the control trench electrode 51a and the gate trench electrode 11a have approximately the same potential.

[0148] Not all control trench electrodes 51a need be connected to the gate wiring 42, and at least one control trench electrode 51a only needs to be electrically connected to the gate wiring 42. The control trench electrode 51a may be directly electrically connected to the gate pad 41c without passing through the gate wiring 42.

[0149] The emitter electrode 6 covers the inner region of the control trench gate 51. Although not shown in the figure, the emitter electrode 6 extends from the IGBT region 10 to the capacitance adjustment region 50. That is, the emitter electrode 6 of the capacitance adjustment region 50 is electrically connected to the emitter electrode 6 of the IGBT region 10. The emitter electrode 6 is connected to the n-type capacitor via the contact hole 4b. + The p-type source layer 53 and the p-type semiconductor layer 55 form an ohmic contact.

[0150] Figure 13 1 is a cross-sectional view showing the structure of the capacitance adjustment region 50 of the semiconductor devices 100 and 101 according to the first embodiment. Figure 13 Show Figure 12 The cross section is shown at line segment HH.

[0151] The semiconductor device 100 and the semiconductor device 101 include n in the capacitance adjustment region 50. + Type source layer 53, p-type semiconductor layer 55, n - type drift layer 1 , n-type buffer layer 3 , p-type collector layer 16 , control trench gate 51 , interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 and collector electrode 7 .

[0152] One capacitance adjustment unit corresponds to, for example, a region divided by the control trench gate 51. The capacitance adjustment unit includes n + Type source layer 53, p-type semiconductor layer 55, n - type drift layer 1 , n-type buffer layer 3 , p-type collector layer 16 , control trench gate 51 , interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 and collector electrode 7 .

[0153] The first main surface of the semiconductor substrate in the capacitance adjustment region 50 corresponds to n + The second main surface of the semiconductor substrate in the capacitance adjustment region 50 corresponds to the surface (lower surface) of the p-type collector layer 16. In other words, Figure 13 The semiconductor substrate corresponds to the + The range from the upper surfaces of the p-type source layer 53 and the p-type semiconductor layer 55 to the lower surface of the p-type collector layer 16 .

[0154] n - The n-type drift layer 1 is formed as an inner layer of the semiconductor substrate. -The drift layer 1 has an n-type contact with the IGBT region 10. - The capacitance adjustment region 50 and the IGBT region 10 have the same structure as the drift layer 1. - The drift layer 1 is continuously and integrally formed.

[0155] The p-type semiconductor layer 55 is opposite to the n-type semiconductor layer 55. - The p-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. The p-type semiconductor layer 55 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is greater than or equal to 1.0E+14 / cm 3 and less than or equal to 1.0E+19 / cm 3 The p-type semiconductor layer 55 is formed, for example, simultaneously with the p-type termination well layer 31 of the termination region 30. The p-type semiconductor layer 55 is, for example, a diffusion layer formed by ion implantation of p-type impurities and heat treatment.

[0156] n + The n-type source layer 53 is provided on the first main surface side of the semiconductor substrate relative to the p-type semiconductor layer 55. + The p-type source layer 53 is selectively provided on the upper surface side of the p-type semiconductor layer 55 as a surface layer of the semiconductor substrate. + The n-type source layer 53 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is preferably greater than or equal to 1.0E+17 / cm 3 and less than or equal to 1.0E+20 / cm 3 . The capacitance adjustment area 50 n + The type source layer 53 is, for example, connected to the n-type source layer of the IGBT region 10. + The type source layer 13 is formed at the same time.

[0157] The n-type buffer layer 3 and the p-type collector layer 16 of the capacitance adjustment region 50 have the same structures as the n-type buffer layer 3 and the p-type collector layer 16 of the IGBT region 10 , respectively.

[0158] The control trench gate 51 extends n from the first main surface of the semiconductor substrate. + However, the front end of the trench is located in the p-type semiconductor layer 55 and does not reach the n-type source layer 53. - Type drift layer 1.

[0159] The control trench insulating film 51b is formed along the inner wall of the trench. + The p-type source layer 53 is in contact with the p-type semiconductor layer 55. The control trench insulating film 51b is, for example, an oxide film. The structure of the control trench insulating film 51b is, for example, the same as that of the gate trench insulating film 11b.

[0160] The control trench electrode 51a is formed within the trench, with the control trench insulating film 51b interposed therebetween. The bottom of the control trench electrode 51a faces the p-type semiconductor layer 55, with the control trench insulating film 51b interposed therebetween. The control trench electrode 51a is formed, for example, of conductive polysilicon. The structure of the control trench electrode 51a is, for example, the same as that of the gate trench electrode 11a.

[0161] The interlayer insulating film 4 is as follows Figure 12 As shown, the area outside the contact holes 4a and 4b is covered. Figure 13 In FIG. 5 , the interlayer insulating film 4 is provided on the control trench electrode 51 a .

[0162] The barrier metal 5 , emitter electrode 6 , and collector electrode 7 of the capacitance adjustment region 50 have the same structures as those of the barrier metal 5 , emitter electrode 6 , and collector electrode 7 of the IGBT region 10 , respectively.

[0163] As described above, the semiconductor devices 100 and 101 of the first embodiment include a semiconductor substrate, an IGBT region 10, and a capacitance adjustment region 50. The IGBT region 10 and the capacitance adjustment region 50 are provided on the semiconductor substrate. The IGBT region 10 includes an IGBT.

[0164] The capacitance adjustment region 50 includes a p-type semiconductor layer 55, an n-type semiconductor layer 56, and a p-type semiconductor layer 57. + The p-type source layer 53 and a plurality of control trench gates 51. The p-type semiconductor layer 55 is provided as a surface layer on the upper surface of the semiconductor substrate. + The p-type source layer 53 is selectively provided on the upper surface side of the p-type semiconductor layer 55 as the surface layer of the semiconductor substrate. Each of the plurality of control trench gates 51 includes a control trench insulating film 51b and a control trench electrode 51a. The control trench insulating film 51b is formed on the inner wall of the trench. The trench is connected to the upper surface of the semiconductor substrate. + The p-type source layer 53 penetrates through the p-type semiconductor layer 55 and has a front end in the p-type semiconductor layer 55. The control trench electrode 51a is formed inside the trench via a control trench insulating film 51b.

[0165] n + The p-type source layer 53 is in contact with the side surfaces of the plurality of control trench gates 51. + The type source layer 53 is electrically connected to the emitter electrode 6 of the IGBT. The control trench electrode 51a of at least one control trench gate 51 among the plurality of control trench gates 51 is electrically connected to the gate trench electrode 11a of the IGBT.

[0166] In the semiconductor devices 100 and 101, the control trench electrode 51a, the gate trench electrode 11a, and the gate pad 41c have substantially the same potential. Furthermore, the p-type semiconductor layer 55 is in ohmic contact with the emitter electrode 6. A capacitance is formed between the control trench electrode 51a and the p-type semiconductor layer 55, which serves as an additional capacitance (C) between the gate and emitter. ge’ ) and it works.

[0167] In order to adjust the input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) and changes the structure of the active trench gate 11 and its surroundings in the IGBT region 10, the input capacitance (C ge +C gc ) and feedback capacitor (C gc ) changes. Therefore, the input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) has a narrow range. On the other hand, the semiconductor devices 100 and 101 have a narrow range of ratios between the additional capacitance (C ge’ ) and adjust the input capacitance (C ge +C gc ) and the feedback capacitor (C gc That is, the adjustable range of the ratio is expanded.

[0168] And, n + The source layer 53 is arranged in such a manner as to be in contact with the control trench gate 51 and electrically connected to the emitter electrode 6, so that the additional capacitance (C ge’ ) frequency response is improved. Even with respect to the on-off speed of the IGBT, the additional capacitance (C ge’ ) is also stably formed. The semiconductor devices 100 and 101 can achieve input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) to reduce the switching loss.

[0169] In the first embodiment, an example in which the semiconductor devices 100 and 101 are RC-IGBTs is shown. However, even if the semiconductor devices 100 and 101 are IGBTs that do not have the diode region 20 , the same effects as described above can be achieved.

[0170] (Variation 1 of Implementation Example 1)

[0171] The pitch of the plurality of control trench gates 51 is preferably narrower than the pitch of the plurality of active trench gates 11. The additional capacitance (C ge’ ) increases. As a result, the input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) is expanded.

[0172] (Variation 2 of Implementation 1)

[0173] The control trench insulating film 51b is preferably thinner than the gate trench insulating film 11b. The additional capacitance (C ge’ ) increases. As a result, the input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) is expanded.

[0174] (Variation 3 of Implementation 1)

[0175] The depth of the control trench gate 51 from the upper surface of the semiconductor substrate is preferably deeper than the depth of the active trench gate 11 from the upper surface of the semiconductor substrate. ge’ ) increases. Input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) is expanded.

[0176] (Variation 4 of Implementation 1)

[0177] Figure 14 This is a plan view showing the structure of the capacitance adjustment region 50 according to the fourth modification of the first embodiment. Figure 14 and Figure 12 Similarly, the interlayer insulating film 4 , the barrier metal 5 , the emitter electrode 6 , and the gate wiring 42 are shown in a transparent state.

[0178] Figure 14 The width of the contact hole 4b is shown as Figure 12 The contact hole 4b shown has a narrow width. + The type source layer 53 is intermittently exposed from the contact hole 4b in the extending direction of the contact hole 4b. Even in such a structure, the above-mentioned effect can be obtained.

[0179] (Variation 5 of Implementation Example 1)

[0180] Figure 15 This is a plan view showing the structure of the capacitance adjustment region 50 according to the fifth modification of the first embodiment. Figure 15 and Figure 12 Similarly, the interlayer insulating film 4 , the barrier metal 5 , the emitter electrode 6 , and the gate wiring 42 are shown in a transparent state.

[0181] n + The type source layer 53 may be arranged so as to partially contact both side surfaces of the control trench gate 51 in a plan view. The above-mentioned effects can also be obtained in such a structure.

[0182] <Implementation Method 2>

[0183] A semiconductor device according to Embodiment 2 will be described. Embodiment 2 is a subordinate concept of Embodiment 1. In Embodiment 2, the same components as those in Embodiment 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0184] Figure 16 It is a plan view showing the structure of the capacitance adjustment region 50 of the semiconductor devices 100 and 101 according to the second embodiment. Figure 16 The interlayer insulating film 4 , the barrier metal 5 , the emitter electrode 6 , the gate wiring 42 , and the control pad 41 are shown in a transparent state.

[0185] The emitter electrode 6 extends from the IGBT region 10 to the capacitance adjustment region 50 , and is arranged between the control pad 41 and the gate line 42 in a plan view.

[0186] Control trench gate 51 extends in one direction, passing directly below control pad 41. In other words, at least a portion of control trench gate 51 is covered by control pad 41. Control pad 41 may be, for example, any of current sensing pad 41a, Kelvin emitter pad 41b, gate pad 41c, and temperature sensing diode pads 41d and 41e, but is not limited thereto.

[0187] The end portion of the control trench gate 51 is not covered by the control pad 41 but is covered by the gate wiring 42. The contact hole 4a for connecting the control trench electrode 51a to the gate wiring 42 is formed only at the end portion of the control trench gate 51. The control trench electrode 51a is electrically connected to the gate wiring 42 via the contact hole 4a only at the end portion of the control trench gate 51.

[0188] For the p-type semiconductor layer 55 and the n + The contact hole 4b connecting the p-type source layer 53 and the emitter electrode 6 is formed only in the region between the control pad 41 and the gate wiring 42. Here, the contact hole 4b is provided at a position closer to the end than the center in the extending direction of the control trench gate 51. +The type source layer 53 is electrically connected to the emitter electrode 6 via the contact hole 4b only in the region between the control pad 41 and the gate line 42 .

[0189] A portion of the capacitance adjustment unit is also formed directly below the control pad 41, thereby reducing the chip area of ​​the semiconductor devices 100 and 101. Even when the chip area is maintained, the area of ​​the capacitance adjustment region 50 is increased, and thus the input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) is expanded.

[0190] Figure 17 is the voltage applied to the control trench electrode 51a and the additional capacitance (C ge’ ) is a graph showing the relationship between . Figure 17 The simulation results obtained by 3D TCAD (Technology CAD) are shown. Figure 17 China-Israel Figure 16 The structure shown is based on the configuration shown with n + The case where the n-type source layer 53 is not provided + Two results in the case of type source layer 53.

[0191] In the control trench electrode 51 a connected to the gate trench electrode 11 a and the gate pad 41 c , a voltage applied to the control trench electrode 51 a corresponds to the gate drive voltage of the IGBT.

[0192] If n is not set + In the case of the type source layer 53, in the region where the voltage of the control trench electrode 51a is high (for example, when it is greater than or equal to 10V), the additional capacitance (C ge’ ) decreases. That is, Figure 17 In the voltage range shown, the additional capacitor (C ge’ ) is unstable. This phenomenon is a common frequency dependency caused by the inversion layer formed around the control trench electrode 51a, i.e., the MOS structure, being unable to follow the high-frequency voltage fluctuation. Here, the contact hole 4b connecting the p-type semiconductor layer 55 and the emitter electrode 6 is provided at a position closer to the end than the center of the control trench gate 51. Figure 12 or Figure 15 Compared to the construction shown, Figure 16 The distance between the inversion layer formed near the center of the control trench gate 51 and the contact hole 4b is long. When the distance between the inversion layer and the contact region is long, such instability is significantly manifested.

[0193] On the other hand, in the case of setting n +In the case of the type source layer 53, even in the region where the voltage of the control trench electrode 51a is high, the additional capacitance (C ge’ ) is also stable and will not decrease. This is because n + The n-type source layer 53 extends from the contact hole 4b to the center of the control trench gate 51. + The type source layer 53 connects the inversion layer near the center of the control trench gate 51 to the contact region, thereby adding capacitance (C ge’ )Stablize.

[0194] (Variation 1 of Implementation 2)

[0195] Figure 18 It is a plan view showing the structure of the capacitance adjustment region 50 according to the first modification of the second embodiment. Figure 18 also with Figure 16 Similarly, the interlayer insulating film 4 , the barrier metal 5 , the emitter electrode 6 , the gate wiring 42 , and the control pad 41 are shown in a transparent state.

[0196] The plurality of control trench gates 51 include a control trench gate 151 and a control trench gate 251 .

[0197] In addition to contact holes 4a and 4b, interlayer insulating film 4 includes contact hole 4c. Contact hole 4a is provided above control trench electrode 51a at the end of control trench gate 151. Contact hole 4c is provided between control pad 41 and gate wiring 42 and above control trench electrode 51a of control trench gate 251. Control trench electrode 51a is exposed through contact hole 4c.

[0198] The control trench electrode 51 a of the control trench gate 151 is electrically connected to the gate line 42 via the contact hole 4 a .

[0199] The control trench electrode 51 a of the control trench gate 251 is electrically connected to the emitter electrode 6 via the contact hole 4 c , and is not connected to the gate wiring 42 .

[0200] The p-type semiconductor layer 55 and the n + The type source layer 53 is electrically connected to the emitter electrode 6 via the contact hole 4 b as in the second embodiment.

[0201] In such a structure, the additional capacitance (C) of the capacitance adjustment region 50 is adjusted by adjusting the number of control trench gates 51 connected to the gate wiring 42, that is, by changing the arrangement of the contact holes 4a and 4c. ge’ ). Input capacitor (C ge +C gc ) and the feedback capacitor (C gc ) is optimized for various usage conditions, and the switching losses of the semiconductor devices 100 and 101 are reduced.

[0202] (Variation 2 of Implementation Example 2)

[0203] Figure 19 This is a plan view showing the structure of the capacitance adjustment region 50 according to the second modification of the second embodiment. Figure 19 also with Figure 16 Similarly, the interlayer insulating film 4 , the barrier metal 5 , the emitter electrode 6 , the gate wiring 42 , and the control pad 41 are shown in a transparent state.

[0204] The plurality of control trench gates 51 include a first control trench gate 351 and a second control trench gate 451 .

[0205] The gate wiring 42 includes a first gate wiring pattern 142 and a second gate wiring pattern 242. The first gate wiring pattern 142 and the second gate wiring pattern 242 are, for example, metal patterns.

[0206] The first gate wiring pattern 142 is electrically connected to the control trench electrode 51a of the first control trench gate 351 via the contact hole 4a. In other words, the control trench electrode 51a of the first control trench gate 351 is connected to the gate trench electrode 11a via the first gate wiring pattern 142.

[0207] The second gate wiring pattern 242 is electrically connected to the control trench electrode 51a of the second control trench gate 451 via the contact hole 4a. However, the second gate wiring pattern 242 is disconnected. Therefore, the control trench electrode 51a of the second control trench gate 451 is insulated from the gate trench electrode 11a and the gate pad 41c.

[0208] The second gate wiring pattern 242 is formed, for example, by cutting the first gate wiring pattern 142 using a laser. When the laser is cut, the upper surface of the first gate wiring pattern 142 is preferably exposed. The side surfaces of the cut portions of the second gate wiring pattern 242 may include, for example, random uneven surfaces as a result of the laser cutting. The unevenness of the side surfaces of the cut portions of the second gate wiring pattern 242 is greater than the unevenness of the side surfaces of the second gate wiring pattern 242 outside the cut portions.

[0209] The additional capacitance (C ge’ In other words, such a structure makes the additional capacitance (C ge’ ) can be adjusted. The input capacitor (C ge +C gc ) and the feedback capacitor (C gc) is optimized for various usage conditions, and the switching losses of the semiconductor devices 100 and 101 are reduced.

[0210] <Implementation Method 3>

[0211] A semiconductor device according to Embodiment 3 will be described. In Embodiment 3, the same components as those in Embodiment 1 or 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0212] Figure 20 1 is a plan view showing the structure of the capacitance adjustment region 50 of the semiconductor devices 100 and 101 according to the third embodiment. Figure 20 The interlayer insulating film 4 , the barrier metal 5 , the emitter electrode 6 , and the gate wiring 42 are shown in a transparent state.

[0213] Figure 21 1 is a cross-sectional view showing the structure of the capacitance adjustment region 50 of the semiconductor devices 100 and 101 according to the third embodiment. Figure 21 Show Figure 20 The cross section at line segment JJ ​​is shown. Figure 21 The structure of one capacitance adjustment unit is shown. Although only one control trench gate 51 is shown in this capacitance adjustment unit, the semiconductor devices 100 and 101 include a plurality of control trench gates 51 similarly to the first or second embodiment.

[0214] The semiconductor device 100 and the semiconductor device 101 include a p-type semiconductor layer 55 and an n-type semiconductor layer 56 in the capacitance adjustment region 50. - type drift layer 1 , n-type buffer layer 3 , p-type collector layer 16 , control trench gate 51 , interlayer insulating film 4 , barrier metal 5 , emitter electrode 6 and collector electrode 7 .

[0215] The p-type semiconductor layer 55 is selectively provided as a surface layer on the upper surface of the semiconductor substrate and is electrically connected to the emitter electrode 6 .

[0216] n - The p-type drift layer 1 is provided between the p-type semiconductor layer 55 and the lower surface of the semiconductor substrate. - The drift layer 1 has an n-type contact with the IGBT region 10. - The structure of the n type drift layer 1 is the same as that of the n type drift layer 1. However, the n type drift layer 1 of the embodiment 3 - The n-type drift layer 1 is exposed from the region where the p-type semiconductor layer 55 is not provided. - The p-type drift layer 1 is exposed as a surface layer of the semiconductor substrate from a region between a plurality of regions where the p-type semiconductor layer 55 is provided.

[0217] The n-type buffer layer 3 and the p-type collector layer 16 of the capacitance adjustment region 50 have the same structures as the n-type buffer layer 3 and the p-type collector layer 16 of the IGBT region 10 , respectively.

[0218] The control trench gate 51 is provided in the n-type semiconductor layer 55 sandwiched between two regions. - However, in the extension direction of the control trench gate 51, it is not necessary to form all the control trench gates 51 in the n-type drift layer 1. - Type drift layer 1. Figure 20 As shown in FIG. 1 , in the extending direction of the control trench gate 51, the control trench gate 51 may also have a portion in contact with the p-type semiconductor layer 55 and a portion not in contact with the p-type semiconductor layer 55. That is, as long as at least a portion of the control trench gate 51 is formed in the n-type semiconductor layer 55 sandwiched by the p-type semiconductor layer 55, the control trench gate 51 may have a portion in contact with the p-type semiconductor layer 55. - Type drift layer 1 is sufficient.

[0219] The front end of the trench of the control trench gate 51 is located at n - In other words, the bottom of the control trench electrode 51a is separated from the n-type drift layer 1 by the control trench insulating film 51b. - The depth from the first main surface of the semiconductor substrate to the bottom surface of the p-type semiconductor layer 55 is deeper than the depth from the first main surface of the semiconductor substrate to the bottom of the control trench electrode 51a. The bottom surface of the p-type semiconductor layer 55 corresponds to the p-type semiconductor layer 55 and the n-type drift layer 1. - The bonding surface between the type drift layers 1.

[0220] The interlayer insulating film 4 controls the upper surface of the trench gate 51 and the n - The upper surface of the p-type drift layer 1 is covered by the interlayer insulating film 4. The interlayer insulating film 4 includes a plurality of contact holes 4a and 4b. The control trench electrode 51a is exposed from the contact hole 4a. The p-type semiconductor layer 55 is exposed from the contact hole 4b.

[0221] The gate wiring 42 is electrically connected to the control trench electrode 51a via the contact hole 4a. The control trench electrode 51a is electrically connected to the gate trench electrode 11a of the IGBT region 10 via the gate wiring 42. The control trench electrode 51a is electrically connected to the gate pad 41c via the gate wiring 42, for example.

[0222] The emitter electrode 6 extends from the IGBT region 10 to the capacitance adjustment region 50. That is, the emitter electrode 6 in the capacitance adjustment region 50 is in ohmic contact with the p-type semiconductor layer 55 via the contact hole 4b.

[0223] It is not necessary for all the control trench electrodes 51 a in the capacitance adjustment region 50 to be connected to the gate line 42 . It is sufficient for at least one control trench electrode 51 a to be electrically connected to the gate line 42 .

[0224] According to such a structure, a capacitance is formed between the control trench electrode 51a and the p-type semiconductor layer 55 at the bottom of the control trench gate 51, and this capacitance serves as an additional capacitance (C gc’ ) and it works. Figure 18 or Figure 19 The structure shown can also be applied to the semiconductor devices 100 and 101 of the third embodiment. The number of control trench gates 51 electrically connected to the gate trench electrode 11a is adjusted. The semiconductor devices 100 and 101 can reduce the input capacitance (C ge +C gc ) and the feedback capacitor (C gc ) to optimize the ratio between them and reduce the switching loss.

[0225] The control trench gate 51 is separated by n - Since the p-type drift layer 1 is sandwiched between the p-type semiconductor layer 55 , the breakdown voltage is maintained even when a voltage is applied between the emitter and the collector.

[0226] In Embodiment 3, the pitch between the plurality of control trench gates 51 may be narrower than the pitch between the plurality of active trench gates 11 , the control trench insulating film 51 b may be thinner than the gate trench insulating film 11 b , and the control trench gates 51 may be deeper than the active trench gates 11 .

[0227] (Variation 1 of Implementation 3)

[0228] Figure 22 This is a top view showing the structure of the capacitance adjustment region 50 according to the first variation of the third embodiment. The control trench gate 51 may extend in one direction, passing directly below the control pad 41. The control trench electrode 51a is electrically connected to the gate wiring 42 only at the end of the control trench gate 51 via the contact hole 4a. The p-type semiconductor layer 55 is electrically connected to the emitter electrode 6 only in the region between the control pad 41 and the gate wiring 42 via the contact hole 4b.

[0229] (Variation 2 of Implementation 3)

[0230] Figure 23 This is a plan view showing the structure of the capacitance adjustment region 50 according to Modification 2 of Embodiment 3. The plurality of control trench gates 51 include a control trench gate 151 connected to the gate wiring 42 and a control trench gate 251 not connected to the gate wiring 42. The control trench electrode 51a of the control trench gate 251 is electrically connected to the emitter electrode 6 via the contact hole 4c.

[0231] (Variation 3 of Implementation 3)

[0232] Figure 24This is a top view showing the structure of the capacitance adjustment region 50 according to a third variation of the third embodiment. The first gate wiring pattern 142 is electrically connected to the control trench electrode 51a of the first control trench gate 351 at the end of the first control trench gate 351. The second gate wiring pattern 242 is electrically connected to the control trench electrode 51a of the second control trench gate 451 at the end of the second control trench gate 451. However, the second gate wiring pattern 242 is disconnected.

[0233] As described above, the arrangement of the control trench gate 51 and the arrangement of the contact holes 4 a , 4 b , and 4 c in the third embodiment may be the same as those in the first and second embodiments and their modifications.

[0234] The present invention can freely combine the various embodiments, or appropriately modify or omit the various embodiments.

[0235] Description of the label

[0236] 1n - type drift layer, 2n-type carrier accumulation layer, 3n-type buffer layer, 4 interlayer insulating film, 4a contact hole, 4b contact hole, 4c contact hole, 5 barrier metal, 6 emitter electrode, 6a terminal electrode, 7 collector electrode, 10 IGBT region, 11 active trench gate, 11a gate trench electrode, 11b gate trench insulating film, 12 dummy trench gate, 12a dummy trench electrode, 12b dummy trench insulating film, 13n + Type source layer, 14p + type contact layer, 15p type base layer, 16p type collector layer, 16a p type end collector layer, 20 diode region, 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film, 24p + Type contact layer, 25p type anode layer, 26n + type cathode layer, 30 terminal region, 31p type terminal well layer, 32n + channel stop layer, 33 semi-insulating film, 34 terminal protection film, 40 pad area, 41 control pad, 41a current sensing pad, 41b Kelvin emitter pad, 41c gate pad, 41d temperature sensing diode pad, 41e temperature sensing diode pad, 42 gate wiring, 50 capacitance adjustment area, 51 control trench gate, 51a control trench electrode, 51b control trench insulating film, 53n + type source layer, 55p-type semiconductor layer, 82 region, 83 region, 100 semiconductor device, 101 semiconductor device, 142 first gate wiring pattern, 151 control trench gate, 242 second gate wiring pattern, 251 control trench gate, 351 first control trench gate, 451 second control trench gate.

Claims

1. A semiconductor device comprising: semiconductor substrates; a transistor region disposed in the semiconductor substrate, wherein the transistor region includes a transistor; and a capacitance adjustment region, which is provided on the semiconductor substrate, The capacitance adjustment area includes: a first semiconductor layer of a first conductivity type provided as a surface layer on the upper surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is selectively provided on the upper surface side of the first semiconductor layer as the surface layer of the semiconductor substrate; and a plurality of control trench gates, each of which includes a control trench insulating film and a control trench electrode, wherein the control trench insulating film is formed on an inner wall of a trench that penetrates the second semiconductor layer from the upper surface of the semiconductor substrate and has a front end in the first semiconductor layer, and the control trench electrode is formed inside the trench through the control trench insulating film. The second semiconductor layer contacts the side surfaces of the plurality of control trench gates. The first semiconductor layer, the second semiconductor layer, and the emitter electrode of the transistor are electrically connected. The control trench electrode of at least one control trench gate among the plurality of control trench gates is electrically connected to the gate electrode of the transistor.

2. The semiconductor device according to claim 1, wherein The transistor region includes: a second conductive type drift layer disposed between the upper surface and the lower surface of the semiconductor substrate; a first conductive type base layer disposed above the drift layer; a second conductive type source layer selectively provided above the base layer as the surface layer on the upper surface of the semiconductor substrate; a plurality of trench gates, each including a gate trench insulating film and a gate trench electrode, the gate trench insulating film being formed on an inner wall of a trench penetrating the source layer and the base layer from the upper surface of the semiconductor substrate and having a front end within the drift layer, the gate trench electrode being formed within the trench as the gate electrode via the gate trench insulating film; and The emitter electrode is electrically connected to the source layer and insulated from the gate trench electrode. The gate trench electrode of at least one trench gate among the plurality of trench gates is electrically connected to the control trench electrode of the at least one control trench gate.

3. The semiconductor device according to claim 2, wherein A pitch between the plurality of control trench gates is narrower than a pitch between the plurality of trench gates.

4. The semiconductor device according to claim 2, wherein The control trench insulating film is thinner than the gate trench insulating film.

5. The semiconductor device according to claim 3, wherein The control trench insulating film is thinner than the gate trench insulating film.

6. The semiconductor device according to any one of claims 2 to 5, wherein A depth of the plurality of control trench gates from the upper surface of the semiconductor substrate is deeper than a depth of the plurality of trench gates from the upper surface of the semiconductor substrate.

7. The semiconductor device according to any one of claims 1 to 5, wherein Also features: a signal pad, which is used to detect or control the state of the semiconductor substrate; as well as a gate wiring electrically connecting the control trench electrode of the capacitance adjustment region and the gate electrode of the transistor region, The emitter electrode extends from the transistor region to the capacitance adjustment region and is arranged between the signal pad and the gate line in a plan view. The plurality of control trench gates pass directly below the signal pad and extend along one direction of the upper surface of the semiconductor substrate. The ends of the plurality of control trench gates are covered by the gate wiring. The control trench electrode is electrically connected to the gate wiring only at the end portion of the at least one control trench gate. The first semiconductor layer is electrically connected to the emitter electrode only in a region between the signal pad and the gate line.

8. The semiconductor device according to claim 7, wherein The plurality of control trench gates include a control trench gate that is not connected to the gate wiring. A control trench electrode of the control trench gate that is not connected to the gate wiring is electrically connected to the emitter electrode in a region between the signal pad and the gate wiring.

9. The semiconductor device according to claim 7, wherein The plurality of control trench gates include a first control trench gate and a second control trench gate, The gate wiring includes: a first gate wiring pattern electrically connected to the control trench electrode of the first control trench gate at the end portion of the first control trench gate; as well as a second gate wiring pattern electrically connected to the control trench electrode of the second control trench gate at the end portion of the second control trench gate; The second gate wiring pattern is disconnected.

10. A semiconductor device comprising: semiconductor substrates; a transistor region disposed in the semiconductor substrate, wherein the transistor region includes a transistor; and a capacitance adjustment region, which is provided on the semiconductor substrate, The capacitance adjustment area includes: a first semiconductor layer of a first conductivity type, which is selectively provided as a surface layer on the upper surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type, provided between the first semiconductor layer and the lower surface of the semiconductor substrate and exposed as the surface layer of the semiconductor substrate from a region where the first semiconductor layer is not provided as the surface layer of the upper surface of the semiconductor substrate; and a plurality of control trench gates, each of which includes a control trench insulating film and a control trench electrode, wherein the control trench insulating film is formed on an inner wall of a trench having a front end in the second semiconductor layer, and the control trench electrode is formed inside the trench via the control trench insulating film. At least a portion of each of the plurality of control trench gates is provided in the second semiconductor layer sandwiched between a plurality of regions of the first semiconductor layer and exposed as the surface layer of the semiconductor substrate. The first semiconductor layer is electrically connected to the emitter electrode of the transistor, The control trench electrode of at least one control trench gate among the plurality of control trench gates is electrically connected to the gate electrode of the transistor.

11. The semiconductor device according to claim 10, wherein The transistor region includes: a second conductive type drift layer disposed between the upper surface and the lower surface of the semiconductor substrate; a first conductive type base layer disposed above the drift layer; a second conductive type source layer selectively provided above the base layer as the surface layer on the upper surface of the semiconductor substrate; a plurality of trench gates, each including a gate trench insulating film and a gate trench electrode, the gate trench insulating film being formed on an inner wall of a trench penetrating the source layer and the base layer from the upper surface of the semiconductor substrate and having a front end within the drift layer, the gate trench electrode being formed within the trench as the gate electrode via the gate trench insulating film; and The emitter electrode is electrically connected to the source layer and insulated from the gate trench electrode. The gate trench electrode of at least one trench gate among the plurality of trench gates is electrically connected to the control trench electrode of the at least one control trench gate.

12. The semiconductor device according to claim 11, wherein A pitch between the plurality of control trench gates is narrower than a pitch between the plurality of trench gates.

13. The semiconductor device according to claim 11, wherein The control trench insulating film is thinner than the gate trench insulating film.

14. The semiconductor device according to claim 12, wherein The control trench insulating film is thinner than the gate trench insulating film.

15. The semiconductor device according to any one of claims 11 to 14, wherein A depth of the plurality of control trench gates from the upper surface of the semiconductor substrate is deeper than a depth of the plurality of trench gates from the upper surface of the semiconductor substrate.

16. The semiconductor device according to any one of claims 10 to 14, wherein Also features: a signal pad, which is used to detect or control the state of the semiconductor substrate; as well as a gate wiring electrically connecting the control trench electrode of the capacitance adjustment region and the gate electrode of the transistor region, The emitter electrode extends from the transistor region to the capacitance adjustment region and is arranged between the signal pad and the gate line in a plan view. The plurality of control trench gates pass directly below the signal pad and extend along one direction of the upper surface of the semiconductor substrate. The ends of the plurality of control trench gates are covered by the gate wiring. The control trench electrode is electrically connected to the gate wiring only at the end portion of the at least one control trench gate. The first semiconductor layer is electrically connected to the emitter electrode only in a region between the signal pad and the gate line.

17. The semiconductor device according to claim 16, wherein The plurality of control trench gates include a control trench gate that is not connected to the gate wiring. A control trench electrode of the control trench gate that is not connected to the gate wiring is electrically connected to the emitter electrode in a region between the signal pad and the gate wiring.

18. The semiconductor device according to claim 16, wherein The plurality of control trench gates include a first control trench gate and a second control trench gate, The gate wiring includes: a first gate wiring pattern electrically connected to the control trench electrode of the first control trench gate at the end portion of the first control trench gate; as well as a second gate wiring pattern electrically connected to the control trench electrode of the second control trench gate at the end portion of the second control trench gate; The second gate wiring pattern is disconnected.

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