Flash memory device and method for manufacturing the same

Abstract

The present invention provides a flash memory device and a manufacturing method thereof. A word line is disposed on a substrate of the flash memory device. A floating gate, an interlayer dielectric layer, and a control gate that are vertically stacked are disposed on both sides of the word line. A first sidewall is disposed on the control gate, and the material of the first sidewall is the same as that of the control gate. A second sidewall is disposed between the control gate and the word line, and a third sidewall is disposed between the floating gate and the word line. By providing the first sidewall and the control gate with the same material, the present invention reduces or avoids the etching damage that the first sidewall may suffer, thereby avoiding the formation of a step at the junction between the first sidewall and the control gate layer, and further maintaining the breakdown voltage of the flash memory device. Further, a metal silicide layer is disposed on the first sidewall of the flash memory device, reducing the contact resistance of the control gate and being beneficial to improving the reading speed of the flash memory device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and particularly to a flash memory device and a manufacturing method thereof. Background Art

[0002] With the development of technology, the application of data storage media has shifted from some traditional non-volatile memories to flash memory-type memories. Large-capacity solid-state storage devices with flash memory as the main storage medium have become one of the mainstream solutions for data storage today. Nord flash (Nord Flasd) devices have occupied an increasingly important position in the memory field due to their performance advantages such as low cost, low power consumption, and fast access speed. However, with the continuous miniaturization of the size of Nord flash devices, in order to avoid the reduction of the erase / write performance and operating voltage of Nord flash devices as the device size shrinks, more stringent requirements need to be imposed on the breakdown voltage inside the Nord flash devices.

[0003] Refer to Figure 1 , a Nord flash device generally includes a floating gate (FG) 10 and a control gate (CG) 20 stacked together, and a composite dielectric layer 30 (such as an ONO stack structure) is formed between the floating gate 10 and the control gate 20. In the existing manufacturing process of Nord flash devices, the first sidewall 40 formed on the surface of the control gate 20 is usually made of an oxide material. During the subsequent wet etching of the composite dielectric layer 30, the first sidewall 40 will be etched by hydrofluoric acid (HF) in the wet process, forming a step A at the junction of the first sidewall 40 and the control gate 20. During the formation of the second sidewall 41, since the second sidewall 41 covers both the surface of the first sidewall 40 and the sidewall of the control gate layer 21, and there is a step A at the junction of the first sidewall 40 and the control gate 20, therefore, the finally formed second sidewall 41 with a smooth surface will have an uneven thickness, that is, the thickness of the part of the second sidewall 41 covering the step A is the thinnest, resulting in a reduction in the breakdown voltage between the subsequent formed control gate and the word line.

[0004] In view of this, a method is needed to reduce or avoid the etching damage that the first sidewall may suffer, and avoid the formation of a step at the junction of the first sidewall and the control gate layer, so as to maintain the breakdown voltage of the flash memory device. Summary of the Invention

[0005] The purpose of the present invention is to provide a flash memory device and a manufacturing method thereof, which can reduce or avoid the etching damage that the first sidewall may suffer, avoid the formation of a step at the junction of the first sidewall and the control gate layer, so as to maintain the breakdown voltage of the flash memory device.

[0006] To achieve the above object, the present invention provides a manufacturing method of a flash memory device, including:

[0007] A substrate is provided, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed. An opening exposing the control gate layer is formed on the hard mask layer;

[0008] A first sidewall is formed on the sidewall of the opening, and the material of the first sidewall is the same as that of the control gate layer;

[0009] The control gate layer exposed by the opening and the interlayer dielectric layer below the opening are removed, so that the opening exposes the floating gate layer, and a second sidewall is formed on the sidewall and the bottom wall of the opening;

[0010] The second sidewall at the bottom of the opening and the floating gate layer below the opening are removed, so that the opening exposes the substrate, and a third sidewall is formed on the sidewall and the bottom wall of the opening;

[0011] A word line is formed in the opening; and,

[0012] The hard mask layer, and the control gate layer, the interlayer dielectric layer, and the floating gate layer below the hard mask layer are removed to form a control gate and a floating gate.

[0013] Optionally, the materials of the control gate layer and the first sidewall are both polysilicon.

[0014] Optionally, the interlayer dielectric layer below the opening is removed by a wet etching process, and the etchant of the wet etching process is hydrofluoric acid.

[0015] Optionally, after forming the word line and before removing the hard mask layer, it further includes:

[0016] Forming a protective layer covering at least the word line.

[0017] Optionally, the second sidewall covers a partial surface of the first sidewall.

[0018] Optionally, after forming the floating gate and the control gate, it further includes:

[0019] Forming a metal silicide layer on the surface of the first sidewall.

[0020] Correspondingly, the present invention further provides a flash memory device, including:

[0021] A substrate;

[0022] A word line disposed on the substrate;

[0023] A floating gate disposed on both sides of the word line;

[0024] A control gate disposed on the floating gate;

[0025] An interlayer dielectric layer, disposed between the floating gate and the control gate;

[0026] A first sidewall, disposed on the control gate, and the material of the first sidewall is the same as that of the control gate;

[0027] A second sidewall, disposed between the control gate and the word line, and the second sidewall covers at least a part of the surface of the first sidewall and the sidewalls of the control gate; and,

[0028] A third sidewall, disposed between the floating gate and the word line, and the third sidewall covers at least a part of the surface of the second sidewall and the sidewalls of the floating gate.

[0029] Optionally, the materials of the control gate and the first sidewall are both polysilicon.

[0030] Optionally, the flash memory device further includes a metal silicide layer disposed on the first sidewall.

[0031] Optionally, the flash memory device is a Nord flash memory.

[0032] In summary, the present invention provides a flash memory device and a manufacturing method thereof. A word line is disposed on a substrate of the flash memory device, and a floating gate, an interlayer dielectric layer, and a control gate are vertically stacked on both sides of the word line. A first sidewall is disposed on the control gate, and the material of the first sidewall is the same as that of the control gate. A second sidewall is disposed between the control gate and the word line, and a third sidewall is disposed between the floating gate and the word line. By providing the first sidewall and the control gate with the same material, the present invention reduces or avoids possible etching damage to the first sidewall, thereby avoiding the formation of a step at the junction of the first sidewall and the control gate layer, and further maintaining the breakdown voltage of the flash memory device.

[0033] Further, a metal silicide layer is disposed on the first sidewall of the flash memory device, reducing the contact resistance of the control gate and facilitating the improvement of the reading speed of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic structural diagram of a Nord flash memory;

[0035] Figure 2 is a flowchart of a manufacturing method of a flash memory device provided by an embodiment of the present invention;

[0036] Figures 3 to 13 is a schematic structural diagram corresponding to each step in the manufacturing method of a flash memory device provided by an embodiment of the present invention;

[0037] Wherein, the reference numerals are as follows:

[0038] 10 - floating gate; 20 - control gate; 30 - composite dielectric layer; 40 - first sidewall; 41 - second sidewall; A - step

[0039] 100 - substrate; 101 - gate oxide layer; 110 - floating gate layer; 111 - floating gate; 120 - interlayer dielectric layer; 130 - control gate layer; 131 - control gate; 140 - hard mask layer; 150 - opening; 151 - first sidewall; 152 - second sidewall; 153 - third sidewall; 160 - word line; 161 - protective layer; 170 - metal silicide layer. Detailed implementation manners

[0040] The following will describe the detailed implementation manners of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0041] Figure 2 It is a flowchart of a manufacturing method of a flash memory device provided in an embodiment of the present invention. Refer to Figure 2 , the manufacturing method of the flash memory device described in this embodiment includes:

[0042] Step S01: Provide a substrate, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed, and an opening exposing the control gate layer is formed on the hard mask layer;

[0043] Step S02: Form a first sidewall on the sidewall of the opening, and the material of the first sidewall is the same as that of the control gate layer;

[0044] Step S03: Remove the control gate layer exposed by the opening and the interlayer dielectric layer below the opening, so that the opening exposes the floating gate layer, and form a second sidewall on the sidewall and bottom wall of the opening;

[0045] Step S04: Remove the second sidewall at the bottom of the opening and the floating gate layer below the opening, so that the opening exposes the substrate, and form a third sidewall on the sidewall and bottom wall of the opening;

[0046] Step S05: Form a word line in the opening; and,

[0047] Step S06: Remove the hard mask layer and the control gate layer, interlayer dielectric layer, and floating gate layer below the hard mask layer to form a control gate and a floating gate.

[0048] Figures 3 to 13 It is a schematic structural diagram corresponding to each step in the manufacturing method of the flash memory device provided in this embodiment. The following combines Figures 3 to 13Describe in detail the manufacturing method of the flash memory device according to this embodiment.

[0049] First, refer to Figure 3 , perform step S01 to provide a substrate 100, on which a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130, and a hard mask layer 140 are sequentially formed. An opening 150 exposing the control gate layer 140 is formed on the hard mask layer 140.

[0050] In this embodiment, a photolithography process and an etching process are performed on the hard mask layer 140 to pattern the hard mask layer 140, thereby forming the opening 150. Optionally, a gate oxide layer 101 is further formed between the substrate 100 and the floating gate layer 110.

[0051] In this embodiment, the substrate 100 is a silicon substrate. The gate oxide layer 110 is a silicon oxide layer. Both the floating gate layer 110 and the control gate layer 130 are polysilicon layers. The interlayer dielectric layer 120 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. In other embodiments of the present invention, Figure 3 The materials of the respective film layers in the shown flash memory device can be selected according to actual needs, and the present invention does not limit this.

[0052] Next, refer to Figure 4 and Figure 5 , perform step S02 to form a first sidewall 151 on the sidewall of the opening 150, and the material of the first sidewall 151 is the same as that of the control gate layer 130.

[0053] Exemplarily, the process of forming the first sidewall 151 includes: First, refer to Figure 4 , deposit and form a first sidewall 151 in the opening 150, and the first sidewall 151 extends to cover the hard mask layer 140 on both sides of the opening 150; Next, refer to Figure 5 , etch the first sidewall 151 to remove the first sidewall 151 on the hard mask layer 140 and the first sidewall 151 at the bottom of the opening 150, so that the remaining first sidewall 151 covers the sidewall of the opening 150 and a partial surface of the control gate layer 130. Optionally, the first sidewall 151 is formed by a chemical vapor deposition process, and the first sidewall 151 is etched by a dry etching process.

[0054] In this embodiment, since the material of the control gate layer 130 is polysilicon and the material of the control gate layer 130 is the same as that of the first sidewall 151, the material of the first sidewall 151 is polysilicon.

[0055] Subsequently, refer to Figure 6 andFigure 7 Execute step S03 to remove the control gate layer 130 exposed by the opening 150 and the interlayer dielectric layer 120 under the opening 150, so that the opening 150 exposes the floating gate layer 110, and form a second sidewall 152 on the sidewalls and the bottom wall of the opening 150.

[0056] Exemplarily, the process of forming the second sidewall 152 includes: First, refer to Figure 6 , use a dry etching process to remove the control gate layer 130 exposed by the opening 150, and then use a wet etching process to remove the interlayer dielectric layer 120 under the opening 150, so that the floating gate layer 110 under the opening 150 is exposed; Then, refer to Figure 7 , form a second sidewall 152 on the sidewalls and the bottom wall of the opening 150 (the formation process of the second sidewall 152 is similar to the formation process of the first sidewall 151 and will not be elaborated here). Optionally, the etching agent for the wet etching process is hydrofluoric acid (HF).

[0057] It should be noted that since the material of the first sidewall 151 is polysilicon, during the process of using the wet etching process to remove the interlayer dielectric layer 120 under the opening 150, the first sidewall 151 will not be etched by the etching agent (i.e., hydrofluoric acid), thus avoiding the appearance of steps at the junction of the first sidewall 151 and the control gate layer 130.

[0058] In this embodiment, the second sidewall 152 covers a part of the surface of the first sidewall 151. In other embodiments of the present invention, the second sidewall 152 may also completely cover the surface of the first sidewall 151, and the present invention does not limit this. Optionally, the second sidewall 152 may be a laminated structure composed of a silicon oxide layer, a silicon nitride layer, or a combination of the two.

[0059] Then, refer to Figure 8 and Figure 9 , execute step S04 to remove the second sidewall 152 at the bottom of the opening 150 and the floating gate layer 110 under the opening 150, so that the opening 150 exposes the substrate 100, and form a third sidewall 153 on the sidewalls and the bottom wall of the opening 150.

[0060] Exemplarily, the process of forming the third sidewall 153 includes: First, refer to Figure 8 , use a dry etching process to remove the second sidewall 152 at the bottom of the opening 150 and the floating gate layer 110 and the gate oxide layer 101 under the opening 150, so that the substrate 100 under the opening 150 is exposed; Then, refer to Figure 9, a third sidewall 153 is formed on the sidewall and the bottom wall of the opening 150 (the formation process of the third sidewall 153 is similar to that of the first sidewall 151 and will not be elaborated here).

[0061] In this embodiment, the third sidewall 153 covers a part of the surface of the second sidewall 155. In other embodiments of the present invention, the third sidewall 153 may also completely cover the surface of the second sidewall 152, and the present invention does not limit this. Optionally, the third sidewall 153 is a silicon oxide layer.

[0062] Subsequently, referring to Figure 10 and Figure 11 , step S05 is performed to form a word line 160 in the opening 150.

[0063] Exemplarily, referring to Figure 10 , the process of forming the word line 160 includes: First, a polysilicon layer (not shown in the figure) is filled in the opening 150, and the polysilicon layer extends to cover the hard mask layers 140 on both sides of the opening 150; then, the polysilicon layer is etched to remove the polysilicon layer on the hard mask layer 140, thereby forming a word line 160 in the opening 150. In this embodiment, the word line 160 is a polysilicon layer.

[0064] Referring to Figure 11 , after forming the word line 160 and before performing step S06, the manufacturing method of the flash memory device described in this embodiment further includes: forming a protective layer 161 that at least covers the word line 160. Optionally, the protective layer 161 is a silicon oxide layer or a silicon nitride layer.

[0065] Next, referring to Figure 12 , step S06 is performed to remove the hard mask layer 140, the control gate layer 130, the interlayer dielectric layer 120, and the floating gate layer 110 below the hard mask layer 140 to form a control gate 131 and a floating gate 111. In this embodiment, a dry etching process is used to remove the hard mask layer 140, the control gate layer 130, the interlayer dielectric layer 120, the floating gate layer 110, and the gate oxide layer 101 below the hard mask layer 140. The protective layer 161 protects the word line 160 from damage during the above etching process, and the protective layer is removed together during the above etching process.

[0066] In addition, referring to Figure 13 , after forming the floating gate 111 and the control gate 131, the manufacturing method of the flash memory device described in this embodiment further includes: forming a metal silicide layer 170 on the surface of the first sidewall 151.

[0067] It should be noted that if the second sidewall 152 formed in step S02 only covers a part of the surface of the first sidewall 151, a metal silicide layer 170 can be directly formed on the exposed part of the surface of the first sidewall 151; if the second sidewall 152 formed in step S02 completely covers the surface of the first sidewall 151, a part of the second sidewall 152 on the first sidewall 151 needs to be etched away by an etching process first to expose a part of the surface of the first sidewall 151, and then a metal silicide layer 170 is formed on the exposed surface of the first sidewall 151.

[0068] Correspondingly, continue to refer to Figure 13 , the present invention also provides a flash memory device, including:

[0069] A substrate 100;

[0070] A word line 160 disposed on the substrate 100;

[0071] A floating gate 111 disposed on both sides of the word line 160;

[0072] A control gate 131 disposed on the floating gate 111;

[0073] An interlayer dielectric layer 120 disposed between the floating gate 111 and the control gate 131;

[0074] A first sidewall 151 disposed on the control gate 131, and the material of the first sidewall 151 is the same as that of the control gate 131;

[0075] A second sidewall 152 disposed between the control gate 131 and the word line 160, and the second sidewall 152 covers at least a part of the surface of the first sidewall 151 and the sidewalls of the control gate 131; and,

[0076] A third sidewall 153 disposed between the floating gate 111 and the word line 160, and the third sidewall 153 covers at least a part of the surface of the second sidewall 152 and the sidewalls of the floating gate 111.

[0077] In this embodiment, the materials of the word line 160, the floating gate 111, the control gate 131, and the first sidewall 151 are all polysilicon. The substrate 100 is a silicon substrate. The interlayer dielectric layer 120 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The second sidewall 152 is a stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, or both of them. The third sidewall 153 is a silicon oxide layer. Optionally, a gate oxide layer 101 is further provided between the substrate 100 and the floating gate 111, and the gate oxide layer 101 is a silicon oxide layer. Optionally, the flash memory device further includes a metal silicide layer 170 provided on the first sidewall 151.

[0078] In this embodiment, the flash memory device is a Nord flash memory, and the manufacturing method of the flash memory device can be used to prepare Nord flash memory devices. In other embodiments of the present invention, the flash memory device can be other semiconductor devices with the same or similar structures, and the manufacturing method of the flash memory device can be used to manufacture other semiconductor devices with the same or similar structures. The present invention does not limit this.

[0079] Comparison Figure 1 and Figure 13 It can be seen that by providing the first sidewall and the control gate with the same material, the present invention reduces or avoids the etching damage that the first sidewall may suffer, thereby avoiding the formation of a step at the junction of the first sidewall and the control gate layer, and further maintaining the breakdown voltage of the flash memory device. In addition, a metal silicide layer is provided on the first sidewall of the flash memory device, which reduces the contact resistance of the control gate and is beneficial to improving the read speed of the flash memory device.

[0080] In summary, the present invention provides a flash memory device and a manufacturing method thereof. A word line is provided on the substrate of the flash memory device, a vertically stacked floating gate, an interlayer dielectric layer, and a control gate are provided on both sides of the word line, a first sidewall is provided on the control gate, and the material of the first sidewall is the same as that of the control gate. A second sidewall is provided between the control gate and the word line, and a third sidewall is provided between the floating gate and the word line. By providing the first sidewall and the control gate with the same material, the present invention reduces or avoids the etching damage that the first sidewall may suffer, thereby avoiding the formation of a step at the junction of the first sidewall and the control gate layer, and further maintaining the breakdown voltage of the flash memory device.

[0081] Furthermore, a metal silicide layer is provided on the first sidewall of the flash memory device, which reduces the contact resistance of the control gate and is beneficial to improving the read speed of the flash memory device.

[0082] The above are only the preferred embodiments of the present invention and do not impose any restrictive effect on the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, makes any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a flash memory device, characterized in that, Comprising: Providing a substrate, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed, and an opening exposing the control gate layer is formed on the hard mask layer; Forming a first sidewall on the sidewall of the opening, and the material of the first sidewall is the same as that of the control gate layer, and the materials of the control gate layer and the first sidewall are both polysilicon; Removing the control gate layer exposed by the opening and the interlayer dielectric layer under the opening, so that the opening exposes the floating gate layer, and forming a second sidewall on the sidewall and the bottom wall of the opening; Removing the second sidewall at the bottom of the opening and the floating gate layer under the opening, so that the opening exposes the substrate, and forming a third sidewall on the sidewall and the bottom wall of the opening; Forming a word line in the opening; And, Removing the hard mask layer and the control gate layer, the interlayer dielectric layer, and the floating gate layer under the hard mask layer to form a control gate and a floating gate.

2. The manufacturing method of the flash memory device according to claim 1, characterized in that, Using a wet etching process to remove the interlayer dielectric layer under the opening, and the etchant of the wet etching process is hydrofluoric acid.

3. The manufacturing method of the flash memory device according to claim 1, characterized in that, After forming the word line and before removing the hard mask layer, further comprising: Forming a protective layer covering at least the word line.

4. The manufacturing method of the flash memory device according to claim 1, characterized in that, The second sidewall covers a partial surface of the first sidewall.

5. The manufacturing method of the flash memory device according to claim 4, characterized in that, After forming the floating gate and the control gate, further comprising: Forming a metal silicide layer on the surface of the first sidewall.

6. A flash memory device, characterized in that, Comprising: A substrate; A word line disposed on the substrate; A floating gate disposed on both sides of the word line; A control gate disposed on the floating gate; An interlayer dielectric layer disposed between the floating gate and the control gate; A first sidewall disposed on the control gate, and the material of the first sidewall is the same as that of the control gate layer, and the materials of the control gate layer and the first sidewall are both polysilicon; A second sidewall disposed between the control gate and the word line, and the second sidewall covers at least a partial surface of the first sidewall and the sidewall of the control gate; And, A third sidewall disposed between the floating gate and the word line, and the third sidewall covers at least a partial surface of the second sidewall and the sidewall of the floating gate.

7. The flash memory device according to claim 6, wherein The materials of the control gate and the first sidewall are both polysilicon.

8. The flash memory device according to claim 6, wherein, The flash memory device further includes a metal silicide layer disposed on the first sidewall.

9. The flash memory device according to claim 6, wherein, The flash memory device is a Nord flash memory.

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