An ldmos power device and a method for manufacturing the same

Abstract

The application belongs to the technical field of semiconductors and provides an LDMOS power device and a preparation method thereof. The LDMOS power device comprises a semiconductor substrate, a buried oxygen region, a P-type well region, a P-type base region, a source region, a drift region, a drain region, a passivation layer, a source electrode, a gate electrode, a drain electrode and a gate extension region. A plurality of substrate grooves opposite to the drift region are arranged on the front surface of the semiconductor substrate, and a plurality of buried oxygen protruding structures matched with the substrate grooves are arranged on the back surface of the buried oxygen region. More holes are gathered by the plurality of substrate grooves, so as to introduce more electric field peaks, enhance the electric field modulation capacity of the device near the drain region, modulate the surface electric field of the LDMOS power device, improve the lateral withstand voltage of the LDMOS power device, and solve the problem of small breakdown voltage of the existing LDMOS power device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to an LDMOS power device and a preparation method thereof. BACKGROUND

[0002] With the improvement of the integration of integrated circuits, the lateral diffusion metal oxide semiconductor (LDMOSFET) is often applied to the design of high-voltage power integrated circuits due to its outstanding advantages such as high-voltage resistance, large driving current, large output power, and good switching characteristics, and is particularly widely used in high-voltage power amplifier occasions. An important parameter of the LDMOSFET is its on-resistance. In practical applications, the on-resistance is an important parameter closely related to performance, and its size is closely related to the maximum output power of the LDMOSFET.

[0003] For high-performance power devices, in addition to high breakdown voltage, it is also necessary to have as low on-resistance as possible. The on-resistance always decreases with the increase of the doping concentration of the drift region, while the relationship between the breakdown voltage and the doping concentration of the drift region is usually more complex. Therefore, we need to optimize the relationship between the breakdown voltage and the on-resistance, and reduce the on-resistance as much as possible under the condition of ensuring a certain breakdown voltage, so as to obtain the largest possible output power. Some literature has studied the on-resistance of the traditional doped LDMOSFET and obtained many achievements, but the problem of small breakdown voltage of the LDMOSFET has not been solved. SUMMARY

[0004] In order to solve the above technical problems, the present application provides an LDMOS power device and a preparation method thereof, which can solve the problem of small breakdown voltage of the existing LDMOS power device.

[0005] The present application provides an LDMOS power device, which comprises:

[0006] a semiconductor substrate;

[0007] a buried oxygen region arranged on the front surface of the semiconductor substrate;

[0008] a P-type well region and a P-type base region, both of which are arranged on the front surface of the buried oxygen region, and the shape of the P-type well region is in the shape of "L", and the P-type base region is in contact with the horizontal part of the P-type well region;

[0009] a source region arranged on the horizontal part of the P-type well region and in contact with the P-type base region;

[0010] a drift region disposed on a front surface of the buried oxide region and in contact with the P-type well region; wherein the drift region has an "L" shape, the front surface of the semiconductor substrate is provided with a plurality of substrate grooves opposite the drift region, and a back surface of the buried oxide region is provided with a plurality of buried oxide protruding structures, the plurality of buried oxide protruding structures being filled in the plurality of substrate grooves;

[0011] a drain region disposed on the horizontal portion of the drift region;

[0012] a passivation layer disposed on the source region, the P-type well region, and the drift region; wherein the passivation layer has an "L" shape;

[0013] a source electrode disposed on the P-type base region;

[0014] a gate electrode disposed on the horizontal portion of the passivation layer; wherein the vertical portion of the passivation layer is between the gate electrode and the source electrode;

[0015] a drain electrode in contact with the drain region;

[0016] a gate extension region disposed on the horizontal portion of the passivation layer and between the gate electrode and the drain electrode.

[0017] In one embodiment, the gate extension region includes:

[0018] a first P-type doped region disposed on the horizontal portion of the passivation layer and in contact with the gate electrode;

[0019] a second P-type doped region disposed on the horizontal portion of the passivation layer and in contact with the first P-type doped region;

[0020] a first N-type doped region disposed on the horizontal portion of the passivation layer and in contact with the second P-type doped region;

[0021] a third P-type doped region disposed on the horizontal portion of the passivation layer and in contact with the first N-type doped region.

[0022] In one embodiment, a depth of the substrate grooves gradually increases from the source region to the drain region.

[0023] In one embodiment, a width of adjacent substrate grooves gradually decreases from the source region to the drain region.

[0024] In one embodiment, a distance between adjacent substrate grooves is equal.

[0025] In one embodiment, a doping concentration of the first P-type doped region is greater than a doping concentration of the second P-type doped region.

[0026] In one embodiment, the second P-type doped region has a width greater than that of the first P-type doped region.

[0027] In one embodiment, the drift region has a doping concentration gradually decreasing from a central region to left and right sides.

[0028] In one embodiment, the P-type base region has a thickness equal to a sum of a thickness of the source region and a thickness of a horizontal portion of the P-type well region.

[0029] A second aspect of the embodiments of the present application provides a preparation method of an LDMOS power device, comprising:

[0030] Performing etching on the semiconductor substrate so that a front surface of the semiconductor substrate is provided with a plurality of substrate grooves;

[0031] Performing oxidation treatment on the front surface of the semiconductor substrate to form a buried oxygen region; wherein a back surface of the buried oxygen region is provided with a plurality of buried oxygen protruding structures, and the plurality of buried oxygen protruding structures are filled in the plurality of substrate grooves;

[0032] Sequentially forming a P-type well region, a P-type base region and a drift region on a front surface of the buried oxygen region; wherein the P-type well region has an "L" shape, the drift region has an "L" shape, and the P-type base region is in contact with a horizontal portion of the P-type well region, and the drift region is in contact with the P-type well region;

[0033] Forming a source region on the horizontal portion of the P-type well region and forming a drain region on a horizontal portion of the drift region; wherein the source region is in contact with the P-type base region;

[0034] Forming a passivation layer on the source region, the P-type well region and the drift region; wherein the passivation layer has an "L" shape;

[0035] Forming a gate extension region on a horizontal portion of the passivation layer;

[0036] Forming a source electrode on the P-type base region, forming a drain electrode on the drain region, and forming a gate electrode on the horizontal portion of the passivation layer; wherein a vertical portion of the passivation layer is between the gate electrode and the source electrode, and the gate extension region is between the gate electrode and the drain electrode.

[0037] Compared with the prior art, the embodiment of the present application has the beneficial effect that: by arranging multiple substrate grooves opposite to the drift region on the front surface of the semiconductor substrate, and arranging multiple buried oxygen protruding structures matching the substrate grooves on the back surface of the buried oxygen region, more holes are gathered from the multiple substrate grooves, so as to introduce more electric field peaks, enhance the electric field modulation capability of the device near the drain region, and improve the lateral withstand voltage of the LDMOS power device by modulating the surface electric field of the LDMOS power device, thereby solving the problem of small breakdown voltage of the existing LDMOS power device. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application Figure 1 ;

[0039] Figure 2 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application Figure 2 ;

[0040] Figure 3 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application Figure 3 ;

[0041] Figure 4 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application Figure 4 ;

[0042] Figure 5 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application

[0043] Figure 6 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application

[0044] Figure 7 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application

[0045] Figure 8 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application

[0046] Figure 9 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application

[0047] Figure 10 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application

[0048] Figure 11 is a structure schematic diagram of an LDMOS power device provided by an embodiment of the present application DETAILED DESCRIPTION

[0049] In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0050] It should be noted that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or indirectly connected to the other element.

[0051] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0052] In addition, the terms "first", "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is one or more than one, unless otherwise specifically limited.

[0053] With the improvement of the integration of integrated circuits, lateral diffusion metal oxide semiconductor (LDMOSFET) is often applied in the design of high-voltage power integrated circuits due to its outstanding advantages such as high-voltage resistance, large driving current, large output power, and good switching characteristics, especially in high-voltage power amplifier applications. An important parameter of LDMOSFET is its on-resistance. In practical applications, on-resistance is an important parameter closely related to performance, and its size is closely related to the maximum output power of LDMOSFET.

[0054] For high performance power devices, in addition to the need for high breakdown voltage, it is also required to have as low on-resistance as possible. The on-resistance is always reduced with the increase of the drift region doping concentration, while the relationship between the breakdown voltage and the drift region doping concentration is usually more complex. Therefore, we want to optimize the relationship between the breakdown voltage and the on-resistance, to reduce the on-resistance as much as possible under the condition of ensuring a certain breakdown voltage, so as to obtain the maximum output power. Some literatures have studied the on-resistance of the traditional doped LDMOSFET and obtained many achievements, but the contradiction between the on-resistance and the breakdown voltage has not been fundamentally solved. The demand for high performance devices makes the research focus of LDMOSFET become to realize high breakdown voltage and low on-resistance at the same time. The off-state breakdown voltage of LDMOSFET and the on-state on-resistance are inversely proportional to the drift region concentration. The early LDMOSFET has a low breakdown voltage due to the too large drift region concentration. The RESURF LDMOSFET appeared later, which improves the breakdown voltage by reducing the drift region concentration, but reducing the drift region concentration greatly increases the on-resistance.

[0055] Therefore, it can be seen that the existing LDMOS power device cannot balance the breakdown voltage and the on-resistance.

[0056] In order to solve the above technical problems, the embodiment of the present application provides a kind of LDMOS power device, reference Figure 1 As shown in the figure, the LDMOS power device includes: semiconductor substrate 10, buried oxygen region 20, P-type well region 50, P-type base region 70, source region 60, drift region 30, drain region 40, passivation layer 80, source electrode S, gate electrode G, drain electrode D and gate extension region 90.

[0057] Specifically, the buried oxide region 20 is arranged on the front surface of the semiconductor substrate 10. The P-type well region 50 and the P-type base region 70 are both arranged on the front surface of the buried oxide region 20, and the P-type well region 50 has an "L" shape, and the P-type base region 70 is in contact with the horizontal part of the P-type well region 50. The source region 60 is arranged on the horizontal part of the P-type well region 50, and the source region 60 is in contact with the P-type base region 70. The drift region 30 is arranged on the front surface of the buried oxide region 20, and the drift region 30 is in contact with the P-type well region 50; wherein the drift region 30 has an "L" shape, the front surface of the semiconductor substrate 10 is provided with a plurality of substrate grooves opposite to the drift region 30, and the back surface of the buried oxide region 20 is provided with a plurality of buried oxide protruding structures, and the plurality of buried oxide protruding structures are filled in the plurality of substrate grooves. The drain region 40 is arranged on the horizontal part of the drift region 30. The passivation layer 80 is arranged on the source region 60, the P-type well region 50 and the drift region 30; wherein the passivation layer 80 has an "L" shape. The source electrode S is located on the P-type base region 70. The gate electrode G is arranged on the horizontal part of the passivation layer 80; wherein the vertical part of the passivation layer 80 is located between the gate electrode G and the source electrode S. The drain electrode D is in contact with the drain region 40. The gate extension region 90 is arranged on the horizontal part of the passivation layer 80, and the gate extension region 90 is located between the gate electrode G and the drain electrode D.

[0058] In the embodiment, the front surface of the semiconductor substrate 10 is provided with a plurality of substrate grooves opposite to the drift region 30, and the back surface of the buried oxide region 20 is provided with a plurality of buried oxide protruding structures, and the plurality of buried oxide protruding structures are filled in the plurality of substrate grooves. It can be understood that the plurality of substrate grooves are only arranged below the drift region 30, and are arranged opposite to the drift region 30, and the number of the substrate grooves and the buried oxide protruding structures is the same, that is, the plurality of substrate grooves and the plurality of buried oxide protruding structures play a complementary role, and each buried oxide protruding structure is filled in one substrate groove. Because the electric field intensity near the drain region 40 of the LDMOS power device is large and the electric field distribution is dense when the device is working, the breakdown voltage of the device can be improved by arranging the plurality of buried oxide protruding structures and the plurality of substrate grooves, because each substrate groove has two corners at the bottom of the substrate groove, and holes can be gathered at the corners, and the plurality of substrate grooves can gather more holes, and more electric field peaks can be introduced, so the ability to modulate the electric field near the drain region 40 is stronger, and the surface electric field of the LDMOS device can be better modulated, the lateral withstand voltage of the device is improved, and the problem of low breakdown voltage of the existing device is solved.

[0059] In the embodiment, by setting multiple substrate grooves opposite to the drift region 30 on the front surface of the semiconductor substrate 10, and setting multiple buried oxygen protruding structures matching the substrate grooves on the back surface of the buried oxygen region 20, more holes are gathered from the multiple substrate grooves, thereby introducing more electric field peaks, enhancing the device's ability to modulate the electric field near the drain region, and improving the lateral withstand voltage of the LDMOS power device by modulating the surface electric field of the LDMOS power device, thereby solving the problem of small breakdown voltage of the existing LDMOS power device.

[0060] In the embodiment, by filling the buried oxygen protruding structures in the substrate grooves, the thickness of the buried oxygen region 20 near the drain region 40 is larger, thus the equipotential area can be reduced to disperse the equipotential lines, so that the equipotential lines are uniformly distributed, the electric field is uniform, and the electric field near the drain region 40 is weakened, thereby further improving the breakdown voltage of the LDMOS power device.

[0061] In the embodiment, the P-type well region 50, the P-type base region 70, and the drift region 30 are all set on the front surface of the buried oxygen region 20, the P-type well region 50 has an "L" shape with a horizontal part and a vertical part, and the source region 60 is set on the horizontal part of the P-type well region 50. In a specific application embodiment, the upper surface of the source region 60 is flush with the upper surface of the vertical part of the P-type well region 50, and the width of the source region 60 is equal to the width of the horizontal part of the P-type well region 50, at this time, the source region 60 and the P-type well region 50 form a cuboid.

[0062] In the embodiment, the drift region 30 has an "L" shape with a horizontal part and a vertical part, the drain region 40 is set on the horizontal part of the drift region 30, and the upper surface of the drain region 40 is flush with the upper surface of the vertical part of the drift region 30, and the width of the drain region 40 is the same as the width of the horizontal part of the drift region 30, at this time, the drain region 40 and the drift region 30 form a cuboid.

[0063] In the embodiment, the passivation layer 80 has an "L" shape with a horizontal part and a vertical part, the gate electrode G and the gate extension region 90 are both set on the horizontal part of the passivation layer 80, and the gate electrode G is in contact with the vertical part of the passivation layer 80, and the gate extension region 90 is in contact with the gate electrode G; in a specific application embodiment, the upper surfaces of the gate electrode G and the gate extension region 90 are flush with the upper surface of the passivation layer 80, and the sum of the widths of the gate electrode G and the gate extension region 90 is equal to the sum of the widths of the horizontal part of the passivation layer 80. At this time, the gate electrode G, the gate extension region 90, and the passivation layer 80 together form a cuboid. In the embodiment, by setting the gate extension region 90, the gate extension region 90 can form a low-resistance high-concentration electron channel from the drain region 40 to the source region 60 above the drift region 30, thereby reducing the on-resistance of the device.

[0064] In the embodiment, the source electrode S, the drain electrode D and the gate electrode G are located in the same plane, so that the source electrode S, the drain electrode D and the gate electrode G can be formed in one process, simplifying the electrode manufacturing process and reducing the electrode manufacturing cost.

[0065] In the embodiment, the gate extension region 90 is arranged to form a low-resistance high-concentration electron channel from the drain region 40 to the source region 60 above the drift region 30, thereby reducing the on-resistance of the device. The plurality of substrate grooves and the plurality of buried oxygen protruding structures are arranged, and the plurality of buried oxygen protruding structures are filled in the plurality of substrate grooves, so as to reduce the equipotential area, thereby dispersing the equipotential lines and making the equipotential lines uniformly distributed and the electric field uniform, thereby weakening the electric field near the drain region 40, thereby improving the breakdown voltage. The device with reduced on-resistance and improved breakdown voltage solves the problem that the existing LDMOS power device cannot balance the breakdown voltage and the on-resistance.

[0066] In one embodiment, for the material of the buried oxygen region 20, the commonly used material in the mature process is silicon oxide, and a low-K dielectric with a dielectric coefficient lower than that of silicon oxide can also be used to reduce the thickness of the buried oxygen region 20.

[0067] In one embodiment, referring to Figure 2 As shown in the figure, the gate extension region 90 includes a first P-type doped region 91, a second P-type doped region 92, a first N-type doped region 93 and a third P-type doped region 94.

[0068] Specifically, the first P-type doped region 91 is arranged on the horizontal part of the passivation layer 80, and the first P-type doped region 91 is in contact with the gate electrode G. The second P-type doped region 92 is arranged on the horizontal part of the passivation layer 80, and the second P-type doped region 92 is in contact with the first P-type doped region 91. The first N-type doped region 93 is arranged on the horizontal part of the passivation layer 80, and the first N-type doped region 93 is in contact with the second P-type doped region 92. The third P-type doped region 94 is arranged on the horizontal part of the passivation layer 80, and the third P-type doped region 94 is in contact with the first N-type doped region 93.

[0069] In the embodiment, the first P-type doped region 91 and the second P-type doped region 92 are doped with P-type doped ions, and the doping concentration of the first P-type doped region 91 is greater than that of the second P-type doped region 92, the first N-type doped region 93 can be doped with N-type doped ions, for example, the N-type doped ions can be nitrogen ions or phosphorus ions, the third P-type doped region 94 can be doped with P-type doped ions, for example, the P-type doped ions can be aluminum ions, by doping different elements, the first N-type doped region 93 and the third P-type doped region 94 form a PN junction, which can enhance the electric field above the passivation layer 80, thereby forming a low-resistance electron channel above the drift region 30, reducing the on-resistance.

[0070] In one embodiment, the doping ions of the second P-type doped region 92 are the same as those of the first P-type doped region 91, but the doping concentration is different, and the doping ions of the first N-type doped region 93 are different, which can avoid the adverse effect of the second P-type doped region 92 on the longitudinal electric field intensity of the drift region 30 after depletion in the device off-state voltage withstand state, and can improve the voltage withstand capability of the device.

[0071] In one embodiment, referring to Figure 3 As shown, the depth of the substrate recess gradually increases from the source region 60 to the drain region 40.

[0072] In the embodiment, because the electric field intensity near the drain region 40 of the LDMOS power device is large and the electric field distribution is dense when the device is working, by setting the depth of the substrate recess gradually increasing from the source region 60 to the drain region 40, for example, H1

[0073] It should be noted that when the depth of the substrate recess gradually increases from the source region 60 to the drain region 40, the depth of the buried oxygen protruding structure also gradually increases from the source region 60 to the drain region 40, because the buried oxygen protruding structure is used to fill the substrate recess, and the buried oxygen region 20 near the drain region 40 is set to be thicker, which can make the buried oxygen region 20 bear a larger electric field intensity, and can further improve the ability of the device to withstand the breakdown voltage.

[0074] In one embodiment, referring to Figure 2 As shown, the width of the adjacent substrate recess gradually decreases from the source region 60 to the drain region 40.

[0075] In the embodiment, because the electric field intensity near the drain region 40 of the LDMOS power device is large and the electric field distribution is dense when the LDMOS power device is working, the width of the adjacent substrate grooves is gradually reduced from the source region 60 to the drain region 40, for example, W1>W2, wherein W1 is the depth of the substrate groove near the source region 60, and W2 is the depth of the substrate groove away from the source region 60. In this way, more substrate grooves can be arranged under the drain region 40 because the holes can be gathered at the corners of the substrate grooves. More substrate grooves arranged under the drain region 40 can introduce more electric field peaks, and the ability to modulate the electric field near the drain region 40 is stronger, which can better modulate the surface electric field of the LDMOS device and improve the lateral withstand voltage of the device, solving the problem of low breakdown voltage of the existing device.

[0076] In a specific application embodiment, the distance between the adjacent substrate grooves is equal. By arranging the distance between the adjacent substrate grooves to be equal, the substrate grooves can be more evenly distributed, the surface electric field of the LDMOS device can be better modulated, the lateral withstand voltage of the device can be improved, and the problem of low breakdown voltage of the existing device can be solved.

[0077] In an embodiment, the doping concentration of the first P-type doped region 91 is greater than the doping concentration of the second P-type doped region 92.

[0078] In the embodiment, the doping concentration of the second P-type doped region 92 is less than the doping concentration of the first P-type doped region 91. By arranging the width of the first P-type doped region 91 to be less than the width of the second P-type doped region 92, more low-resistance electron channels can be formed above the drift region 30, the on-resistance is reduced, and the on-resistance of the device is further reduced.

[0079] In an embodiment, the width of the second P-type doped region 92 is greater than the width of the first P-type doped region 91.

[0080] In the embodiment, the doping concentration of the second P-type doped region 92 is less than the doping concentration of the first P-type doped region 91. By arranging the width of the first P-type doped region 91 to be less than the width of the second P-type doped region 92, more low-resistance electron channels can be formed above the drift region 30, the on-resistance is reduced, and the on-resistance of the device is further reduced.

[0081] In an embodiment, as shown in FIG. 1, Figure 3 The LDMOS power device further comprises a plurality of shallow trench isolation regions 100.

[0082] Specifically, the plurality of shallow trench isolation regions 100 are arranged in the second P-type doped region 92. The plurality of shallow trench isolation regions 100 gradually increase in depth from the source region 60 to the drain region 40. Specifically, the shallow trench isolation region 100 close to the source region 60 has a smaller depth than the shallow trench isolation region 100 close to the drain region 40. The plurality of shallow trench isolation regions 100 are formed by depositing, patterning, and etching silicon through a silicon nitride mask, and then filling the trench with deposited oxide. By arranging the plurality of shallow trench isolation regions 100 in the second P-type doped region 92, a high electric field can be formed at the plurality of shallow trench isolation regions 100, the electric field distribution of the LDMOS power device can be modulated, and the breakdown voltage of the LDMOS power device can be improved.

[0083] In one embodiment, the passivation layer 80 uses a high-K dielectric. By using a high-K dielectric, the concentration of the electron channel formed above the drift region 30 can be increased, and the resistance can be reduced. In this way, the on-resistance of the LDMOS power device can be reduced.

[0084] In one embodiment, the doping concentration of the drift region 30 gradually decreases from the central region to the left and right sides.

[0085] In this embodiment, the middle region of the drift region 30 has a larger doping concentration, and the drift region 30 close to the drain region 40 and the P-type well region 50 has a smaller doping concentration. Since the electric field strength near the drain region 40 is larger, the doping concentration of the drift region 30 close to the drain region 40 is set to be smaller, which can appropriately increase the breakdown voltage of the device. The doping concentration of the drift region 30 close to the P-type well region 50 is smaller, which can appropriately weaken the electron channel induced by the gate electrode G in the drift region 30, thereby improving the threshold voltage.

[0086] In one embodiment, referring to Figure 4 As shown, the drift region 30 includes a first drift unit 31, a second drift unit 32, and a third drift unit 33.

[0087] Specifically, the first drift unit 31 has an "L" shape, and the drain region 40 is arranged on the horizontal part of the first drift unit 31. The second drift unit 32 is in contact with the first drift unit 31. The third drift unit 33 is in contact with the second drift unit 32, and the third drift unit 33 is in contact with the P-type well region 50. The doping concentration of the first drift unit 31 is smaller than the doping concentration of the second drift unit 32, and the doping concentration of the third drift unit 33 is smaller than the doping concentration of the second drift unit 32.

[0088] In the embodiment, the drift region 30 can be doped with N-type doping ions, and the performance of the device can be improved by using different doping concentrations for the drift region 30. For example, the doping concentration of the first drift unit 31 is set to be less than the doping concentration of the second drift unit 32. Since the first drift unit 31 is closer to the drain region 40, the electric field intensity near the drain region 40 is larger. By setting the doping concentration of the first drift unit 31 to be smaller, the electric field intensity near the drain region 40 can be reduced, and the breakdown voltage of the device can be improved. The doping concentration of the third drift unit 33 is set to be less than the doping concentration of the second drift unit 32. Since the third drift unit 33 is closer to the source region 60, the voltage required by the source region 60 is generally larger. By setting the doping concentration of the third drift unit 33 to be smaller, the electron channel induced by the gate electrode G in the drift region 30 can be appropriately weakened, so as to improve the threshold voltage and improve the performance of the device.

[0089] In one embodiment, referring to FIG. 1, the doping concentration of the first drift unit 31 is equal to the doping concentration of the third drift unit 33. Figure 4

[0090] In the embodiment, the doping concentration of the first drift unit 31 is equal to the doping concentration of the third drift unit 33, and both are less than the doping concentration of the second drift unit 32. In this way, not only can the electric field intensity near the drain region 40 be reduced and the breakdown voltage of the device be improved, but also the voltage of the source region 60 can be improved, thereby improving the overall performance of the device.

[0091] In one embodiment, the thickness of the P-type base region 70 is equal to the sum of the thickness of the source region 60 and the thickness of the horizontal part of the P-type well region 50.

[0092] In the embodiment, the thickness of the P-type base region 70 is greater than the thickness of the source region 60. Since the P-type base region 70 is the voltage access point of the LDMOS power device, by setting the thickness of the P-type base region 70 to be the sum of the thickness of the source region 60 and the thickness of the horizontal part of the P-type well region 50, the voltage can be better accessed, the stability of the LDMOS power device can be maintained, and the performance of the LDMOS power device can be improved.

[0093] In one embodiment, the semiconductor substrate 10 is oxidized to different degrees to form a plurality of substrate grooves and a plurality of buried oxygen protruding structures. The plurality of buried oxygen protruding structures are filled in the plurality of substrate grooves to increase the area of the buried oxygen region 20, thereby dispersing the potential lines and making the equipotential lines uniformly distributed. The electric field inside the drift region 30 is uniformly distributed, the electric field of the drain is avoided to be concentrated, and the breakdown voltage of the device is improved.

[0094] In one embodiment, the width of the gate electrode G is greater than the width of the vertical part of the P-type well region 50.

[0095] ​In this embodiment, the gate electrode G is made of a metal material, such as copper, gold, or silver. By setting the width of the gate electrode G to be greater than the width of the vertical portion of the P-type well region 50, a high-concentration electron channel can be induced in the drift region 30 when the device is working, thereby reducing the on-resistance of the device.

[0096] In one embodiment, the buried oxide region 20 can be silicon oxide.

[0097] In one embodiment, the gate electrode G can be at least one of copper, gold, and silver.

[0098] In one embodiment, the drain electrode D can be at least one of copper, gold, and silver.

[0099] In one embodiment, the source electrode S can be at least one of copper, gold, and silver.

[0100] In one embodiment, the source region 60 and the drain region 40 can be used as pad materials for the corresponding electrodes, such as gallium nitride materials, or metal material layers.

[0101] This application also provides a method for fabricating an LDMOS power device, see reference. Figure 5 As shown, it includes steps S10 to S70.

[0102] Step S10: Reference Figure 6 As shown, etching is performed on the semiconductor substrate 10 to provide a plurality of substrate grooves on the front side of the semiconductor substrate 10.

[0103] In one specific application, selective etching is performed on the semiconductor substrate 10 to etch multiple substrate grooves on the front side of the semiconductor substrate 10. In this embodiment, the semiconductor substrate 10 can be an N-type silicon substrate, and in specific applications, the thickness of the semiconductor substrate 10 can be set according to the application requirements of the device.

[0104] Step S20: An oxidation process is performed on the front side of the semiconductor substrate 10 to form a buried oxide region 20, as shown in the reference. Figure 7 As shown; wherein, the back side of the buried oxide region 20 is provided with multiple buried oxide protrusion structures, and the multiple buried oxide protrusion structures fill multiple substrate grooves.

[0105] In a specific application, the method for forming a buried oxide region 20 on a semiconductor substrate 10 is as follows: oxygen is injected into the semiconductor substrate 10 to oxidize the semiconductor substrate 10. The shape of the buried oxide region 20 can be determined by controlling the amount of oxygen injected. In this embodiment, a plurality of buried oxide protrusion structures are provided on the back side of the buried oxide region 20, and the plurality of buried oxide protrusion structures fill a plurality of substrate grooves.

[0106] Step S30: Forming P-type well region 50, P-type base region 70 and drift region 30 on the front surface of buried oxide region 20 in sequence, as shown in FIG. 3; wherein P-type well region 50 is in the shape of "L", drift region 30 is in the shape of "L", and P-type base region 70 is in contact with the horizontal part of P-type well region 50, and drift region 30 is in contact with P-type well region 50. Figure 8

[0107] In one specific application, P-type well region 50, P-type base region 70 and drift region 30 can be formed on the preset region of buried oxide region 20 by depositing semiconductor material or metal material.

[0108] In one embodiment, P-type well region 50, P-type base region 70 and drift region 30 are etched respectively by selective etching of buried oxide region 20, and then corresponding ion material is deposited to form the corresponding region, for example, N-type ion is deposited to form drift region 30, and P-type ion is deposited to form P-type well region 50 and P-type base region 70.

[0109] Step S40: Forming source region 60 on the horizontal part of P-type well region 50, and forming drain region 40 on the horizontal part of drift region 30, as shown in FIG. 4; wherein source region 60 is in contact with P-type base region 70. Figure 9

[0110] In one specific application, N-type ion is deposited on the horizontal part of P-type well region 50 to form source region 60, and N-type ion is deposited on the horizontal part of drift region 30 to form drain region 40, and drain region 40 and source region 60 are heavily doped with N-type ion.

[0111] Step S50: Forming passivation layer 80 on source region 60, P-type well region 50 and drift region 30, as shown in FIG. 5; wherein passivation layer 80 is in the shape of "L". Figure 10

[0112] In this embodiment, selective etching is performed on source region 60, P-type well region 50 and drift region 30 to form passivation layer 80, and selective etching is performed on passivation layer 80 to make passivation layer 80 in the shape of "L".

[0113] In one embodiment, the material used by passivation layer 80 is high-K dielectric, and by using high-K dielectric, the concentration of the electron channel formed above drift region 30 can be greater, and the resistance can be smaller, so that the on-resistance of LDMOS power device can be reduced better.

[0114] Step S60: Forming gate extension region 90 on the horizontal part of passivation layer 80, as shown in FIG. 6. Figure 11 ​​​​

[0115] In the embodiment, the trench of the gate extension region 90 can be formed by etching on the passivation layer 80, and then P-type ions are doped in the trench to form the gate extension region 90.

[0116] Step S70: forming the source electrode S on the P-type base region 70, forming the drain electrode D on the drain region 40, and forming the gate electrode G on the horizontal part of the passivation layer 80, as shown in FIG. 7; wherein the vertical part of the passivation layer 80 is between the gate electrode G and the source electrode S, and the gate extension region 90 is between the gate electrode G and the drain electrode D. Figure 11

[0117] In one specific application, the shapes of the source electrode S, the gate electrode G and the drain electrode D are determined by a mask, and the source electrode S, the gate electrode G and the drain electrode D are formed by depositing metal on the mask.

[0118] In the embodiment, the shapes of the source electrode S, the gate electrode G and the drain electrode D are defined by a mask, so that the source electrode S, the gate electrode G and the drain electrode D are formed by depositing metal material on the mask, and then the mask is removed.

[0119] In the embodiment, more holes are gathered by setting multiple substrate grooves opposite to the drift region 30 on the front surface of the semiconductor substrate 10, and multiple buried oxygen protruding structures matching the substrate grooves are set on the back surface of the buried oxygen region 20, so that more electric field peaks are introduced, the ability of the device to modulate the electric field near the drain region is enhanced, the surface electric field of the LDMOS power device is modulated, the lateral withstand voltage of the LDMOS power device is improved, and the problem that the existing LDMOS power device cannot balance the breakdown voltage and the on-resistance is solved.

[0120] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0121] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.​

Claims

1. An LDMOS power device, characterized in that, The LDMOS power device includes: Semiconductor substrate; The buried oxide region is located on the front side of the semiconductor substrate; P-type well region and P-type base region, both of which are located on the front side of the buried oxygen region, and the P-type well region is L-shaped, with the P-type base region in contact with the horizontal portion of the P-type well region; The source region is located on the horizontal portion of the P-type well region and is in contact with the P-type base region; A drift region is located on the front side of the buried oxide region and contacts the P-type well region; wherein the drift region is "L"-shaped, the front side of the semiconductor substrate has multiple substrate grooves opposite to the drift region, and the back side of the buried oxide region has multiple buried oxide bump structures, the multiple buried oxide bump structures filling the multiple substrate grooves; the multiple substrate grooves and the multiple buried oxide bump structures are complementary; each substrate groove has two corners at its bottom, the corners being used to collect holes; The drain region is located on the horizontal portion of the drift region; A passivation layer is disposed on the source region, the P-type well region, and the drift region; wherein the passivation layer is L-shaped. The source electrode is located on the P-type base region; A gate electrode is disposed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is located between the gate electrode and the source electrode; The drain electrode is in contact with the drain region; A gate extension region is disposed on the horizontal portion of the passivation layer and located between the gate electrode and the drain electrode. The sum of the widths of the gate electrode and the gate extension region is equal to the sum of the widths of the horizontal portion of the passivation layer. The gate extension region forms an electron channel from the drain region to the source region above the drift region.

2. The LDMOS power device as described in claim 1, characterized in that, The gate extension region includes: A first P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the gate electrode; The second P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the first P-type doped region; The first N-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the second P-type doped region; The third P-type doped region is located on the horizontal portion of the passivation layer and is in contact with the first N-type doped region.

3. The LDMOS power device as described in claim 1, characterized in that, The depth of the substrate groove gradually increases from the source region to the drain region.

4. The LDMOS power device according to any one of claims 1-3, characterized in that, The width of the adjacent substrate grooves gradually decreases from the source region to the drain region.

5. The LDMOS power device according to any one of claims 1-3, characterized in that, The distance between adjacent substrate grooves is equal.

6. The LDMOS power device as described in claim 2, characterized in that, The doping concentration of the first P-type doped region is greater than that of the second P-type doped region.

7. The LDMOS power device as described in claim 2, characterized in that, The width of the second P-type doped region is greater than the width of the first P-type doped region.

8. The LDMOS power device as described in claim 1, characterized in that, The doping concentration in the drift region gradually decreases from the central region to the left and right sides.

9. The LDMOS power device as described in claim 1, characterized in that, The thickness of the P-type base region is equal to the sum of the thickness of the source region and the thickness of the horizontal portion of the P-type well region.

10. A method for fabricating an LDMOS power device, characterized in that, include: Etching is performed on the semiconductor substrate to create multiple substrate grooves on the front side of the semiconductor substrate; An oxide layer is formed on the front side of the semiconductor substrate by oxidation treatment; wherein, a plurality of buried oxide bump structures are provided on the back side of the buried oxide region, and the plurality of buried oxide bump structures fill the plurality of substrate grooves; the plurality of substrate grooves and the plurality of buried oxide bump structures are complementary; each substrate groove has two corners at the bottom, and the corners are used to collect holes; A P-type well region, a P-type base region, and a drift region are sequentially formed on the front side of the buried oxygen region; wherein, the P-type well region is L-shaped, the drift region is L-shaped, and the P-type base region is in contact with the horizontal portion of the P-type well region, and the drift region is in contact with the P-type well region. A source region is formed on the horizontal portion of the P-type well region, and a drain region is formed on the horizontal portion of the drift region; wherein the source region is in contact with the P-type base region; A passivation layer is formed on the source region, the P-type well region, and the drift region; wherein the passivation layer is L-shaped. A gate extension region is formed on the horizontal portion of the passivation layer; A source electrode is formed on the P-type base region, a drain electrode is formed on the drain region, and a gate electrode is formed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is located between the gate electrode and the source electrode, the gate extension region is located between the gate electrode and the drain electrode, and the sum of the widths of the gate electrode and the gate extension region is equal to the sum of the widths of the horizontal portion of the passivation layer; the gate extension region forms an electron channel from the drain region to the source region above the drift region.

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