A field effect transistor and a method of manufacturing the same
By employing an embedded gate structure and a vertical channel design in the field-effect transistor, the problem of deteriorated electronic control effect of the gate structure in the channel region is solved, and better threshold characteristics and stability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2022-10-31
- Publication Date
- 2026-07-24
Smart Images
Figure CN115528116B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a field-effect transistor and its fabrication method. Background Technology
[0002] With the continuous development of semiconductor technology, the size of field-effect transistors (FETs) is constantly decreasing. Existing FETs mainly include: a substrate, a gate structure on the substrate, and drain and source regions located on either side of the gate structure within the substrate. The substrate between the drain and source regions forms a channel region. As the size of the FET decreases, the size and thickness of the source, drain, gate structure, and channel regions also decrease proportionally. This leads to a deterioration in the gate structure's control over electrons within the channel region, resulting in enhanced short-channel effects and deteriorated threshold characteristics in the FET. Summary of the Invention
[0003] The purpose of this invention is to provide a field-effect transistor to solve the problem that the gate structure of existing field-effect transistors results in poor electronic control performance in the channel region.
[0004] To achieve the above objectives, the present invention provides a field-effect transistor, comprising:
[0005] Substrate;
[0006] A first aluminum gallium nitride layer is located on the substrate;
[0007] A first gate is located on the first aluminum gallium nitride layer and extends along a first direction;
[0008] The second gate is located on both sides of the first gate;
[0009] A second aluminum gallium nitride layer is located on the first aluminum gallium nitride layer and extends in the first direction. The second aluminum gallium nitride layer covers the first gate and extends to cover a portion of the width of the first aluminum gallium nitride layer and the second gate along the second direction. The first direction is perpendicular to the second direction.
[0010] The source and drain regions are located within the first aluminum gallium nitride layer on the side of the second gate away from the first gate and within the second aluminum gallium nitride layer above the second gate, respectively.
[0011] Optionally, the second gate includes a first portion and a second portion, the second aluminum gallium nitride layer covers the first portion, and the width of the second portion along the first direction is greater than the width of the first portion along the first direction.
[0012] Optional, also includes:
[0013] The first gate oxide layer is located between the first gate structure and the first aluminum gallium nitride layer and the second aluminum gallium nitride layer;
[0014] The second gate oxide layer is located between the second gate and the first aluminum gallium nitride layer and the second aluminum gallium nitride layer.
[0015] Optionally, the materials of the first gate oxide layer and the second gate oxide layer include hafnium dioxide.
[0016] Optional, also includes:
[0017] A gallium nitride layer is located between the substrate and the first aluminum gallium nitride layer, and covers the substrate.
[0018] Optional, also includes:
[0019] A dielectric layer covering the first aluminum gallium nitride layer, the second gate, and the second aluminum gallium nitride layer;
[0020] Several plugs are located within the dielectric layer and are electrically connected to the first gate, the second gate, and the source / drain regions, respectively.
[0021] Based on the same inventive concept, the present invention also provides a method for fabricating a field-effect transistor, comprising:
[0022] Provide substrate;
[0023] A first aluminum gallium nitride layer is formed, which covers the substrate;
[0024] A first gate, a second gate, and a second aluminum gallium nitride layer are formed. The first gate covers a portion of the first aluminum gallium nitride layer and extends along a first direction. The second gate is located on both sides of the first gate. The second aluminum gallium nitride layer is located on the first aluminum gallium nitride layer and extends along the first direction. The second aluminum gallium nitride layer covers the first gate and extends to cover a portion of the first aluminum gallium nitride layer and a portion of the width of the second gate along a second direction. The first direction is perpendicular to the second direction.
[0025] Source and drain regions are formed, which are located in the first aluminum gallium nitride layer on the side of the second gate away from the first gate and in the second aluminum gallium nitride layer above the second gate, respectively.
[0026] Optionally, after forming the first aluminum gallium nitride layer, the step of forming the second gate includes:
[0027] A third aluminum gallium nitride layer is formed on the first aluminum gallium nitride layer, and the third aluminum gallium nitride layer covers the first aluminum gallium nitride layer;
[0028] Etching removes a portion of the third aluminum gallium nitride to form a plurality of first openings, the first openings being distributed along the first direction and exposing the first aluminum gallium nitride layer;
[0029] A first gate oxide layer, a first gate material layer, a second gate oxide layer, and a fourth aluminum gallium nitride layer are sequentially formed in the first opening. The first gate oxide layer covers a portion of the height and bottom surface of the sidewall of the first opening. The first gate material layer fills a portion of the first opening. The second gate oxide layer covers the top surface of the first portion. The fourth aluminum gallium nitride layer covers the second gate oxide layer, and the top surface of the fourth aluminum gallium nitride layer is flush with the top surface of the third aluminum gallium nitride layer.
[0030] A portion of the fourth aluminum gallium nitride layer, the second gate oxide layer, the first gate material layer, and the first gate oxide layer are removed to form a second opening exposing the first aluminum gallium nitride layer. The second opening extends along the first direction to penetrate a plurality of the first openings, and the remaining first gate material constitutes a first portion of the second gate.
[0031] A first oxide layer and a second gate material layer are formed in the second opening. The first oxide layer covers the first aluminum gallium nitride layer, and the second gate material layer covers the sidewall of the first portion to form the second portion of the second gate.
[0032] The second oxide layer is formed, and the second oxide layer fills the second opening.
[0033] Optionally, after forming the second portion and before forming the second oxide layer, the method further includes:
[0034] An ion implantation process is performed on the first aluminum gallium nitride layer inside the second opening and the fourth aluminum gallium nitride layer above the first portion to form source / drain regions in the first aluminum gallium nitride layer on both sides of the second portion and the fourth aluminum gallium nitride layer above the first portion.
[0035] Optionally, after forming the third oxide layer, the step of forming the first gate includes:
[0036] The third aluminum gallium nitride layer between the second gates is etched to form the third opening that exposes the first aluminum gallium nitride layer, and the third opening extends along the first direction;
[0037] A third gate oxide layer, a third gate material layer, and a fourth gate oxide layer are formed within the third opening. The third gate oxide layer covers a portion of the height of the sidewall and the bottom surface of the third opening. The third gate material layer fills a portion of the third opening to form the first gate. The fourth gate oxide layer covers the first gate.
[0038] The fifth aluminum gallium nitride layer is formed to fill the third opening.
[0039] In the field-effect transistor provided by this invention, a first gate extends along a first direction, a second gate is located on both sides of the first gate, a second aluminum gallium nitride layer extends along the first direction and covers the first gate and part of the second gate, and the source and drain regions are respectively located in the first aluminum gallium nitride layer outside the second gate away from the first gate and in the second aluminum gallium nitride layer on the top surface of the second gate. The channel region of the field-effect transistor provided by this invention is the second aluminum gallium nitride layer and the first aluminum gallium nitride layer between the first gate and the second gate. This transforms the horizontal channel region in the existing field-effect transistor into the vertical channel region, increases the size of the channel region, and effectively reduces the impact of semiconductor device miniaturization on the channel region size. At the same time, the second aluminum gallium nitride layer covers part of the second gate, and the dielectric layer covers the remaining second gate, so that the second gate is partially embedded in the second aluminum gallium nitride layer, forming an embedded gate structure, thereby effectively strengthening the control of the second gate over electrons in the channel region, and giving the field-effect transistor better threshold characteristics and stability. Attached Figure Description
[0040] Figure 1 A flowchart of a method for fabricating a field-effect transistor is provided for embodiments of the present invention;
[0041] Figures 2-27 The diagram shows the corresponding structural steps of the fabrication method of the field-effect transistor provided in the embodiments of the present invention. Figure 26 A schematic diagram of the structure of a field-effect transistor provided in an embodiment of the present invention;
[0042] The attached figures are labeled as follows:
[0043] y - first direction; x - second direction;
[0044] 100 - Substrate; 101 - Gallium nitride layer; 102 - Second aluminum gallium nitride layer; 103 - Sacrificial layer; 104 - Hard mask layer; 105 - First aluminum gallium nitride layer; 106 - Third aluminum gallium nitride layer; 107 - First opening; 108 - First gate oxide layer; 109 - First gate material layer; 110 - Second gate oxide layer; 111 - Fourth aluminum gallium nitride layer; 112 - Fourth oxide layer; 113 - First portion; 11 4-Second gate oxide layer; 115-Second opening; 116-First oxide layer; 117-Second gate material layer; 118-Second portion; 119-Second oxide layer; 120-Third opening; 121-Third gate oxide material layer; 122-First gate; 123-Fourth gate oxide material layer; 124-First gate oxide layer; 125-Fifth aluminum gallium nitride layer; 126-Third oxide layer; 127-Plug; 128-Dielectric layer. Detailed Implementation
[0045] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0046] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the steps presented herein are not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described in the text may be added to the method.
[0047] Figure 26 This is a schematic diagram of the field-effect transistor provided in this embodiment, as shown below. Figure 26 As shown, the field-effect transistor includes: a substrate 100, a first aluminum gallium nitride layer 105, a second aluminum gallium nitride layer 102, a first gate 122, a second gate, and source / drain regions.
[0048] Specifically, the first aluminum gallium nitride layer 105 covers the substrate 100, the first gate 122 is located on the first aluminum gallium nitride layer 105, the first gate 122 covers a portion of the first aluminum gallium nitride layer 105 and extends along a first direction y, a plurality of second gates are located on both sides of the first gate 122 and distributed along the first direction y; the second aluminum gallium nitride layer 102 is located on the first aluminum gallium nitride layer 105 and extends along the first direction y, the second aluminum gallium nitride layer 102 covers the first gate 122 and extends to cover a portion of the first aluminum gallium nitride layer 105 and a portion of the width of the second gate along a second direction x, wherein the first direction y is perpendicular to the second direction x; the source and drain regions are respectively located in the first aluminum gallium nitride layer 105 on the side of the second gate away from the first gate 122 and in the second aluminum gallium nitride layer 102 above the second gate.
[0049] In the field-effect transistor provided in this embodiment, the channel region is the second aluminum gallium nitride layer 102 and the first aluminum gallium nitride layer 105 between the first gate 122 and the second gate. This transforms the horizontal channel region in the existing field-effect transistor into the vertical channel region, increases the size of the channel region, and effectively reduces the impact of semiconductor device miniaturization on the channel region size.
[0050] Furthermore, the field-effect transistor provided in this embodiment also includes a dielectric layer 128 and a plurality of plugs 127. The dielectric layer 128 covers the first aluminum gallium nitride layer 105, the second gate, and the second aluminum gallium nitride layer 102, and a portion of the dielectric layer 128 is located between the second gate and the first aluminum gallium nitride layer 105 to isolate the substrate 100 and the second gate; the plugs 127 are located within the dielectric layer 128 and are electrically connected to the first gate 122, the second gate, and the source / drain regions, respectively. The first gate 122 can enhance the control of the first gate 122 and the second gate over the electrons in the channel region, providing better threshold characteristics and stability for the field-effect transistor.
[0051] Figure 27 for Figure 26 A schematic diagram of the cross-sectional structure along line A to A1, as shown below. Figure 27 As shown, the second gate includes a first portion 113 and a second portion 118. The second aluminum gallium nitride layer 102 covers the first portion 113, and the dielectric layer 128 covers the second portion 118. The width of the second portion 118 along the first direction y is greater than the width of the first portion 113 along the first direction y. The first portion 113 is embedded within the second aluminum gallium nitride layer 102, forming an embedded gate structure, which further enhances the control of the second gate over electrons in the channel region, thereby improving the performance of the field-effect transistor.
[0052] Wherein, the width L3 of the first portion 113 along the first direction y is 0.15 to 1.5 nm, and the width L4 of the second portion 118 along the first direction y is 3 to 28 nm. Increasing the width of the second portion 118 along the first direction y can increase the size of the channel region in the first direction y, thereby enhancing the control capability of the second gate over electrons in the channel region.
[0053] Furthermore, the width L2 of the second aluminum gallium nitride layer 102 between the second portion 118 and the first gate 122 along the second direction x is 2.4 to 32 nm, and the width L1 of the second aluminum gallium nitride layer 102 between the first portion 113 and the first gate 122 along the second direction x is 0.7 to 8 nm, so as to ensure the size of the channel region.
[0054] The field-effect transistor provided in this embodiment further includes: a gallium nitride layer 101, a first gate oxide layer 124, and a second gate oxide layer 114.
[0055] The gallium nitride layer 101 is located between the substrate 100 and the first aluminum gallium nitride layer 105, and covers the substrate 100. The material of the gallium nitride layer 101 is gallium nitride, which has a larger electronic band gap, can effectively reduce source-drain leakage current of the device, and provide a more stable threshold swing and lower switching losses.
[0056] The first gate oxide layer 124 is located between the first gate structure 122 and the first aluminum gallium nitride layer 105 and the second aluminum gallium nitride layer 102; the second gate oxide layer 114 is located between the second gate and the first aluminum gallium nitride layer 105 and the second aluminum gallium nitride layer 102. The materials of the first gate oxide layer 124 and the second gate oxide layer 114 include hafnium dioxide. Hafnium dioxide is a high dielectric constant ceramic material, which can effectively solve the size limitation problem of traditional gate oxide materials (silicon oxide), and is beneficial to the miniaturization of semiconductor devices.
[0057] Based on this, this embodiment also provides a method for fabricating a field-effect transistor. Figure 1 This is a flowchart of the fabrication method of the field-effect transistor. Figure 1 As shown, the fabrication method of the field-effect transistor includes:
[0058] Step S1: Provide a substrate;
[0059] Step S2: Form a first aluminum gallium nitride layer, the first aluminum gallium nitride layer covering the substrate;
[0060] Step S3: Form a first gate, a second gate, and a second aluminum gallium nitride layer. The first gate covers a portion of the first aluminum gallium nitride layer and extends along a first direction. The second gate is located on both sides of the first gate. The second aluminum gallium nitride layer is located on the first aluminum gallium nitride layer and extends along the first direction. The second aluminum gallium nitride layer covers the first gate and extends to cover a portion of the first aluminum gallium nitride layer and a portion of the width of the second gate along a second direction. The first direction is perpendicular to the second direction.
[0061] Step S4: Form source and drain regions, which are respectively located in the first aluminum gallium nitride layer on the side of the second gate away from the first gate and in the second aluminum gallium nitride layer above the second gate.
[0062] Figures 2-27 This is a schematic diagram of the corresponding steps in the fabrication method of the field-effect transistor provided in this embodiment. Next, we will combine... Figures 2-27 The fabrication method of the field-effect transistor is described in detail.
[0063] like Figure 2 As shown, a substrate 100 is provided, on which an epitaxial layer (not shown) and a gallium nitride layer 101 are formed. The epitaxial layer covers the substrate 100, and the gallium nitride layer 101 covers the epitaxial layer. The gallium nitride layer 101 can increase the electron band gap and reduce leakage current.
[0064] Furthermore, a first aluminum gallium nitride layer 105 of a certain thickness is formed on the gallium nitride layer 101, and then a third aluminum gallium nitride layer 106 is formed on the first aluminum gallium nitride layer 105 using the same process. The thickness of the third aluminum gallium nitride layer 106 is greater than the thickness of the first aluminum gallium nitride layer 105.
[0065] like Figure 3 As shown, a sacrificial layer 103 is formed on the third aluminum gallium nitride layer 106, and the sacrificial layer 103 covers a portion of the third aluminum gallium nitride layer 106. Figure 4 for Figure 3 The top view of the structure shown is as follows: Figure 4 As shown, the sacrificial layer 103 extends along the first direction y.
[0066] like Figure 5 As shown, a hard mask layer 104 is formed on the third aluminum gallium nitride layer 106, and the hard mask layer 104 covers a portion of the third aluminum gallium nitride layer 106. Figure 6 for Figure 5 The top view of the structure shown is as follows: Figure 6As shown, the hard mask layer 104 has a plurality of first openings 107 that expose the third aluminum gallium nitride layer 106. The first openings 107 are located on both sides of the sacrificial layer 103, and the plurality of first openings 107 are distributed along the first direction y.
[0067] like Figure 7 As shown, the third aluminum gallium nitride layer 106 is etched to deepen the first opening 107 until the first aluminum gallium nitride layer 105 is exposed.
[0068] like Figure 8 and Figure 9 As shown, a first gate oxide layer 108 and a first gate material layer 109 are formed in the first opening 107. The first gate oxide layer 108 covers the inner wall of the first opening 107 and extends to cover the hard mask layer 104 and the sacrificial layer 103. The first gate material layer 109 is located on the first gate oxide layer 108 and fills the first opening 107.
[0069] Furthermore, such as Figure 10 As shown, after removing a portion of the thickness of the first gate material layer 109, the top surface of the remaining first gate material layer 109 is lower than the top surface of the third aluminum gallium nitride layer 106; then a second gate oxide layer 110 is formed, which covers the top surface of the first gate material layer 109 and the first gate oxide layer 108, and the top surface of the second gate oxide layer 110 is also lower than the top surface of the third aluminum gallium nitride layer 106.
[0070] like Figure 11 As shown, after removing a portion of the first gate oxide layer 108 and the second gate oxide layer 110, the remaining second gate oxide layer 110 covers the top surface of the first gate oxide layer 109, and the remaining first gate oxide layer 108 is located between the first gate oxide layer 109 and the first aluminum gallium nitride layer 105 and the third aluminum gallium nitride layer 106, that is, the first gate oxide layer 108 covers the bottom surface and part of the sidewall of the first opening 107.
[0071] like Figure 12 As shown, a fourth aluminum gallium nitride layer 111 is formed, which covers the second gate oxide material layer 110, and the top surface of the fourth aluminum gallium nitride layer 111 is flush with the top surface of the third aluminum gallium nitride layer 106.
[0072] like Figures 12-13 As shown, the hard mask layer 104 is removed, and then a fourth oxide layer 112 is formed, which covers the exposed fourth aluminum gallium nitride layer 111 and the third aluminum gallium nitride layer 106.
[0073] like Figure 14 As shown, the fourth oxide layer 112, the fourth aluminum gallium nitride layer 111, the second gate oxide layer 110, the first gate material layer 109, and the first gate oxide layer 108 are etched sequentially until the first aluminum gallium nitride layer 105 is exposed to form a second opening 115. The second opening 115 extends along the first direction y and penetrates a plurality of the first openings 107, and the width of the second opening 115 along the second direction x is smaller than the width of the first openings 107 along the second direction x. The remaining first gate material layer 109 constitutes the first portion 113 of the second gate, and the remaining first gate oxide layer 108 and the second gate oxide layer 110 constitute the second gate oxide layer 114.
[0074] like Figure 15 As shown, a first oxide layer 116 and a second gate material layer 117 are formed in the second opening 115. The first oxide layer 116 covers the bottom surface of the second opening 115, and the thickness of the first oxide layer 116 is the same as the thickness of the second gate oxide layer 114. The second gate material layer 117 covers the first oxide layer 116, and the top surface of the second gate material layer 117 is flush with the top surface of the first portion 113.
[0075] like Figure 16 As shown, a portion of the second gate material layer 117 is etched away, and the remaining second gate material layer 117 covers the sidewall of the first portion 113 to form the second portion 118 of the second gate; then, an ion implantation process is performed on the first aluminum gallium nitride layer 105 in the second opening 115 and the fourth aluminum gallium nitride layer 111 on the first portion 113 to form source / drain regions (not shown).
[0076] like Figure 17 As shown, a second oxide layer 119 is formed, which fills the second opening 115.
[0077] Figure 18 for Figure 17 The cross-sectional view of the structure shown is along lines A to A1, as follows: Figure 18 As shown, in this embodiment, the second portion 118 extends to cover part of the sidewall of the third aluminum gallium nitride layer 106, such that the width of the second portion 118 along the first direction y is greater than the width of the first portion 113 along the first direction y.
[0078] like Figure 19 As shown, the sacrificial layer 103 is removed to expose the third aluminum gallium nitride layer 106.
[0079] Figure 21 for Figure 20The cross-sectional view of the structure shown is along lines A to A1, as follows: Figures 20-21 As shown, the third aluminum gallium nitride layer 106 is etched to form a third opening 120 that exposes the first aluminum gallium nitride layer 105. The third opening 120 extends along the first direction y.
[0080] like Figure 22 As shown, a third gate oxide material layer 121 is formed within the third opening 120, and the third gate oxide material layer 121 covers the inner wall of the third opening 120.
[0081] like Figure 23 As shown, a second gate material layer 117 is formed in the third opening 120. The top surface of the second gate material layer 117 is flush with the top surface of the second gate. The second gate material layer 117 constitutes the first gate 122.
[0082] like Figure 24 As shown, a fourth gate oxide layer 123 is formed within the third opening 120, and the fourth gate oxide layer 123 covers the top surface of the first gate 122 and the third gate oxide layer 121.
[0083] like Figure 25 As shown, after removing the third gate oxide layer 121 and the fourth gate oxide layer 123 on the sidewall of the third opening 120, the remaining third gate oxide layer 121 and the fourth gate oxide layer 123 constitute the first gate oxide layer 124. Then, a fifth aluminum gallium nitride layer 125 is formed in the third opening 120, and the top surface of the fifth aluminum gallium nitride layer 125 is flush with the top surface of the third aluminum gallium nitride layer 106. The fifth aluminum gallium nitride layer 125, the fourth aluminum gallium nitride layer 111, and the third aluminum gallium nitride layer 106 constitute the second aluminum gallium nitride layer 102. A third oxide layer 126 is formed in the third opening 120, and the third oxide layer 126 fills the third opening 120. The first oxide layer 116, the third oxide layer 126, the second oxide layer 119, and the fourth oxide layer 112 constitute the dielectric layer 128.
[0084] like Figure 26As shown, a plurality of plugs 127 are formed in the dielectric layer 128. The plugs 127 are electrically connected to the source / drain region and the second portion 118, respectively. In this embodiment, the channel region of the field-effect transistor is the second aluminum gallium nitride layer 102 and the first aluminum gallium nitride layer 105 between the first gate 122 and the second gate. The source / drain region and channel region distributed horizontally in the original field-effect transistor are transformed into a vertical distribution, which facilitates the increase of the size of the channel region. At the same time, the second gate portion is embedded in the second aluminum gallium nitride layer 102, that is, embedded in the channel region, to form an embedded gate structure, which can effectively enhance the control of the second gate over the electrons in the channel region, thereby providing a field-effect transistor with better threshold characteristics and stability.
[0085] In other alternative embodiments, the plug 127 may also be electrically connected to the first gate 122 to further enhance the control of the first gate 122 and the second gate over the electrons in the channel region.
[0086] In summary, in the field-effect transistor provided in this embodiment of the invention, the first gate 122 extends along the first direction y, the second gate is located on both sides of the first gate 122, the second aluminum gallium nitride layer extends along the first direction y and covers the first gate 122 and part of the second gate, the source and drain regions are respectively located in the first aluminum gallium nitride layer 105 away from the second gate 122 and in the second aluminum gallium nitride layer 102 above the second gate, the channel region of the field-effect transistor provided by this invention is the second aluminum gallium nitride layer 102 and the first aluminum gallium nitride layer 105 between the first gate 122 and the second gate, transforming the horizontal channel region in the existing field-effect transistor into the vertical direction, increasing the size of the channel region, and effectively reducing the impact of semiconductor device miniaturization on the channel region size; at the same time, the second aluminum gallium nitride layer 102 covers part of the second gate, and the dielectric layer 128 covers the remaining second gate, so that the second gate is partially embedded in the second aluminum gallium nitride layer 102, forming an embedded gate structure, thereby effectively strengthening the control of the second gate on electrons in the channel region, and giving the field-effect transistor better threshold characteristics and stability.
[0087] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A field-effect transistor, characterized in that, include: Substrate; A first aluminum gallium nitride layer is located on the substrate; A first gate is located on the first aluminum gallium nitride layer and extends along a first direction; The second gate is located on both sides of the first gate; The second aluminum gallium nitride layer extends upward from the position of the first aluminum gallium nitride layer between the first gate and the second gate to cover the sidewall of the second gate, and extends above the first aluminum gallium nitride layer along the first direction and the second direction, covering the top of the first gate, part of the first aluminum gallium nitride layer and the top of the second gate, wherein the first direction is perpendicular to the second direction. The source and drain regions are respectively located within the first aluminum gallium nitride layer on the side of the second gate away from the first gate and within the second aluminum gallium nitride layer above the second gate; The second gate includes a first portion and a second portion, the second aluminum gallium nitride layer covers the first portion, and the width of the second portion along the first direction is greater than the width of the first portion along the first direction. The second aluminum gallium nitride layer and the first aluminum gallium nitride layer between the first gate and the second gate constitute a channel region.
2. The field-effect transistor as described in claim 1, characterized in that, Also includes: The first gate oxide layer is located between the first gate and the first aluminum gallium nitride layer and the second aluminum gallium nitride layer; The second gate oxide layer is located between the second gate and the first aluminum gallium nitride layer and the second aluminum gallium nitride layer.
3. The field-effect transistor as described in claim 2, characterized in that, The materials of the first gate oxide layer and the second gate oxide layer include hafnium dioxide.
4. The field-effect transistor as described in claim 1, characterized in that, Also includes: A gallium nitride layer is located between the substrate and the first aluminum gallium nitride layer, and covers the substrate.
5. The field-effect transistor as claimed in claim 1, characterized in that, Also includes: A dielectric layer covers the first aluminum gallium nitride layer, the second gate, and the second aluminum gallium nitride layer, and is located between the second portion and the first aluminum gallium nitride layer; Several plugs are located within the dielectric layer and are electrically connected to the first gate, the second gate, and the source / drain regions, respectively.
6. A method for fabricating a field-effect transistor, characterized in that, include: Provide substrate; A first aluminum gallium nitride layer is formed, which covers the substrate; A first gate, a second gate, and a second aluminum gallium nitride layer are formed. The first gate covers a portion of the first aluminum gallium nitride layer and extends along a first direction. The second gate is located on both sides of the first gate. The second aluminum gallium nitride layer extends upward from the position of the first aluminum gallium nitride layer between the first gate and the second gate to cover the sidewall of the second gate. It also extends above the first aluminum gallium nitride layer along the first and second directions, covering the top of the first gate, a portion of the first aluminum gallium nitride layer, and the top of the second gate. The first direction is perpendicular to the second direction. Source and drain regions are formed, which are respectively located in the first aluminum gallium nitride layer on the side of the second gate away from the first gate and in the second aluminum gallium nitride layer above the second gate; The second gate includes a first portion and a second portion, the second aluminum gallium nitride layer covers the first portion, and the width of the second portion along the first direction is greater than the width of the first portion along the first direction. The second aluminum gallium nitride layer and the first aluminum gallium nitride layer between the first gate and the second gate constitute a channel region.
7. The method for fabricating a field-effect transistor as described in claim 6, characterized in that, After forming the first aluminum gallium nitride layer, the step of forming the second gate includes: A third aluminum gallium nitride layer is formed on the first aluminum gallium nitride layer, and the third aluminum gallium nitride layer covers the first aluminum gallium nitride layer; Etching removes a portion of the third aluminum gallium nitride to form a plurality of first openings, the first openings being distributed along the first direction and exposing the first aluminum gallium nitride layer; A first gate oxide layer, a first gate material layer, a second gate oxide layer, and a fourth aluminum gallium nitride layer are sequentially formed in the first opening. The first gate oxide layer covers a portion of the height and bottom surface of the sidewall of the first opening. The first gate material layer fills a portion of the first opening. The second gate oxide layer covers the top surface of the first portion. The fourth aluminum gallium nitride layer covers the second gate oxide layer, and the top surface of the fourth aluminum gallium nitride layer is flush with the top surface of the third aluminum gallium nitride layer. A portion of the fourth aluminum gallium nitride layer, the second gate oxide layer, the first gate material layer, and the first gate oxide layer are removed to form a second opening exposing the first aluminum gallium nitride layer. The second opening extends along the first direction to penetrate a plurality of the first openings, and the remaining first gate material constitutes the first portion of the second gate. A first oxide layer and a second gate material layer are formed in the second opening. The first oxide layer covers the first aluminum gallium nitride layer, and the second gate material layer covers the sidewall of the first portion to form the second portion of the second gate. A second oxide layer is formed, which fills the second opening.
8. The method for fabricating a field-effect transistor as described in claim 7, characterized in that, After the second part is formed and before the second oxide layer is formed, the process further includes: An ion implantation process is performed on the first aluminum gallium nitride layer inside the second opening and the fourth aluminum gallium nitride layer above the first portion to form source / drain regions in the first aluminum gallium nitride layer on both sides of the second portion and the fourth aluminum gallium nitride layer above the first portion.
9. The method for fabricating a field-effect transistor as described in claim 7, characterized in that, The step of forming the first gate includes: The third aluminum gallium nitride layer between the second gates is etched to form a third opening exposing the first aluminum gallium nitride layer, the third opening extending along the first direction; A third gate oxide layer, a third gate material layer, and a fourth gate oxide layer are formed within the third opening. The third gate oxide layer covers a portion of the height of the sidewall and the bottom surface of the third opening. The third gate material layer fills a portion of the third opening to form the first gate. The fourth gate oxide layer covers the first gate. A fifth aluminum gallium nitride layer and a third oxide layer are formed to fill the third opening.