A method for permeation passivation of silicon nanowire arrays

Abstract

The application relates to the technical field of silicon nano array, and proposes a permeation passivation method for a silicon nano array, which comprises the following steps: dropping a passivation solution onto the surface of the silicon nano array, standing until permeation, and completing passivation. Through the technical scheme, 1) the passivation problem of the silicon nano array is solved, the silicon nano array prepared through physical etching and chemical etching is effectively and high-quality passivated, large-scale vacuum equipment required by an existing passivation scheme is eliminated, the process is simplified, the cost is reduced, and the safety is improved; 2) the silicon nano array is permeation passivated, so that the silicon nano array simultaneously has low reflection loss and low recombination loss functions, meets two necessary conditions of inverse Auger abnormal photovoltaic effect (that is, one photon generates two pairs of electron-hole pairs), the external quantum efficiency is greater than 100%, the SQ theoretical limit of the single-crystal silicon cell efficiency can be broken through, and higher cell photoelectric conversion efficiency can be obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon nanometer array, in particular to a permeation passivation method for silicon nanometer array. BACKGROUND

[0002] The silicon nanometer array structure can effectively reduce the reflection of incident light and increase the absorption of light. However, due to the large specific surface area of the silicon nanometer array and the large number of surface recombination centers, most of the photo-generated carriers are lost by surface recombination, which hinders the effective conversion of light energy to electrical energy. At present, there is a lack of effective high-quality passivation technology to inhibit the surface recombination of carriers.

[0003] The existing silicon nanometer array passivation technology includes growing silicon dioxide (SiO2) on the surface of the silicon nanometer array by high-temperature thermal oxidation, preparing amorphous silicon, silicon nitride (SiN x ) and aluminum oxide (Al2O3) dielectric film passivation layer by atomic layer deposition (ALD) and other methods, so that the dielectric film passivation layer is grown on the surface of the silicon nanometer array to passivate surface defects.

[0004] The preparation methods of the silicon nanometer array mainly include physical etching and chemical etching. The surface morphology of the silicon nanometer array prepared by different methods is different, and the difficulty of passivation is also different. Compared with the regular arrangement and large pore of the conical silicon nanometer array formed by physical etching, the linear silicon nanometer array prepared by chemical etching has the characteristics of random arrangement, different pore size and more surface defects, so it is more difficult to passivate. Figure 1

[0005] Whether it is a silicon nanometer array prepared by physical etching or a silicon nanometer array prepared by chemical etching, the existing high-temperature thermal oxidation method for preparing SiO2, the PECVD method for preparing amorphous silicon, and the SiN x and other dielectric film passivation layers cannot be completely and uniformly grown on the surface of the silicon nanometer array, especially the bottom of the silicon nanometer array, so the surface defects of the silicon nanometer array cannot be effectively passivated.

[0006] For the silicon nanometer array prepared by physical etching, only the Al2O3 dielectric film prepared by ALD can be grown on the surface of the silicon nanometer array, which can solve the passivation problem to a certain extent. For the silicon nanometer array prepared by chemical etching, due to its linear structure, uneven pore size and more surface defects, ALD deposition of Al2O3 cannot effectively solve the surface recombination problem.

[0007] In addition, the existing passivation materials such as SiN x ​, Al2O3, etc., large equipment such as PECVD, ALD needs to be used, there are problems such as high cost, complex process, involving dangerous gas source, not easy to mass production, how to simplify the passivation process, effectively and high quality complete passivation is a technical problem that the industry has been difficult to solve. SUMMARY

[0008] The application provides a permeation passivation method for a silicon nano array, solves the passivation problem of the silicon nano array, effectively and high quality passivates the silicon nano array prepared by physical etching or chemical etching, eliminates the large vacuum equipment required by the existing passivation scheme, simplifies the process, reduces the cost, and improves the safety.

[0009] The technical scheme of the application is as follows:

[0010] A permeation passivation method for a silicon nano array, comprising the following steps: dropping a passivation solution on the surface of the silicon nano array, standing until permeation, and completing passivation.

[0011] As a further technical scheme, after completing passivation, a thin film can be prepared by a spin coating method, a blade coating method, etc.

[0012] As a further technical scheme, the passivation solution is an organic solution or an inorganic solution.

[0013] The organic solution is prepared by mixing an organic compound with a sulfonic acid group, a phosphoric acid group, and a carboxylic acid group with a solvent.

[0014] The inorganic solution is selected from iodine liquor, sulfuric acid, or sulfurous acid.

[0015] As a further technical scheme, the passivation solution has the ability to penetrate into the pores of the nano silicon.

[0016] As a further technical scheme, the ability of the solution to penetrate into the pores of the nano silicon refers to good hydrophilicity of the solution, small contact angle with the nano silicon, and large surface tension.

[0017] As a further technical scheme, the solvent includes one or a mixed solvent of water, methanol, ethanol, isopropanol, etc.

[0018] As a further technical scheme, the silicon nano array is obtained by treating a silicon wafer by chemical etching or physical etching.

[0019] As a further technical scheme, the standing time is 0.5-10 min.

[0020] As a further technical scheme, the length of the silicon nano array is 10-1000 nm.

[0021] The application further provides application of the permeation passivation method for the silicon nano array in a silicon nano array solar cell.

[0022] The application has the following advantages:

[0023] 1. The application uses a passivation material to replace the existing dielectric passivation material, and the passivation material is prepared into a passivation solution to passivate the surface of the silicon nano array through solution permeation, thereby solving the problem that the dielectric film cannot be completely and uniformly grown on the silicon nano array, and the silicon nano array prepared by physical etching or chemical etching can be effectively passivated; the passivation material has the advantage of low natural cost, and when the solution permeation passivation scheme at room temperature needs to prepare a film in the end, a spin coating method or a blade coating method is used to prepare the film, thereby replacing the expensive and complex vacuum preparation technology, greatly reducing the cost, making the preparation process simpler, and being safer.

[0024] 2. The method has a simple and safe process flow; in the application, the passivation solution is dropped onto the surface of the silicon nano array, the solution permeates to passivate the silicon nano array, and then a film can be prepared by using a spin coating method, a blade coating method or the like, while the prior art uses an atomic layer deposition method and is performed in a vacuum device. The film plating step in the vacuum device is more complex and involves equipment use, operation and management, and the passivation process can be completed at room temperature.

[0025] 3. The passivation method has low cost; in terms of materials, the passivation material has low cost, and the material used in the prior art has relatively high cost; in terms of equipment, the application does not need large equipment, and the expensive equipment cost, maintenance cost, management cost, labor cost and electricity cost are saved.

[0026] 4. The passivation method has high production quality, and there is no limitation on the area of the silicon wafer; different sizes of silicon wafers can be passivated by solution permeation, and the passivation effect is the same at different positions, and there is no difference between the edge and the center; the size of the silicon wafer is limited by the size of the vacuum device in the prior art, and the larger the area, the worse the uniformity of the film deposition, which greatly reduces the passivation effect.

[0027] 5. The silicon wafer obtained by the passivation method has good performance, and the minority carrier lifetime can be greatly improved compared with the prior art. The silicon nano array is passivated by the method, and is applied to a silicon nano array solar cell, and has low reflection loss and low recombination loss, meets the two necessary conditions of inverse Auger abnormal photovoltaic effect (i.e. one photon generates two pairs of electron-hole pairs), and obtains an external quantum efficiency of more than 100%, which is expected to break through the theoretical limit of the single-crystal silicon cell SQ photoelectric conversion efficiency.

[0028] 6、The passivation method of the application can replace the antireflection material, and is a passivation and antireflection dual-functional film. The prior art, i.e. the atomic layer deposition method for depositing aluminum oxide, can only solve the passivation problem of the silicon wafer subjected to physical etching to a certain extent, and the ALD method cannot achieve the passivation effect for the silicon wafer subjected to chemical etching, because the array spacing of the physical etching is wider than that of the chemical etching, and the aluminum oxide can grow at the bottom, while the aluminum oxide cannot grow well at the bottom due to the narrow gap of the chemical etching. The passivation method of the application can solve the technical problem that the ALD method cannot grow the film well at the bottom of the chemical etching, and has a good passivation effect. BRIEF DESCRIPTION OF DRAWINGS

[0029] The application will be further described in detail below in combination with the drawings and specific embodiments.

[0030] Figure 1 Schematic diagram of the silicon nano array structure prepared by physical etching and chemical etching;

[0031] Figure 2 The electron microscope images of the silicon wafer treated in Example 1 before and after passivation, wherein a is before passivation, and b is after passivation;

[0032] Figure 3 The minority carrier lifetime diagram of the silicon wafer obtained in Example 1 under the oxygen passing condition;

[0033] Figure 4 The minority carrier lifetime diagram of the silicon wafer obtained in Comparative Example 1 under the oxygen passing condition;

[0034] Figure 5 The external quantum efficiency comparison diagram of the traditional IBC cell and the IBC silicon nano array solar cell of the application;

[0035] Figure 6 The antireflection effect comparison diagram of the IBC silicon nano array solar cell with and without the film;

[0036] Figure 7 The minority carrier lifetime comparison diagram of the silicon wafer obtained in Examples 1-4 under the non-oxygen passing condition;

[0037] Figure 8 The minority carrier lifetime comparison diagram of the silicon wafer obtained in Examples 5-8 under the non-oxygen passing condition. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the application will be clearly and completely described below in combination with the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all the other embodiments obtained by those skilled in the art without creative labor are involved in the protection scope of the application.

[0039] Example 1

[0040] S1, processing silicon wafer: single-sided chemical etching surface treatment was performed on a double-sided polished silicon wafer, one side obtained a silicon nano array structure, the length of the silicon nano array was 160 nm, and the other side was unchanged, still a polished surface;

[0041] S2, cleaning the silicon wafer: the silicon wafer was soaked in 10% hydrofluoric acid for 10 min;

[0042] S3, preparing a solution: 20wt% perfluorosulfonic acid was mixed with anhydrous ethanol to prepare a solution with a mass concentration of 5.9%;

[0043] S4, passivation: the above solution was dropped on the surface of the processed silicon wafer and left for 3 min;

[0044] S5, preparing a thin film: the excess solution was spun off at the same time to prepare a thin film by using a spin coating method; the above solution was dropped on the other side which was not processed, and a film was directly spin-coated (this side was not processed and did not need to be infiltrated), wherein the rotation speed of the spin coating method was 3500 r / min. The electron microscope images before and after passivation are shown in Figure 2 .

[0045] Example 2

[0046] Compared with Example 1, the other steps were the same, and the difference was that in step S3, the mass concentration of the solution was 3.5%.

[0047] Example 3

[0048] Compared with Example 1, the other steps were the same, and the difference was that in step S3, the mass concentration of the solution was 1.8%.

[0049] Example 4

[0050] Compared with Example 1, the other steps were the same, and the difference was that in step S3, the mass concentration of the solution was 0.3%, and in step S4, the solution was left for 5 min.

[0051] Example 5

[0052] Compared with Example 1, the other steps were the same, and the difference was that the length of the silicon nano array was 320 nm.

[0053] Example 6

[0054] Compared with Example 2, the other steps were the same, and the difference was that the length of the silicon nano array was 320 nm.

[0055] Example 7

[0056] The other steps are the same as in Example 3, except that the length of the silicon nanometer array is 320 nm.

[0057] Example 8

[0058] The other steps are the same as in Example 4, except that the length of the silicon nanometer array is 320 nm.

[0059] Comparative Example 1

[0060] 1) Steps S1 and S2 are the same.

[0061] 2) One cycle of ALD deposition growth of an Al2O3 film: 1. The obtained silicon wafer is placed in the ALD device cavity, and the surface of the silicon wafer is hydrophilic, and Si-OH bonds exist on the surface; 2. The TMA precursor is brought into the reaction cavity by pulse with the carrier gas N2, and saturated chemical adsorption and reaction occur on the silicon surface. The TMA reacts with the -OH groups on the surface of the silicon wafer to form Si-O-Al-CH3 bonds, and a monolayer of TMA is generated; 3. Inert carrier gas N2 is introduced to purify the reaction cavity and discharge unreacted TMA and reaction product CH4; 4. The H2O precursor is brought into the reaction cavity by pulse with the carrier gas N2, and the H2O coordinates to replace the CH3 group in the Si-O-Al-CH3 bond to create an O-Al-OH bond, and a layer of Al atoms has been deposited on the surface of the silicon wafer; 5. Unreacted H2O and reaction product CH4 are discharged again by introducing N2; 6. The reaction process is repeated to form an Al2O3 film.

[0062] 3) Step 2 is repeated on the other side of the silicon wafer to grow an aluminum oxide film on both sides of the silicon wafer.

[0063] 4) The silicon wafer with films on both sides is placed in an annealing furnace and annealed at 400°C for 30 min in a nitrogen atmosphere.

[0064] Experimental Example 1

[0065] The minority carrier lifetime of the silicon wafer obtained in Example 1 and Comparative Example 1 is tested using a Sinton device under oxygen conditions.

[0066] The minority carrier lifetime of the silicon wafer obtained in Example 1 and Comparative Example 1 is shown in Figure 3 , 4 The experimental results are shown in Table 1.

[0067] Table 1 Comparison of minority carrier lifetime data of silicon wafers in Example 1 and Comparative Example 1

[0068] Item Example 1 Comparative Example 1 Before passivation Minority carrier lifetime 2.4 ms 11.43 μs 3.8 μs

[0069] According to the above data, it can be found that the minority carrier lifetime of the embodiment of the application is significantly improved, the method of example 1 can improve the minority carrier lifetime of the silicon wafer by about 632 times under the oxygen passing condition, and the method of comparative example 1, i.e., the atomic layer deposition method, can only improve the minority carrier lifetime by about 3 times.

[0070] The silicon nanometer array obtained by chemical etching is linear and vertically arranged, the surface is uneven, the defects are more, the arrangement is random, the interval is relatively narrow, generally 20-200 nm, the widest is several hundred nanometers, and the interval is uneven, while the silicon nanometer array obtained by physical etching is conical, the interval of the nanometer array is relatively wide, generally can reach microns, and the interval between the nanometer arrays is uniform. Therefore, the chemical etching is more difficult to passivate, and it is difficult to grow a passivation layer at the bottom. Due to the narrow interval of the silicon nanometer array obtained by chemical etching, the deposition effect is very poor, which leads to that the passivation cannot be well completed, while the solution infiltration method of the application can complete the infiltration only by completely coating the solution on the surface of the silicon wafer, and good passivation effect can be achieved whether chemical etching or physical etching is used.

[0071] Experimental example 2

[0072] 1) Double-sided polishing of n-type bare silicon wafer to remove surface damage layer;

[0073] 2) First, a layer of intrinsic amorphous silicon film is prepared on one side of the passivated silicon wafer by PECVD technology;

[0074] 3) Then, n-type amorphous silicon and p-type amorphous silicon are prepared on this side by PECVD technology through photolithography technology to form a back field and an emission junction respectively;

[0075] 4) Finally, positive and negative electrodes are prepared on this side by screen printing technology;

[0076] 5) On the other side, a silicon nanometer array (the length of the silicon nanometer array is between 400-500 nm) is prepared by chemical etching method;

[0077] 6) The solution in example 2 is dropped on the surface of the silicon nanometer array, and spin-coated into a film after standing for 3 min.

[0078] The external quantum efficiency of the silicon nanometer array solar cell and the traditional IBC cell purchased on the market is tested.

[0079] The experimental results are as follows Figure 5As shown, the IBC silicon nanometer array solar cell of the present application produces obvious inverse Auger abnormal photovoltaic effect in the ultraviolet region (<300 nm), and an external quantum efficiency of EQE=129% is obtained at 250 nm (breaking the theoretical limit of one photon generating one electron-hole pair, i.e. the external quantum efficiency of the solar cell is greater than 100%), and the current is improved compared with the existing conventional cell, thereby improving the performance of the cell.

[0080] Experimental Example 3

[0081] The reflectivity of the solar cell in Experimental Example 2 was tested, and the results are shown in the following table. Figure 6 The solid line in the figure is the reflectivity of the silicon nanometer array structure before permeation passivation, and the dotted line is the reflectivity of the silicon nanometer array structure containing the thin film after permeation passivation. As can be seen from the figure, Figure 6 The thin film obtained by the passivation method of the present application not only has a passivation effect, but also has an antireflection effect, and the reflectivity is reduced by about 2%-4% in the wavelength range of 400-1000 nm. The thin film obtained by the passivation method of the present application applied to the IBC silicon nanometer array solar cell can further improve the conversion efficiency of the solar cell. The ALD prepared Al2O3 dielectric thin film of the prior art applied to the silicon wafer of the silicon nanometer array structure only has a passivation effect, and does not have an antireflection effect. If the antireflection effect is required, an additional antireflection material needs to be added.

[0082] Experimental Example 4

[0083] The silicon wafers obtained in Examples 1-8 were tested for minority carrier lifetime under conventional conditions (without oxygen) using a Sinton device. The results of the minority carrier lifetime of the silicon wafer with a silicon nanometer array length of 160 nm are shown in the following table. Figure 7 The results of the minority carrier lifetime of the silicon wafer with a silicon nanometer array length of 320 nm are shown in the following table. Figure 8

[0084] As can be seen from Figure 7 and Figure 8 The shorter the length of the silicon nanometer array, the higher the concentration of the solution is better; the longer the length, the lower the concentration is better, so in practical application to solar cells, the appropriate concentration can be selected according to the length of the silicon nanometer array.

[0085] The above is only a preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.​

Claims

1. A permeation passivation method for silicon nanoarrays, characterized in that, Includes the following steps: Passivation solution is dropped onto the surface of silicon nanoarray and left to stand until it penetrates, thus completing the passivation process. After passivation is completed, the process also includes the step of preparing a thin film by spin coating or blade coating. The passivation solution was prepared by mixing perfluorosulfonic acid with a solvent; When the length of the silicon nanoarray is 10-1000 nm, the mass concentration of the passivation solution is 0.3%-6.0%.

2. The permeation passivation method for silicon nanoarrays according to claim 1, characterized in that, The solvent includes one or more of the following solvents: water, methanol, ethanol, and isopropanol.

3. The permeation passivation method for silicon nanoarrays according to claim 1, characterized in that, The silicon nanoarray is obtained by processing a silicon wafer using chemical etching or physical etching.

4. The permeation passivation method for silicon nanoarrays according to claim 1, characterized in that, The settling time is 0.5-10 minutes.

5. The application of the permeation passivation method for silicon nanoarrays according to claim 1 in silicon nanoarray solar cells.

Images