Pressure sensor and its manufacturing method

Abstract

This application discloses a pressure sensor and its manufacturing method. The pressure sensor includes a substrate, the substrate including a first capacitance region, and a first doped region formed within a predetermined depth range of the first capacitance region in the substrate. The first doped region serves as a first electrode of the first capacitor. A first cavity is disposed within the substrate. A second electrode is disposed on one side of the substrate. In the orthographic projection of the substrate, the first electrode, the second electrode, and the first cavity all at least partially overlap, and the first cavity is located between the first electrode and the second electrode. This solution, by doping the substrate to form the first electrode and the first cavity within the substrate, eliminates the need for depositing a conductive film layer for forming the first electrode and a sacrificial layer for forming the first cavity compared to existing technologies. Therefore, it simplifies the fabrication process and reduces manufacturing costs.

Description

Technical Field

[0001] This invention generally relates to the field of sensor technology, and specifically to a pressure sensor and its manufacturing method. Background Technology

[0002] A pressure sensor is a device that converts pressure signals into electrical signals. It can be mainly classified into four types: piezoresistive, capacitive, resonant, and piezoelectric. A pressure sensor typically consists of an upper electrode, a lower electrode, and a vacuum cavity positioned between the upper and lower electrodes.

[0003] Currently, the fabrication of pressure sensors involves depositing a conductive film on a substrate, patterning the conductive film to form a lower electrode, depositing a sacrificial layer on the lower electrode, and then etching the sacrificial layer to form a vacuum cavity. Because the fabrication process requires depositing a conductive film and an additional sacrificial layer, followed by the etching removal of a portion of it, it increases the number of fabrication steps and thus the manufacturing cost. Summary of the Invention

[0004] This application aims to provide a pressure sensor and a method for manufacturing the same, thereby reducing the manufacturing cost of the pressure sensor.

[0005] In a first aspect, the present invention provides a pressure sensor, comprising:

[0006] A substrate, the substrate including a first capacitor region, a first doped region being formed within a predetermined depth range of the first capacitor region in the substrate, the first doped region serving as a first electrode of the first capacitor, and a first cavity being disposed within the substrate;

[0007] The second electrode plate is disposed on one side of the substrate. In the orthographic projection of the substrate, the first electrode plate, the second electrode plate, and the first cavity all overlap at least partially, and the first cavity is located between the first electrode plate and the second electrode plate.

[0008] As an implementation method, the substrate further includes a second capacitor region, and a second doped region is formed within a predetermined depth range of the second capacitor region in the substrate. The second doped region serves as the third electrode of the second capacitor, and a second cavity is provided in the substrate.

[0009] A third electrode plate is disposed on one side of the substrate. In the orthographic projection of the substrate, the third electrode plate, the fourth electrode plate, and the second cavity all overlap at least partially, and the second cavity is located between the third electrode plate and the fourth electrode plate.

[0010] A rigid support layer is provided on the side of the fourth electrode plate opposite to the third electrode plate.

[0011] As an alternative, the first doped region and the second doped region are prepared by the same implantation process.

[0012] As an alternative, the first cavity and the second cavity are fabricated using the same etching process.

[0013] As an alternative implementation, the second electrode plate and the fourth electrode plate are disposed on the same layer.

[0014] In one possible implementation, the first electrode is electrically connected to the first electrode, which is insulated from the substrate; the second electrode is electrically connected to the second electrode.

[0015] As an implementation, the third electrode is electrically connected to the third electrode, which is insulated from the substrate; the fourth electrode is electrically connected to the fourth electrode.

[0016] As an implementation method, both the first cavity and the second cavity are parallelogram cavities, and each face of the parallelogram cavity is a crystal plane, with the acute angle between adjacent crystal planes being 69°-72°.

[0017] As an implementation method, the acute angle is 70.52°.

[0018] As a possible implementation, one of the substrate and the first doped region is N-type and the other is P-type; and / or,

[0019] Of the substrate and the second doped region, one is N-type and the other is P-type.

[0020] Secondly, the present invention provides a method for manufacturing the above-mentioned pressure sensor, comprising:

[0021] A substrate is provided, the substrate including a first capacitance region;

[0022] A first doped region is formed at a predetermined depth in the first capacitor region of the substrate by an implantation process, and the first doped region serves as the first electrode of the first capacitor.

[0023] A first cavity is formed on one side of the substrate by an etching process;

[0024] A second electrode plate is formed on one side of the substrate. In the orthographic projection of the substrate, the first electrode plate, the second electrode plate, and the first cavity all at least partially overlap, and the first cavity is located between the first electrode plate and the second electrode plate.

[0025] As one possible implementation, the substrate further includes a second capacitance region;

[0026] A second doped region is formed at a predetermined depth in the second capacitor region of the substrate through the implantation process, and the second doped region serves as the third electrode of the second capacitor.

[0027] A second cavity is formed on one side of the substrate by the etching process described above;

[0028] A fourth electrode plate is formed on one side of the substrate. In the orthographic projection of the substrate, the third electrode plate, the fourth electrode plate, and the second cavity all at least partially overlap, and the second cavity is located between the third electrode plate and the fourth electrode plate.

[0029] As an implementation method, the formation of a first cavity on one side of the substrate through an etching process, and the formation of a second cavity on one side of the substrate through the etching process, specifically include:

[0030] An etching hole is formed on the top of the substrate by etching, and the depth of the etching hole is less than the predetermined depth range;

[0031] An etching protective layer is formed at least on the sidewalls and bottom surface of the etched hole;

[0032] After the etching protective layer is formed, the etching of the etch hole continues until the first doped region and the second doped region are reached;

[0033] The substrate is etched using a crystal plane self-stopping etching method through the etch holes to form the first cavity and the second cavity.

[0034] As an alternative approach, after forming the first cavity and the second cavity, the etched hole is filled to seal it.

[0035] As a possible implementation, a rigid support layer is formed on the fourth electrode plate;

[0036] A via is formed on the rigid support layer, and a conductive element is formed in the via, the conductive element being electrically connected to the fourth electrode plate;

[0037] A fourth electrode is formed on the side of the rigid support layer opposite to the fourth substrate, and the fourth electrode is electrically connected to the conductive element.

[0038] The above-mentioned solution forms a first electrode plate and a first cavity within the substrate by doping the substrate. Compared with the prior art, it does not require the deposition of a conductive film layer for forming the first electrode plate and a sacrificial layer for forming the first cavity. Therefore, it simplifies the fabrication process and reduces manufacturing costs. Attached Figure Description

[0039] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0040] Figure 1 This is a schematic diagram of the structure of a pressure sensor provided in an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of the structure of a pressure sensor provided in another embodiment of the present invention;

[0042] Figure 3 for Figure 2 The equivalent circuit diagram;

[0043] Figure 4 This is a schematic diagram of the structure of a pressure sensor provided in another embodiment of the present invention;

[0044] Figure 5 A schematic diagram of the structure of the first cavity provided in an embodiment of the present invention;

[0045] Figure 6 A flowchart illustrating a method for manufacturing a pressure sensor according to an embodiment of the present invention;

[0046] Figures 7-15 This is a schematic diagram of the manufacturing process of a pressure sensor according to an embodiment of the present invention;

[0047] Figures 16-28 This is a structural schematic diagram of the manufacturing process of a pressure sensor provided in another embodiment of the present invention. Detailed Implementation

[0048] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0049] The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; etching can employ known methods; and epitaxial growth also employs known methods; no specific limitations are made here.

[0050] In the description of the embodiments of this invention, it should be understood that a "thin film" refers to a thin film made of a certain material on a certain layer (e.g., a substrate) using deposition, coating, or growth processes. If the "thin film" does not require patterning or photolithography processes during the entire fabrication process, it can also be called a "layer". If the "thin film" requires patterning or photolithography processes during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern". For example, but not limited to, the thickness of the thin film referred to herein can be less than 100 μm.

[0051] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] like Figure 1 As shown, the pressure sensor provided by the present invention includes:

[0053] Substrate 1, the substrate 1 includes a first capacitor region A, a first doped region 2 is formed within a predetermined depth range of the first capacitor region A in the substrate 1, the first doped region 2 serves as the first electrode plate of the first capacitor C1, and a first cavity 7 is provided in the substrate 1.

[0054] For example, but not limited to, substrate 1 is a silicon substrate.

[0055] The first doped region 2 can be formed in the substrate 1 by implantation, and the implantation depth can be controlled by controlling the implantation process parameters, such as power and time, so as to achieve the formation of the first doped region 2 in the first capacitor region A within the substrate 1 at a predetermined depth range.

[0056] The first cavity 7 provides space for the deformation of the second electrode plate 5.

[0057] The second electrode plate 5 is disposed on one side of the substrate 1. In the orthographic projection of the substrate 1, the first electrode plate, the second electrode plate 5, and the first cavity 7 all overlap at least partially, and the first cavity 7 is located between the first electrode plate and the second electrode plate 5.

[0058] The first electrode plate 5 and the second electrode plate 5, as well as the first cavity 7, all overlap at least partially, forming a capacitor between the first electrode plate 5 and the second electrode plate 5. Furthermore, the partially overlapping portion also overlaps with the first cavity 7. When the pressure sensor senses pressure, the second electrode plate 5 deforms into the first cavity 7, reducing the distance between the first electrode plate 5 and the second electrode plate 5. Since the capacitance value is negatively correlated with the distance between the first electrode plate 5 and the second electrode plate 5, the capacitance value of the pressure sensor increases as the distance between them decreases. By observing the relationship between the change in capacitance value and the pressure value, the actual pressure value can be obtained.

[0059] The above solution forms a first electrode plate and a first cavity 7 within the substrate 1 by doping the substrate 1. Compared with the prior art, it does not require the deposition of a conductive film layer for forming the first electrode plate and a sacrificial layer for forming the first cavity 7. Therefore, it simplifies the fabrication process and reduces the manufacturing cost.

[0060] As a possible approach, such as Figure 2 As shown, in order to improve the detection accuracy of the pressure sensor, the substrate 1 further includes a second capacitor region B. A second doped region 10 is formed within a predetermined depth range of the second capacitor region B in the substrate 1. The second doped region 10 serves as the third electrode of the second capacitor C2. A second cavity 11 is provided in the substrate 1.

[0061] The third electrode plate is disposed on one side of the substrate 1. In the orthographic projection of the substrate 1, the third electrode plate, the fourth electrode plate 12, and the second cavity 11 all overlap at least partially, and the second cavity 11 is located between the third electrode plate and the fourth electrode plate 12.

[0062] A rigid support layer 13 is provided on the side of the fourth electrode plate 12 away from the third electrode plate. That is, a rigid support layer 13 is provided on the fourth electrode plate 12. Pressure is applied to the rigid support layer 13 so that it does not deform, thereby ensuring that the fourth electrode plate 12 does not deform into the second cavity 11, so that the second capacitor C2 is a capacitor with a constant capacitance value.

[0063] Both the first cavity 7 and the second cavity 11 are sealed cavities. For example, but not limited to, the sealed cavity can be a vacuum cavity.

[0064] The above scheme, such as Figure 3As shown, the pressure sensor also includes a first capacitor C1 whose capacitance value can change according to the pressure and a second capacitor C2 whose capacitance value is constant. In use, one of the plates of the first capacitor C1 and one of the plates of the second capacitor C2 can be electrically connected together. Of course, in other examples, they can also be not connected together. The actual capacitance value of the pressure sensor is the measured capacitance value, which is the current capacitance value of the first capacitor C1 (the capacitance value between contacts ab) minus the capacitance value of the second capacitor C2 (the capacitance value between contacts cd). By using differential capacitance, the background noise of the pressure sensor can be effectively eliminated, the detection accuracy can be improved, and the performance of the pressure sensor can be optimized.

[0065] As an feasible approach, in order to improve preparation efficiency, simplify the preparation process, and reduce preparation costs, the first doped region 2 and the second doped region 10 are prepared by the same implantation process, that is, the first doped region 2 and the second doped region 10 are prepared simultaneously by the same preparation process.

[0066] As an feasible approach, in order to improve preparation efficiency, simplify the preparation process, and reduce preparation costs, the first cavity 7 and the second cavity 11 are prepared by the same etching process, that is, the first cavity 7 and the second cavity 11 are prepared simultaneously by the same preparation process.

[0067] As an feasible approach, in order to improve preparation efficiency, simplify the preparation process, and reduce preparation costs, the second electrode plate 5 and the fourth electrode plate 12 are disposed in the same layer, that is, the second electrode plate 5 and the fourth electrode plate 12 can be obtained from the same film layer by patterning.

[0068] In one possible implementation, the first electrode plate is electrically connected to the first electrode 3, and the first electrode 3 is insulated from the substrate 1; the second electrode plate 5 is electrically connected to the second electrode 6.

[0069] For example, the insulation of the first electrode 3 from the substrate 1 can be achieved using the following structure, such as... Figure 1 As shown, the first electrode 3 is disposed in the area of ​​the first electrode plate exposed outside the substrate 1. The first electrode 3 has a relatively small width, such that it lies within the orthographic projection of the first electrode plate. Furthermore, a gap 4 exists between the first electrode 3 and the substrate 1 in the width direction to achieve insulation between the first electrode 3 and the substrate 1. With this structure, because the first electrode 3 has a small width and a gap needs to be maintained between it and the substrate 1 in the width direction, the process precision required for forming the first electrode 3 is relatively high. Figure 2As shown, in order to reduce the process precision requirements when forming the first electrode 3 and thus reduce manufacturing costs, an insulator 8 is formed on the side of the first cavity 7 near the area of ​​the first electrode plate exposed outside the substrate 1. With the insulator 8 provided, the width of the first electrode 3 can be made relatively large, thereby reducing the process precision requirements during fabrication and thus reducing manufacturing costs; Figure 4 As shown, an insulating layer can also be formed in the area of ​​the first electrode plate exposed outside the substrate 1, and the insulating layer also covers at least a portion of the substrate 1. A via is formed on the insulating layer, and the first electrode 3 is formed in the via.

[0070] As an implementation, the third electrode plate is electrically connected to the third electrode 9, and the third electrode 9 is insulated from the substrate 1; the fourth electrode plate 12 is electrically connected to the fourth electrode 15.

[0071] The insulation structure between the third electrode 9 and the substrate 1 can be referred to as the insulation structure between the first electrode 3 and the substrate 1 described above, and will not be repeated here.

[0072] As a possible approach, such as Figure 5 As shown, in this scheme, the first cavity 7 and the second cavity 11 are formed on the substrate 1 by etching through a self-stopping etching process, so that the first cavity 7 and the second cavity 11 are both parallelogram cavities, and each face of the parallelogram cavity is a crystal plane 20, and the acute angle between adjacent crystal planes 20 is 70.52°.

[0073] As one possible implementation, one of the substrate 1 and the first doped region 2 is N-type and the other is P-type, forming a PN junction between the substrate 1 and the first doped region 2 to prevent conduction between them. When the first doped region 2 is P-type and the substrate 1 is N-type, a negative voltage can be applied to the first electrode 3 during use to prevent conduction between the substrate 1 and the first doped region 2. When the first doped region 2 is N-type and the substrate 1 is P-type, a positive voltage can be applied to the first electrode 3 during use to prevent conduction between the substrate 1 and the first doped region 2, and / or...

[0074] Of the substrate 1 and the second doped region 10, one is N-type and the other is P-type, forming a PN junction between the substrate 1 and the second doped region 10 to prevent conduction between them. When the second doped region 10 is P-type and the substrate 1 is N-type, a negative voltage can be applied to the third electrode 9 during use to prevent conduction between the substrate 1 and the second doped region 10. When the second doped region 10 is N-type and the substrate 1 is P-type, a positive voltage can be applied to the third electrode 9 during use to prevent conduction between the substrate 1 and the second doped region 10.

[0075] Secondly, such as Figure 6 As shown, the present invention provides a method for manufacturing the above-mentioned pressure sensor, comprising:

[0076] S1: Provide a substrate 1, the substrate 1 including a first capacitance region A;

[0077] S2: A first doped region 2 is formed in the first capacitor region A of the substrate 1 at a predetermined depth range by an implantation process, and the first doped region 2 serves as the first electrode of the first capacitor C1.

[0078] S3: A first cavity 7 is formed on one side of the substrate 1 by an etching process;

[0079] S4: A second electrode plate 5 is formed on one side of the substrate 1. In the orthographic projection of the substrate 1, the first electrode plate, the second electrode plate 5, and the first cavity 7 all overlap at least partially, and the first cavity 7 is located between the first electrode plate and the second electrode plate 5.

[0080] As an implementation method, the substrate 1 further includes a second capacitance region A; that is, the substrate 1 includes a first capacitance region A and a second capacitance region B.

[0081] A second doped region 10 is formed at a predetermined depth in the second capacitor region B of the substrate 1 by means of the implantation process. The second doped region 10 serves as the third electrode of the second capacitor C2. That is, the second doped region 10 is formed on the substrate 1 at the same time as the first doped region 2 is formed by means of the same implantation process.

[0082] The second cavity 11 is formed on one side of the substrate 1 by the etching process; that is, the second cavity 11 is formed at the same time as the first cavity 7 is formed by the same etching process.

[0083] A fourth electrode plate 12 is formed on one side of the substrate 1. In the orthographic projection of the substrate 1, the third electrode plate, the fourth electrode plate 12, and the second cavity 11 all at least partially overlap, and the second cavity 11 is located between the third electrode plate and the fourth electrode plate 12.

[0084] As an implementation method, the formation of a first cavity 7 on one side of the substrate 1 through an etching process, and the formation of a second cavity 11 on one side of the substrate 1 through the etching process, specifically:

[0085] An etching hole 17 is formed on the top of the substrate 1 by etching, and the depth of the etching hole 17 is less than the predetermined depth range;

[0086] An etching protective layer 18 is formed at least on the sidewalls and bottom surface of the etched hole 17;

[0087] After the etching protective layer 18 is formed, the etching hole 17 is etched until the first doped region 2 and the second doped region 10 are reached; for example, but not limited to, the etching hole 17 is etched by DRIE (Deep Reactive Ion Etching). During etching, the etching protective layer 18 at the bottom of the etching hole 17 is etched away, while the etching protective layer 18 on the sidewall of the etching hole 17 is retained. In this way, when the first cavity 7 and the second cavity 11 are subsequently formed, the substrate 1 is etched only in the etching hole 17, that is, within the depth range of the second etching of the etching hole 17, to form the first cavity 7 and the second cavity 11.

[0088] The substrate 1 is etched using the etching hole 17 by employing a crystal plane self-stopping etching method to form the first cavity 7 and the second cavity 11.

[0089] As an alternative approach, after forming the first cavity 7 and the second cavity 11, the etched hole 17 is filled to seal the etched hole 17.

[0090] As a possible implementation, a rigid support layer 13 is formed on the fourth electrode plate 12;

[0091] A via is formed on the rigid support layer 13, and a conductive element 14 is formed in the via. The conductive element 14 is electrically connected to the fourth electrode plate 12.

[0092] A fourth electrode 15 is formed on the side of the rigid support layer 13 opposite to the fourth substrate 12, and the fourth electrode 15 is electrically connected to the conductive element 14.

[0093] The present invention will be illustrated by specific examples of two of the manufacturing methods below.

[0094] Example 1

[0095] like Figure 7 As shown, a substrate 1 is provided, which may be, for example, a P-type silicon substrate. The substrate 1 includes a first capacitor region A. The substrate 1 is locally N-type doped by an implantation process to improve the conductivity of the doped site. A first doped region 2 is formed within the substrate 1 at a predetermined depth range of the first capacitor region A. The first doped region 2 serves as the first electrode of the first capacitor C1.

[0096] like Figure 8As shown, a photoresist layer is formed on the top of the substrate 1, and the photoresist layer is exposed and developed to serve as a mask. An etching hole 17 is formed on the top of the substrate 1, for example, but not limited to, using DRIE (Deep Reactive Ion Etching) to form the etching hole 17. The photoresist layer is removed after etching, and the depth of the etching hole 17 is less than the predetermined depth range.

[0097] like Figure 9 As shown, an etching protection layer 18 is deposited on the sidewalls and bottom surface of the etched hole 17 using LPCVD (Low Pressure Chemical Vapor Deposition). The material of the etching protection layer 18 can be, but is not limited to, silicon nitride or silicon oxide.

[0098] like Figure 10 As shown, DRIE can be used to continue etching the hole 17 downwards until the first doped region 2 is reached;

[0099] like Figure 11 As shown, a photoresist layer is formed on the top of the substrate 1, and the photoresist layer is exposed and developed to serve as a mask 19. A first cavity 7 is formed by a crystal plane self-stop etching method, and the photoresist layer is removed after etching. The first cavity is a parallelogram cavity, and each face of the parallelogram cavity is a crystal plane. The acute angle between adjacent crystal planes is 70.52°. Of course, in other examples, the acute angle can be other degrees depending on the actual situation.

[0100] like Figure 12 As shown, an insulating material such as silicon oxide or silicon nitride is deposited on the top surface of substrate 1 by LPCVD. At least a portion of the deposited material is located within the etched holes 17 to fill the etched holes 17. After sealing the etched holes 17, CMP (Chemical Mechanical Polishing) is used to remove excess filling material from the surface of substrate 1 to expose the top surface of substrate 1.

[0101] like Figure 13 As shown, an electrode plate thin film is deposited on the top surface of the substrate 1, and the electrode plate thin film is patterned to form a second electrode plate 5; wherein, the material of the electrode plate thin film can be polycrystalline silicon, metal, etc., and the metal is, for example, but not limited to, elemental or alloyed materials including aluminum, copper, silver, gold, etc.

[0102] like Figure 14As shown, at a location different from the second electrode 5, for example, ICP (Inductive Coupled Plasma) is used to etch the substrate 1 until the first doped region 2 is exposed, and an insulator 8 is formed in the first doped region 2 exposed outside the substrate 1.

[0103] like Figure 15 As shown, a first electrode 3 is formed in the first doped region 2, and a second electrode 6 is formed on the second electrode plate 5. The first electrode 3 is electrically connected to the first doped region 2, and the second electrode 6 is electrically connected to the second electrode plate 5.

[0104] For example, an electrode film can be deposited by PVD (Physical Vapor Deposition) and then patterned to obtain the first electrode 3 and the second electrode 6.

[0105] Example 2

[0106] like Figure 16 As shown, a substrate 1 is provided, which may be, for example, a P-type silicon substrate. The substrate 1 includes a first capacitor region A and a second capacitor region B. The substrate 1 is locally N-type doped by an implantation process to improve the conductivity of the doped sites. A first doped region 2 is formed within the substrate 1 at a predetermined depth range of the first capacitor region A. The first doped region 2 serves as the first electrode of the first capacitor C1. A second doped region 10 is formed within the substrate 1 at a predetermined depth range of the second capacitor region B. The second doped region 10 serves as the third electrode of the second capacitor C2.

[0107] like Figure 17 As shown, a photoresist layer is formed on the top of the substrate 1, and the photoresist layer is exposed and developed to serve as a mask. An etching hole 17 is formed on the top of the substrate 1, for example, but not limited to, using DRIE (Deep Reactive Ion Etching) to form the etching hole 17. The photoresist layer is removed after etching, and the depth of the etching hole 17 is less than the predetermined depth range.

[0108] like Figure 18 As shown, an etching protection layer 18 is deposited on the sidewalls and bottom surface of the etched hole 17 using LPCVD (Low Pressure Chemical Vapor Deposition). The material of the etching protection layer 18 can be, but is not limited to, silicon nitride or silicon oxide.

[0109] like Figure 19 As shown, DRIE can be used to continue etching the etched hole 17 downwards until the first doped region 2 and the second doped region 10 are reached;

[0110] like Figure 20 As shown, a photoresist layer is formed on the top of the substrate 1, and the photoresist layer is exposed and developed to serve as a mask 19. A first cavity 7 and a second cavity 11 are formed by a crystal plane self-stop etching method, and the photoresist layer is removed after etching.

[0111] like Figure 21 As shown, an insulating material such as silicon oxide or silicon nitride is deposited on the top surface of substrate 1 by LPCVD. At least a portion of the deposited material is located within the etched holes 17 to fill the etched holes 17. After sealing the etched holes 17, CMP (Chemical Mechanical Polishing) is used to remove excess filler material from the surface of substrate 1 to expose the top surface of substrate 1.

[0112] like Figure 22 As shown, an electrode plate thin film is deposited on the top surface of the substrate 1, and the electrode plate thin film is patterned to form a second electrode plate 5 and a fourth electrode plate 12; wherein, the material of the electrode plate thin film can be polycrystalline silicon, metal, etc., and the metal is, for example, but not limited to, elements or alloys including aluminum, copper, silver, gold, etc.

[0113] like Figure 23 As shown, at a position different from the second electrode 5 and the fourth electrode 12, for example, ICP (Inductively Coupled Plasma) is used to etch the substrate 1 until the first doped region 2 and the second doped region 10 are exposed, and an insulator 8 is formed in both the first doped region 2 and the second doped region 10 exposed outside the substrate 1.

[0114] like Figure 24 As shown, a first electrode 3 is formed in the first doped region 2, and a second electrode 6 is formed on the second electrode plate 5. The first electrode 3 is electrically connected to the first doped region 2, and the second electrode 6 is electrically connected to the second electrode plate 5.

[0115] like Figure 25 As shown, a third electrode 9 is formed in the second doped region 10, and the third electrode 9 is electrically connected to the second doped region 10.

[0116] In some examples, the first electrode 3, the second electrode 6, and the third electrode 9 can also be disposed in the same layer. For example, an electrode film can be deposited by PVD (Physical Vapor Deposition) and the first electrode 3, the second electrode 6, and the third electrode 9 can be obtained by patterning.

[0117] like Figure 26As shown, a rigid support layer 13 is provided on the fourth electrode plate 12. For example, but not limited to, the rigid support layer 13 can be a thick silicon nitride layer or silicon oxide layer, etc., and the rigid support layer 13 can be formed by CVD (Chemical Vapor Deposition).

[0118] like Figure 27 As shown, vias are formed on the rigid support layer 13 vias through DRIE, and conductive elements 14 are deposited in the vias, the conductive elements 14 being electrically connected to the fourth electrode plate 12.

[0119] like Figure 28 As shown, an electrode film is deposited by PVD on the side of the rigid support layer 13 away from the fourth substrate 12, and the electrode film is patterned to form a fourth electrode 15, which is electrically connected to the conductive element 14.

[0120] It should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., used above to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0121] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A pressure sensor, characterized by The application relates to a substrate for a capacitor, comprising: a substrate, wherein a first capacitor region is formed in the substrate, a first doped region is formed in the substrate within a predetermined depth range of the first capacitor region, the first doped region serves as a first electrode plate of a first capacitor, and a first cavity is etched in the substrate; a second electrode plate is arranged on one side of the substrate, in the orthographic projection of the substrate, the first electrode plate, the second electrode plate and the first cavity at least partially overlap, and the first cavity is located between the first electrode plate and the second electrode plate; the substrate further comprises a second capacitor region, a second doped region is formed in the substrate within a predetermined depth range of the second capacitor region, the second doped region serves as a third electrode plate of a second capacitor, and a second cavity is arranged in the substrate; a third electrode plate is arranged on one side of the substrate, in the orthographic projection of the substrate, the third electrode plate, the fourth electrode plate and the second cavity at least partially overlap, and the second cavity is located between the third electrode plate and the fourth electrode plate; a rigid support layer is arranged on the side of the fourth electrode plate away from the third electrode plate. The first doped region and the second doped region are prepared by the same implantation process. The first cavity and the second cavity are prepared by the same etching process. The second electrode plate and the fourth electrode plate are arranged in the same layer. The first electrode plate is electrically connected to a first electrode, and the first electrode is insulated from the substrate; the second electrode plate is electrically connected to a second electrode. The third electrode plate is electrically connected to a third electrode, and the third electrode is insulated from the substrate; the fourth electrode plate is electrically connected to a fourth electrode.

2. The pressure sensor of claim 1, wherein, The first cavity and the second cavity are both parallelogram cavities, and each face of the parallelogram cavity is a crystal face, and the acute angle between adjacent crystal faces is 69-72 degrees.

3. The pressure sensor of claim 1, wherein, The acute angle is 70.52 degrees.

4. The pressure sensor of claim 1, wherein, One of the substrate and the first doped region is N-type, and the other is P-type; and / or, 5. The pressure sensor according to any one of claims 1 to 4, characterized in that One of the substrate and the second doped region is N-type, and the other is P-type.

6. The pressure sensor according to any one of claims 1 to 4, characterized in that The application relates to a substrate for a capacitor, comprising: providing a substrate, wherein a first capacitor region is formed in the substrate; a first doped region is formed in the substrate within a predetermined depth range of the first capacitor region by an implantation process, the first doped region serves as a first electrode plate of a first capacitor; a first cavity is formed on one side of the substrate by an etching process; a second electrode plate is formed on one side of the substrate, in the orthographic projection of the substrate, the first electrode plate, the second electrode plate and the first cavity at least partially overlap, and the first cavity is located between the first electrode plate and the second electrode plate; the substrate further comprises a second capacitor region; a second doped region is formed in the substrate within a predetermined depth range of the second capacitor region by the implantation process, the second doped region serves as a third electrode plate of a second capacitor; a second cavity is formed on one side of the substrate by the etching process; and a fourth electrode plate is formed on one side of the substrate, in the orthographic projection of the substrate, the third electrode plate, the fourth electrode plate and the second cavity at least partially overlap, and the second cavity is located between the third electrode plate and the fourth electrode plate.

7. The pressure sensor according to any one of claims 1 to 4, wherein ​ 8. The pressure sensor of claim 7, wherein, ​ 9. The pressure sensor according to any one of claims 1 to 4, wherein ​ ​ 10. A method of manufacturing a pressure sensor, characterized by, ​ ​ ​ ​ ​ ​ ​ ​ ​ forming a rigid support layer on the fourth electrode plate; forming a via hole on the rigid support layer and forming a conductive member in the via hole, the conductive member being electrically connected with the fourth electrode plate; forming a fourth electrode on the side of the rigid support layer away from the fourth electrode plate, the fourth electrode being electrically connected with the conductive member.

11. The manufacturing method according to claim 10, wherein The first cavity is formed on one side of the substrate by an etching process, and the second cavity is formed on the one side of the substrate by the etching process, specifically: forming an etching hole on the top of the substrate by etching, the etching hole having a depth less than the predetermined depth range; forming an etching protection layer on at least the sidewall and bottom surface of the etching hole; after forming the etching protection layer, continuing to etch the etching hole until the first doped region and the second doped region are reached; using a crystal face self-stop etching method, etching the substrate by the etching hole to form the first cavity and the second cavity.

12. The manufacturing method according to claim 11, wherein after forming the first cavity and the second cavity, filling the etching hole to seal the etching hole.

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