Radar signal processing device and method based on rfsoc chip real-time configuration

Abstract

The application discloses a radar signal processing device and method based on an RFSoC chip and capable of real-time configuration. The application integrates a DMA data transmission module, a data sending control module, a radio frequency data transceiving conversion module, a data preprocessing module and a data receiving buffer module into a single RFSoC chip, realizes integration of radio frequency signal transceiving, echo signal preprocessing and data transmission functions, and makes the device structure simple, easy to miniaturize and strong in reliability. The method of the application runs a Jupyter platform in the RFSoC processing module, maps current parameters and stored data of each module to a webpage interactive interface displayed on a host computer, is convenient for real-time modification, and enables users to customize a radar echo data processing algorithm in the interactive interface, so that the method of the application realizes synchronization of radar processing program writing and real-time verification.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of communication, and further relates to a radar signal processing device and method based on a radio frequency system on chip (RFSoC) chip that can be configured in real time. The radar signal processing device is used for intermediate frequency signal transmission and reception and digital signal processing of a radar system, and can control radar transmission waveforms and process received echo signals in real time through a Jupyter platform running in the device. BACKGROUND

[0002] The core function of a radar signal processing machine is to complete the processing function of radar signals, and the processing function mainly includes interference suppression, target detection and information extraction. With the development of digital radars, the radar signal processing machine is also responsible for sending modulated waveforms, receiving and storing radar echoes. Modern radar signal processing systems require faster processing speed, higher transmission bandwidth and better system architecture. The development trend mainly presents in three aspects: high-speed serial interconnection technology, field programmable gate array (FPGA) and digital signal processor (DSP) application technology, and system platform architecture.

[0003] Hubei Aerospace Technology Research Institute General Design Office discloses a radar signal processing system based on a VPX platform in its applied patent "Radar signal processing system based on VPX platform and application software design method" (application number: 201710323773.7, authorized publication number: CN 107167773 B). The system runs in a VPX processor, and the system includes a hybrid communication board, which integrates a multi-channel AD / DA and a Virtex-7 FPGA processor, is used for frequency modulation waveform control, signal acquisition and corresponding signal pre-processing work, and performs radar timing control; a general signal processing board, which integrates a multi-core DSP6678 processing architecture, is used for realizing high-performance computing, that is, a parallel system composed of multiple processors is used to realize high processing capability. The system has the following disadvantages: the whole system is not easy to miniaturize due to volume and power consumption limitations. Secondly, digital signals are transmitted between chips through multiple data buses, and the above buses are transmitted based on printed circuit boards, which not only makes it difficult to guarantee signal integrity, but also causes signal acquisition and transmission delay, affecting the overall processing efficiency of the system.

[0004] A technical solution of SAR imaging real-time signal processing is disclosed in the patent document "SAR imaging real-time signal processing device based on RFSoC chip" (application date: May 30, 2019, application number: 201910465065.6, application publication number: CN 110174672 A) applied by Xi'an University of Electronic Science and Technology. The radio frequency RF conversion unit in the technical solution is used for radio frequency signal transceiving, the clock unit provides the required clock of the system, the program loading unit is used for loading programs, the Ethernet interface unit is used for transmitting imaging result data, the internal cache unit is used for caching data, the wave control interface unit is used for configuring the front-end wave control system, and the radio frequency system on chip RFSoC chip unit is used for SAR imaging processing. The technical solution realizes synthetic aperture radar SAR imaging processing by taking a radio frequency system on chip RFSoC chip as a core processor: using the 4Gsps sampling rate analog-to-digital conversion functional component inside the radio frequency system on chip RFSoC chip to directly collect radar echo signals in the radio frequency band; then using the logic resources of the radio frequency system on chip RFSoC chip to perform digital down-conversion processing, decimation filter processing, pulse compression processing and other preprocessing procedures on the radar echo signals; then transferring the preprocessing results to the embedded processing unit inside the chip to perform SAR imaging; finally outputting the imaging result data through the gigabit Ethernet interface of the radio frequency system on chip RFSoC chip. The technical solution has two shortcomings: first, the functions and configurations of each module and unit are fixed with program loading, and this method has high software and hardware coupling degree, and cannot flexibly update functions and configurations. Second, the technical solution uses gigabit Ethernet only for radar imaging result data transmission, and cannot adjust the system working parameters in real time according to the imaging results. Overall, the technical solution cannot realize real-time modification and control of the parameters of modules such as the transmitting waveform and the radio frequency RF conversion unit according to needs, resulting in monotonous functions of the entire system, and the working mode cannot be quickly converted, and it is difficult to change the system parameters in real time and verify the algorithm online in real time according to different needs. SUMMARY

[0005] The idea for achieving the object of the present application is to realize the receiving, transmitting and processing of radar signals with a radio frequency system on chip (RFSoC) chip as the core. The above functions are realized by the single-chip RFSoC chip to solve the problems of complex structure and difficulty in miniaturization. The software interface abstracted from the logic part of the RFSoC chip by the ARM processing core integrated in the RFSoC chip is mapped to the webpage operation interface of the host computer together with the configuration parameters and waveform data, so as to solve the defects that the working mode cannot be quickly switched and the system parameters cannot be modified in real time. The analog-to-digital and digital-to-analog conversion functions integrated in the RFSoC chip are used to realize the transmission of radio frequency signals and the collection of radar echo signals. The start time of collection and transmission is kept aligned through a synchronization signal, and the signals are transmitted in the chip, solving the problems of signal asynchronization and unreliable data in the prior art. The ARM processor core integrated in the RFSoC chip is used to run the Jupyter platform to read the stored radar echo data, convert the data into a python array on the webpage operation interface, and save the data in the memory of the processor. The user can write a Python program on the webpage operation interface to process and verify the array containing the echo data, so as to solve the problem that the radar signal processing algorithm program cannot be verified in real time in the prior art.

[0006] The device of the present application comprises an RFSoC processing module, a DMA data transmission module, a data transmission control module, a radio frequency data transceiver conversion module, a data preprocessing module and a data receiving buffer module, which are built on the RFSoC chip.

[0007] The RFSoC processing module is used to read and transmit the parameters of the other modules and the waveform data of the DAC transmission control module in its memory. According to the program or the instruction of the host computer, the data reading instruction is transmitted. The echo data can also be processed using a user-defined algorithm.

[0008] The data transmission control module is used to store waveform data and transmit the waveform data at a pulse repetition frequency set by parameters, and output a synchronization signal to the receiving data buffer module for keeping the transmission and reception synchronized.

[0009] The radio frequency data transceiver conversion module is used to receive the parameters transmitted by the control signal. The radio frequency data transceiver conversion module converts the waveform data into radio frequency signals while converting the received echo radio frequency signals into echo data.

[0010] The preprocessing module is used to perform FIR filtering or pulse compression or no processing on the data when starting to receive the echo data according to the corresponding preprocessing mode, and transmit the processed data to the data receiving buffer module.

[0011] The data receiving buffer module is used for buffering the data sent by the preprocessing module, and sending the data according to the reading instruction of the DMA data transmission module.

[0012] The DMA data transmission module is used for receiving the data reading instruction of the RFSoC processing module, sending a reading signal to the data receiving buffer module, starting to read all the data stored in the data receiving buffer module, and transferring the data to the memory of the RFSoC processing module.

[0013] The steps of the radar signal processing method of the application include the following:

[0014] Step 1: The RFSoC processing module reads the remaining module parameters in its memory and the waveform data of the DAC sending control module, sends the read parameters, and transmits the waveform data of the DAC sending control module to the sending control module; each time the module parameters and the waveform data of the DAC sending control module are sent, the configuration parameters and the state of each module are read, and the above parameters are mapped to the RFSoC processing module as the parameters for interaction with the upper computer;

[0015] Step 2: The data sending control module reads the data corresponding to the actual physical address in the BRAM or DDR and sends it; a clock cycle width pulse is output at the starting moment after each reset; the actual physical address refers to the address obtained by adding the base address of data storage and the counter value at the current time;

[0016] Step 3: According to the parameters transmitted by the radio frequency data transceiver conversion module control signal, the radio frequency data transceiver conversion module converts the waveform data into a radio frequency signal while converting the received echo radio frequency signal into echo data;

[0017] Step 4: The preprocessing module selects the corresponding preprocessing mode according to the preprocessing module control signal, starts to perform FIR filtering or pulse compression or no processing on the data when receiving the echo data; sends the processed data to the data receiving buffer module; the data receiving buffer module buffers the sent data;

[0018] Step 5: The RFSoC processing module sends a data reading instruction according to the program or the instruction of the upper computer; after receiving the data reading instruction of the RFSoC processing module, the DMA data transmission module sends a reading signal to the data receiving buffer module, starts to read all the data stored in the data receiving buffer module, and transfers the data to the memory of the RFSoC processing module;

[0019] Step 6: The signal data in the memory of the RFSoC processing module is processed by a user-defined algorithm. In the web interface of the host computer, the user can use the echo data collected in the memory of the RFSoC processing module by calling variables. By entering the calculation function for the above variables in a specific program input box, real-time processing can be achieved. The processed result is saved in memory and displayed directly through the interface.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] First, the device of the present invention uses an RFSoC chip as the core to perform analog-to-digital conversion, signal processing and control of radar echo signals. This overcomes the shortcomings of the existing technology, which uses a multi-chip structure of multiple analog-to-digital and digital-to-analog converter chips, a programmable gate array (FPGA) chip and multiple digital signal processor (DSP) chips, resulting in a complex structure, large size and high power consumption. As a result, the device of the present invention has a simple structure, small size and is easy to miniaturize.

[0022] Secondly, the device of this invention uses an RF-SoC chip to directly sample radio frequency signals. The parameters of the RF sampling module can be configured to achieve functions such as digital up-conversion, digital down-conversion, and decimation filtering. Simultaneously, the logic section of the RFSoC chip enables on-chip synchronization between sampling and transmission, avoiding data asynchrony and signal susceptibility to interference caused by varying copper wire connection lengths between different chips. This overcomes the shortcomings of existing technologies, such as signal asynchrony and unreliable data, ensuring that the radar echo signal data acquired by this invention remains synchronized with a low bit error rate and high reliability.

[0023] Third, the method of the present invention overcomes the shortcomings of the prior art in that the working mode cannot be quickly switched and the system parameters cannot be modified in real time by mapping the control parameters and data of each module to the display interface of the Jupyter platform running in the ARM processing core integrated in the RFSoC chip. This makes the present invention applicable to radar transmitting and processing radar signals in a variety of different scenarios.

[0024] Fourth, the method of this invention converts the acquired digital signals into an array format required for computation on the Jupyter platform. Users can directly write Python programs through a web interface on a host computer to perform real-time computations on the digital signal arrays and display the results. This allows the digital signal processing program to be modified and run online in real time. It overcomes the limitation of existing radar signal processing algorithms that cannot be verified online in real time, enabling the method of this invention to be used for radar system verification. Users can verify the implementation effect while writing the radar processing program. Attached Figure Description

[0025] Figure 1This is a block diagram of the device structure of the present invention;

[0026] Figure 2 This is a schematic diagram of the internal structure of the radio frequency data transceiver conversion module of the present invention;

[0027] Figure 3 This is a flowchart of the method of the present invention;

[0028] Figure 4 This is a connection diagram of the radio frequency circuit of the present invention;

[0029] Figure 5 (a) is a top view of the test scenario of the monopulse radar in the experiment of this invention;

[0030] Figure 5 (b) is the range-amplitude diagram of the echo signal measured under the simulated single-pulse radar usage state in the experiment of this invention. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0032] refer to Figure 1 The apparatus of the present invention will be further described in conjunction with the embodiments.

[0033] The present invention relates to a radar signal processing device based on an RFSOC chip that can be configured in real time, comprising an RFSoC processing module, a DMA data transfer module, a data receiving buffer module, a data preprocessing module, a data transmission control module, and an RF data transceiver conversion module. The RFSoC processing module is implemented using an ARM multi-core processor integrated in the RFSoC chip, and the remaining modules are implemented using a field-programmable gate array (FPGA).

[0034] The RFSoC processing module is used to read and send parameters from other modules in its memory and waveform data from the DAC transmission control module; it also sends data read commands according to the program or the host computer's instructions; and it can process echo data using user-defined algorithms. This module is implemented by running the Jupyter platform on an ARM multi-core processor. The host computer can connect to the Jupyter platform via a gigabit Ethernet port and access the RFSoC processing module through a web page to transmit control signals and data. Without a host computer connection, the RFSoC processing module can also run independently, reading the configuration stored in memory for use as parameters and data for other modules. Furthermore, users can write and run Python algorithm programs within the RFSoC processing module for processing radar echo data.

[0035] The aforementioned RF data transceiver module is used to receive parameters for control signal transmission. Simultaneously, the module converts waveform data into RF signals and the received echo RF signals into echo data. This module can simultaneously receive and transmit eight RF signals, connected to the RF amplifier and antenna via a total of 16 SMA RF cables.

[0036] refer to Figure 2 The internal structure of the radio frequency data transceiver conversion module in the device of the present invention will be further described.

[0037] The RF data transceiver module includes eight analog-to-digital converters (ADCs) and eight digital-to-analog converters (DACs). Each converter is connected to a digital down-converter (DDC) or digital up-converter (DUC) for mutual conversion between RF analog signals and digital data signals. The module's sampling clock is input from an external sampling clock chip. This sampling clock frequency is fixed. Based on the different sampling frequencies used by the ADCs and DACs, the RF data transceiver module divides the input sampling clock to obtain the sampling clocks for the ADCs and DACs. The module controls these devices via control signals transmitted through the AXI-Lite interface. Digital signals are transmitted through the AXI-Stream interface to realize the data transmission of sampling signals between the ADCs and DACs. Control parameters include: sampling rate of the ADCs and DACs, data clock frequency of the ADCs and DACs, decimation factor of the ADCs, interpolation factor of the DACs, and mixing frequency of the digital up-converters and down-converters.

[0038] The data preprocessing module is used to perform FIR filtering, pulse compression, or no processing on the received echo data according to the corresponding preprocessing method; and to send the processed data to the data receiving buffer module; the preprocessing method is controlled by the signal transmitted through the AXI-Lite interface, and the sampled data is transmitted through the AXI-Stream interface.

[0039] The data transmission control module stores waveform data and transmits it at a pre-defined pulse repetition frequency. Simultaneously, it outputs a synchronization signal to the receiving data buffer module to maintain transmission and reception synchronization. The storage location for the data required for DAC transmission can be either the chip's internal BRAM or a connected DDR4 memory chip. The former is a logic resource with fast storage speed but limited space. The latter has a larger data storage space but requires an additional DDR4 chip, making it suitable for situations where a single pulse signal is large. The pulse repetition frequency and the data storage location required for DAC transmission are controlled by signals transmitted through the AXI-Lite interface, and the stored data is transmitted via the AXI-Stream interface.

[0040] The received data buffer module is used to buffer the data sent by the preprocessing module and send data according to the read command of the DMA data transfer module. The storage location of the received data can be selected as the BRAM inside the chip or the DDR4 memory chip connected to the chip. The data storage location is controlled by the signal transmitted by the AXI-Lite interface, and the stored data is transmitted by the AXI-Stream interface.

[0041] The DMA data transfer module receives data read commands from the RFSoC processing module, sends a read signal to the data receive buffer module, begins reading all data stored in the data receive buffer module, and transfers the data to the memory of the RFSoC processing module. Data transfer between the DMA data transfer module and the RFSoC processing module uses an AXI-4 bus interface, while data transfer with the data receive buffer module and the data transmission control module uses an AXI-Stream interface.

[0042] refer to Figure 3 The implementation steps of the method of the present invention will be further described in conjunction with the embodiments.

[0043] Step 1, Transmit control commands and module data:

[0044] The RFSoC processing module reads the parameters of the other modules and the waveform data of the DAC transmit control module from its memory, sends the read parameters, and transmits the waveform data of the DAC transmit control module to the transmit control module. Each time the module parameters and the waveform data of the DAC transmit control module are sent, the configuration parameters and status of each module are read, and then the above parameters are mapped into the RFSoC processing module as parameters for interaction with the host computer.

[0045] The waveform data is transmitted via the AXI-4 bus and the DMA data transfer module, converting the waveform data required by the data transmission control module into an AXI-Stream data stream signal. If the data storage address parameter of the data transmission control module is configured for BRAM storage, the waveform data is stored in the storage space generated by the BRAM core. If the data storage address parameter of the data transmission control module is configured for DDR storage, the waveform data is converted into AXI-4 bus data, and the data bit conversion is performed by the AXI-SmartConnect core before being sent to the DDR4-MIG core for data storage on the external DDR4 chip. The storage address is fixed at 0x0000 0000-0x1FFF FFFF, with a maximum storage capacity of 512MB of waveform data. The maximum data transmission amount per DAC interface is 64MB.

[0046] In the embodiments of the present invention, the AXI-4 bus adopts a high-performance memory-mapped bus.

[0047] In the embodiments of the present invention, the AXI4-Lite bus is a subset of the AXI4 bus and is dedicated to communication between control registers within components.

[0048] In the embodiments of the present invention, the AXI4-Stream data stream is a bus used to transmit large amounts of streaming data.

[0049] The BRAM core is a custom RAM resource for FPGA, with a large storage space. It is arranged in an array inside the FPGA and is the main part of the FPGA to implement various storage functions.

[0050] The DDR-MIG core refers to the memory controller. The physical interface of the IP core is connected to the memory, and the writing and reading of data are controlled through the AXI-4 bus.

[0051] Step 2, output waveform data and synchronization signal:

[0052] The data transmission control module reads data from the corresponding physical address in BRAM or DDR and transmits it. At the beginning of each reset, the transmit / receive synchronization signal outputs a pulse one clock cycle wide.

[0053] The actual physical address refers to the address obtained by adding the base address of the data storage to the counter value at the current moment.

[0054] The current counter value refers to the value of the counter in each clock cycle. The single pulse length parameter value of the data transmission control module is n. When the state of the RF output switch register of the transmission control module is "1", the counter value in the module is incremented by 1 in each clock cycle. When the counter data accumulates to n-1, the counter is reset to 0.

[0055] The output of a pulse with a width of one clock cycle means that the signal changes from state "0" to "1", remains for one clock cycle, and then changes back to "0".

[0056] In this embodiment of the invention, transmit and receive synchronization means that the output time of the radio frequency waveform data (digital signal) is the same as the start time of the acquisition of the radio frequency echo signal (digital signal). There is a small clock delay, i.e., system error, in the logical conversion process of the data. However, this system error is fixed and controllable. It can be calibrated by looping through an external cable of known length.

[0057] Step 3, conversion between radio frequency signals and data:

[0058] According to the parameters controlling signal transmission of the RF data transceiver module, the module converts waveform data into RF signals and simultaneously converts the received echo RF signals into echo data. Based on the parameter configuration, the RF data transceiver module sets the mixing frequencies of the digital oscillators corresponding to the eight ADC converters and eight DAC converters. The single-frequency digital signal output from the oscillators of the ADC converters is multiplied by the sampled data of the RF analog signal input to the RF data transceiver module, and filtered to obtain the down-converted data. Then, according to the configured decimation rate, the down-converted signal is resampled and output as data. The waveform data input to the RF data transceiver module is upsampled according to the configured interpolation factor, then multiplied by the single-frequency digital signal output from the oscillators of the DAC converters, filtered, and converted into an RF analog signal by the DAC converter, thus realizing the output and acquisition of RF signals. The input sampling clock is multiplied and divided for data processing.

[0059] The conversion of waveform data into radio frequency signals refers to setting up a DAC converter and outputting radio frequency signals based on the upconversion frequency and interpolation multiple parameters of the radio frequency data transceiver conversion module to control signal transmission.

[0060] The process of converting the received echo radio frequency signal into echo data refers to converting the received radio frequency signal into echo data by configuring the ADC converter according to the down-conversion frequency and decimation factor of the radio frequency data transceiver conversion module to control the signal transmission.

[0061] The aforementioned sampling clock multiplication and division refer to the RF data transceiver module multiplying the sampling clock output from the sampling clock chip to the sampling clock frequency configured by the RF data transceiver module's control signal, so that the DAC converter and ADC converter can operate at the required sampling rate. Secondly, the RF data transceiver module also divides the sampling clock according to the sampling frequency and decimation factor, using it as the clock signal for the AXI4-Stream data stream to ensure the synchronization of data processing throughout the system.

[0062] In the embodiments of the present invention, upconversion refers to digital upconversion, which modulates the baseband signal to a medium-to-high frequency using a digital method.

[0063] In the embodiments of the present invention, downconversion refers to digital downconversion, which converts radio frequency (high frequency) or intermediate frequency signals into baseband signals.

[0064] Step 4, Echo RF Data Reception and Processing:

[0065] The preprocessing module selects the appropriate preprocessing method based on the control signal, performing FIR filtering, pulse compression, or no processing on the data when it begins receiving echo data. The processed data is then sent to the data receiving buffer module, which buffers the incoming data.

[0066] The preprocessing mentioned refers to the process where the echo data output from the RF data transceiver module is first transmitted to the data preprocessing module for preprocessing. The preprocessing module is configured via a control signal. When configured in no-processing mode, the echo data undergoes no processing and is directly transmitted to the data receiving buffer module. When configured in pulse compression mode, the data preprocessing module receives parameters such as signal bandwidth, signal frequency, and number of data sampling points from the control signal and generates a corresponding frequency domain reference signal based on these parameters. In the preprocessing module, the echo data first undergoes FFT processing to convert it to a frequency domain signal. Then, it is multiplied by the aforementioned frequency domain reference signal and subjected to IFFT to obtain the pulse compression result, which is then output to the next stage. When configured in filtering mode, the echo data undergoes filtering processing through an FIR filter core, which stores the configured filter parameters. The filtered data is then output to the next stage.

[0067] The buffering of incoming data refers to the following process: when the data receiving buffer module receives a transmit / receive synchronization signal in state "1", the module begins to save the received data into BRAM or DDR according to the receive mode state setting. When the storage location is full, it stops receiving data and waits for the DMA module's read signal. If the transmit / receive synchronization signal is in state "1" during the waiting period, the above steps are repeated to start receiving data, and the newly received data overwrites the previously saved data. There are two receive modes: single-pulse receive mode and continuous receive mode. The mode used is determined by the control signal of the data receiving buffer module. In single-pulse receive mode, the internal BRAM resources are used as buffer storage. The data length stored in the BRAM is changed by controlling the echo signal length parameter. Each newly arrived echo data overwrites the previously received echo data, meaning the latest echo data is always stored in the BRAM. In continuous receive mode, data is stored in the DDR chip via the AXI-4 bus. Because the DDR chip has a large storage capacity, it can continuously store data from multiple pulses. The addresses stored in the DDR are 0x2000 0000-0x7FFF FFFF. When the RFSoC processing module needs the current data, it sends a receive preparation instruction through the DMA data transfer module and waits for the data receive buffer module to send data. After receiving the instruction from the DMA module, the data receive buffer module starts sending all the data at the current data storage location. After the data is sent, it continues the previous data receiving work.

[0068] In the embodiments of the present invention, the reference signal refers to a linear frequency modulated signal. The above-mentioned pulse compression preprocessing mode can only be used when the waveform data is a linear frequency modulated wave.

[0069] In embodiments of the present invention, pulse compression processing involves multiplying the input signal's FFT by the conjugate of the reference signal's FFT and then performing an inverse FFT. The conjugate of the reference signal's FFT is obtained directly through the parameters of the control signal because its formula is fixed.

[0070] In the embodiments of the present invention, FFT refers to Fast Discrete Fourier Transform, which is implemented through an FFT kernel.

[0071] In the embodiments of the present invention, IFFT refers to Fast Discrete Inverse Fourier Transform, which is implemented through an FFT kernel.

[0072] Step 5, read cached data:

[0073] The RFSoC processing module sends data read commands according to the instructions of the program or the host computer. After receiving the data read command from the RFSoC processing module, the DMA data transfer module sends a read signal to the data receive buffer module, begins reading all the data stored in the data receive buffer module, and transfers the data to the memory of the RFSoC processing module.

[0074] Step 6, Post-processing of echo data:

[0075] The signal data in the RFSoC processing module's memory is processed by a user-defined algorithm. In the web interface of the host computer, the user can use the echo data collected in the RFSoC processing module's memory by calling variables. By entering the calculation function for the above variables in a specific program input box, real-time processing can be achieved. The processed results are saved in memory and displayed directly through the interface.

[0076] The effectiveness of this invention can be further demonstrated through the following simulation experiments.

[0077] 1. Simulation experimental conditions:

[0078] The hardware platform for the simulation experiment of this invention is: an RFSOC hardware platform equipped with an XCZU28DR chip, which contains one RFSOC, one radio frequency clock chip and eight DDR4 memory chips.

[0079] The software platform for the simulation experiment of this invention is the Windows 11 operating system.

[0080] 2. Simulation content and result analysis:

[0081] The simulation experiment of this invention uses the device and method of this invention. A simple radio frequency circuit is connected to the radio frequency interface of the device to realize the function of S-band monopulse radar. The connection relationship of the radio frequency circuit is as follows: Figure 4 As shown. In Figure 5 A monopulse radar test experiment was conducted on the scenario shown in (a), and the results were as follows: Figure 5 The test results are shown in (b).

[0082] The monopulse radar implemented in this experiment uses a single-receive, single-transmit mode. The RF input and output interfaces are connected to two sets of RF circuits, with the RF transmitting circuit connected as follows:

[0083] The RF signal output by the RFSoC first passes through a 10dB attenuator, then through a 3000-4000MHz bandpass filter, and finally through a 40dB power amplifier to amplify the RF signal and extend the radar's detection range. The signal is then transmitted through a horn antenna, and the echo signal reflected from objects in space is received by the horn antenna at the receiver. The echo signal is first filtered using a 3000-4000MHz bandpass filter, then amplified by a low-noise amplifier with a 20dB amplification factor. The amplified signal is then input to the RFSoC chip for acquisition.

[0084] In this simulation experiment, a computer is used to connect to the device described in this invention via a network cable, and parameters are configured on a web interface.

[0085] The parameters for this simulation experiment are set as follows: the transmitted waveform uses a linear frequency modulated wave; the signal bandwidth is 100MHz; the starting frequency of the transmitted signal is 200MHz; the transmitted pulse period is 0.4ms; the pulse repetition frequency is 1KHz; the up-conversion frequency of the transmitted signal is 3500MHz; the interpolation factor is 1x; the down-conversion frequency of the echo signal is 3700MHz; the decimation factor is 2x; the echo data reception is in single-pulse mode; the preprocessing mode is no processing; and the transmitted data is stored in BRAM.

[0086] In this simulation experiment, a pulse compression algorithm was written in the post-processing program editor on a web page. The echo data was pulse compressed within the RFSOC processing module, and the processed result was directly displayed on the web page. The processed result was saved and exported to a computer for viewing.

[0087] The following is combined Figure 5 (a) and Figure 5 (b) The image further illustrates the effects of the present invention.

[0088] Figure 5 (a) is a top view of the test scenario for a monopulse radar. Figure 5(a) The start and end points of the range measuring ruler represent the placement positions of the radar's transmitting and receiving antennas, respectively. The scale of the range measuring ruler represents the distance relationship between each target point and the antenna position.

[0089] Figure 5 (b) is the range-amplitude diagram of the echo signal measured under the simulated monopulse radar operating conditions of this invention. Figure 5 (b) marks the amplitude of three obvious peak points and the calculated distance values. In the marked points, X represents the target distance measured by the radar, and Y represents the intensity of the reflected signal from the object.

[0090] By comparing the two images above, we can... Figure 5 The peak points marked in (b) and Figure 5 The objects in (a) correspond one-to-one. Figure 5 Figure 5 (b) The distances below the peak points marked in the figure correspond from left to right to the distance difference between the two speaker placement positions in 5(a), the cars parked on the road, and the buildings. The target distances obtained by the echo measurement are basically consistent with the actual spatial distances.

[0091] Based on the simulation results above, the device and method of the present invention can quickly realize the function of a single-pulse radar, and the implementation process is simple to operate. Various parameters and functions of the radar can be configured only through a web page; the algorithm program can also be written online to process the signal in real time, which greatly speeds up the verification speed of the radar system.

Claims

1. A radar signal processing device based on an RFSOC chip with real-time configurability, comprising an RFSOC processing module, a DMA data transmission module, a data transmission control module, an RF data transceiver conversion module, a data preprocessing module, and a data receiving buffer module, characterized in that, These six modules are built on the RFSOC chip, among which: The RFSoC processing module is used to read and send the configuration parameters of the other modules in its memory and the waveform data of the DAC transmission control module; it also sends data reading instructions according to the program or the host computer's instructions; and it processes the echo data using a user-defined algorithm program. The data transmission control module is used to store waveform data and transmit waveform data at a preset pulse repetition frequency, while simultaneously outputting a synchronization signal to the receiving data buffer module to maintain transmission and reception synchronization. The radio frequency data transceiver conversion module is used to receive parameters for control signal transmission. While converting waveform data into radio frequency signals, the radio frequency data transceiver conversion module also converts the received echo radio frequency signals into echo data. The preprocessing module is configured to perform FIR filtering, pulse compression, or no processing on the data when the echo data is first received, according to the corresponding preprocessing method settings; and send the processed data to the data receiving buffer module. The data receiving buffer module is used to buffer the data sent by the preprocessing module and send the data according to the read instruction of the DMA data transmission module. The DMA data transfer module is used to receive data read instructions from the RFSoC processing module, send a read signal to the data receive buffer module, start reading all the data stored in the data receive buffer module, and transfer the data to the memory of the RFSoC processing module.

2. A radar signal processing method based on an RFSOC chip with real-time configurability according to the device described in claim 1, characterized in that, The parameters are mapped to the interactive interface of the host computer for easy real-time modification, and the user-defined algorithm processes the data; the processing method includes the following steps: Step 1: The RFSoC processing module reads the parameters of the other modules and the waveform data of the DAC transmit control module from its memory, sends the read parameters, and transmits the waveform data of the DAC transmit control module to the transmit control module. Each time the module parameters and the waveform data of the DAC transmit control module are sent, the configuration parameters and status of each module are read, and the above parameters are mapped into the RFSoC processing module as parameters for interaction with the host computer. Step 2: The data transmission control module reads the data corresponding to the actual physical address in BRAM or DDR and transmits it; at the beginning of each reset, the transmit / receive synchronization signal outputs a pulse with a clock cycle width; the actual physical address refers to the address obtained by adding the base address of the data storage to the counter value at the current moment; Step 3: According to the parameters of the RF data transceiver conversion module for controlling signal transmission, the RF data transceiver conversion module converts waveform data into RF signals and simultaneously converts the received echo RF signals into echo data. Step 4: The preprocessing module selects the appropriate preprocessing method according to the control signal of the preprocessing module. When the echo data is received, the data is either FIR filtered, pulse compressed, or not processed. The processed data is sent to the data receiving buffer module. The data receiving buffer module buffers the incoming data. Step 5: The RFSoC processing module sends a data read instruction according to the program or the host computer's instructions; after receiving the data read instruction from the RFSoC processing module, the DMA data transfer module sends a read signal to the data receive buffer module, starts reading all the data stored in the data receive buffer module, and transfers the data to the memory of the RFSoC processing module. Step 6: The signal data in the memory of the RFSoC processing module is processed by a user-defined algorithm. In the web interface of the host computer, the user can use the echo data collected in the memory of the RFSoC processing module by calling variables. By entering the calculation function for the above variables in a specific program input box, real-time processing can be achieved. The processed result is saved in memory and displayed directly through the interface.

3. The radar signal processing method based on an RFSOC chip with real-time configurability according to claim 2, characterized in that, The counter value mentioned in step 2 refers to the value of the counter in each clock cycle. The single pulse length parameter value of the data transmission control module is n. When the state of the RF output switch register of the transmission control module is "1", the counter value in the module is incremented by 1 in each clock cycle. When the counter data accumulates to n-1, the counter is reset to 0.

4. The radar signal processing method based on an RFSOC chip with real-time configurability according to claim 2, characterized in that, The output of a pulse with a clock cycle width in step 2 means that the signal changes from state "0" to "1", holds for one clock cycle, and then changes back to "0".

5. The radar signal processing method based on an RFSOC chip with real-time configurability according to claim 2, characterized in that, The conversion of waveform data into radio frequency signals in step 3 refers to setting up the DAC converter and outputting radio frequency signals according to the upconversion frequency and interpolation multiple parameters of the control signal transmission of the radio frequency data transceiver conversion module.

6. The radar signal processing method based on an RFSOC chip with real-time configurability according to claim 2, characterized in that, Step 3, which involves converting the received radio frequency signal into echo data, refers to configuring the ADC converter according to the down-conversion frequency and decimation factor of the radio frequency data transceiver conversion module to control the signal transmission, and then converting the radio frequency signal into echo data.

7. The radar signal processing method based on an RFSOC chip with real-time configurability according to claim 2, characterized in that, The buffering of incoming data in step 4 refers to the following: when the data receiving buffer module receives a transmit / receive synchronization signal in state "1", the module starts to save the received data to BRAM or DDR according to the receive mode state setting. When the above storage location is full, it stops receiving data and waits for the read signal from the DMA module. If the transmit / receive synchronization signal is in state "1" during the waiting period, the above steps are repeated to start receiving data, and the newly received data overwrites the previously saved data.

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