A layout structure of a silicon-based liquid crystal display driving circuit

Abstract

The application provides a part layout structure of a silicon-based liquid crystal display driving circuit, which comprises a plurality of minimum pixel matrix units, each of which is composed of four identical pixel units, the four pixel units are arranged in 2*2, and are axisymmetric along the vertical axis and the horizontal axis, and the four pixel units share a power supply in the minimum pixel matrix unit, which greatly reduces the area of the pixel, and in addition, adjacent pixel matrix units also share a signal port, and high resolution can be realized through multiplexing of the basic units.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of silicon-based liquid crystal display driving, and particularly relates to a layout structure of a silicon-based liquid crystal display driving circuit. BACKGROUND

[0002] The silicon-based liquid crystal display driving circuit (LCOS) is a silicon-based liquid crystal chip core circuit, and a pixel unit is the most important basic unit in the chip. The silicon-based liquid crystal technology provides an effective idea for low-cost manufacturing of high-resolution micro displays by combining mature CMOS technology and liquid crystal manufacturing technology, and therefore has attracted much attention in recent years. The overall circuit of a silicon-based liquid crystal includes a digital driving circuit and an analog circuit. The function of the digital circuit is to generate a row scanning signal and column data, and to transmit the signals to the analog circuit. The analog circuit includes a display pixel matrix, a level conversion circuit, a signal buffer circuit, a D flip-flop and a temperature sensor.

[0003] The layout design is realized by a Cadence IC tool. The task of the layout design is to design a photolithography mask corresponding to the circuit according to a constraint file (DRC\LVS, etc.) of the process. This process is performed after the function and performance verification of all the circuits are completed. A LCOS display driving chip contains about hundreds of thousands or even millions of transistors, and such a large number of transistors is realized by reuse of basic module units. The layout design process is divided into several stages, such as division, layout planning, layout and routing, by the technical personnel.

[0004] The layout planning occupies an important position in the whole layout design. The basis of the layout planning is the function to be realized by the chip, pin requirements, distribution of power supply and ground, etc. The layout is to determine the specific position of the module on the chip, so as to reasonably allocate the space of the signal lines and the power supply lines. The routing needs to satisfy the mutual connection between the modules and between the devices, and also needs to optimize the routing to improve the electrical performance. In the specific design process, the position of the module, the size of the module, the number of the modules and the wiring between the modules need to be considered. Finally, the verification is needed, and the contents of the verification are whether the circuit connection is wrong, whether the design rules of the process subscription are violated, and whether there is an error in the electrical performance.

[0005] The resolution size of an LCOS chip depends on the number of pixel units integrated on a single chip, and the more pixel units integrated on a chip, the larger the resolution of the LCOS. In the case of a very limited area, in order to improve the resolution of the LCOS, the size of the pixel unit must be reduced to integrate more pixel units, so the requirements for the layout of the pixel module and the routing of the signals are extremely strict. In addition, the area of an LCOS chip is very large, and both the power lines and the signal lines must cross a long distance, which will cause a large IR drop, that is, signal attenuation and power attenuation, so it is also very important to solve these problems through the layout of the layout.

[0006] The current pixel layout scheme in the prior art basically uses a single pixel unit to be powered through a separate power ground port. Such a layout will limit the layout of the device, so that the area of the pixel cannot be reduced. SUMMARY

[0007] In order to solve the above problems existing in the prior art, the present application provides a layout structure of a silicon-based liquid crystal display driving circuit. The technical problem to be solved by the present application is solved by the following technical scheme:

[0008] The layout structure of the silicon-based liquid crystal display driving circuit provided by the present application comprises: a plurality of minimum pixel matrix units, each minimum pixel matrix unit being composed of 4 identical pixel units, the 4 pixel units being arranged in 2*2 and being axisymmetric on the vertical and horizontal axes, and being respectively a left upper pixel unit 201, a right upper pixel unit 202, a left lower pixel unit 203 and a right lower pixel unit 204;

[0009] The left upper pixel unit 201 and the right upper pixel unit 202 share a ground terminal GND and a first address terminal GATE1, and the left lower pixel unit 203 and the right lower pixel unit 204 share a ground terminal GND and a second address terminal GATE2; the 4 pixel units share a power terminal VDD;

[0010] The left upper pixel unit 201 and the left lower pixel unit 203 share a first data terminal DATA1, and the right upper pixel unit 202 and the right lower pixel unit 204 share a second data terminal DATA2.

[0011] Optionally, the maximum resolution of the LCOS of the silicon-based liquid crystal display driving circuit is 4096*256. The minimum pixel matrix unit is n*m;

[0012] Wherein, n is the number of columns of the minimum pixel matrix unit, and m is the number of rows of the minimum pixel matrix unit, the maximum value of n is 256, the maximum value of m is 4096, and the size of each pixel unit is 3um*4.2um.

[0013] Optionally, the ground terminals GND of the adjacent row minimum pixel matrix units are shared, the address terminals GATE of the same row minimum pixel matrix units are shared, and the data terminals DATA and the power supply terminals VDD of the same column minimum pixel matrix units are shared.

[0014] Optionally, each pixel unit is composed of MOS switches M0, M1, M2, M3, M4 and M5.

[0015] The source terminal of M0 is connected with the substrate terminal and is connected to the power supply terminal VDD, the gate terminal of M0 is connected with the gate terminal of M3, the drain terminal of M5, the drain terminal of M4 and the drain terminal of M2, and serves as an output terminal OUT; the drain terminal of M0 is connected with the gate terminal of M4, the gate terminal of M2 and the drain terminal of M1; the source terminal of M4 is connected with the substrate terminal and is connected to the power supply terminal VDD; the substrate terminal of M3 is connected with the source terminal of M3 and is connected to the ground terminal GND; the substrate terminal of M5 is connected with the source terminal of M5 and is connected to the ground terminal GND; the substrate terminal of M4 is connected with the source terminal of M4 and is connected to the ground terminal GND; the substrate terminal of M2 is connected with the source terminal of M2 and is connected to the ground terminal GND; the source terminal of M1 serves as a data terminal DATA, and the gate terminal serves as an address terminal GATA; and the gate terminal of M5 serves as a reset terminal RST.

[0016] Optionally, in each of the pixel matrix units, the source terminal of M1 in the upper left pixel unit 201 is shared with the source terminal of M1 in the lower left pixel unit 203; the gate terminal of M1 in the upper left pixel unit 201 is shared with the gate terminal of M1 in the upper right pixel unit 202; the source terminal of M1 in the upper right pixel unit 202 is shared with the source terminal of M1 in the lower right pixel unit 204; and the gate terminal of M1 in the upper left pixel unit 203 is shared with the gate terminal of M1 in the upper right pixel unit 204.

[0017] The present application has the following beneficial effects:

[0018] The present application provides a partial layout structure of a silicon-based liquid crystal display driving circuit, which comprises a plurality of minimum pixel matrix units, each of which is composed of four identical pixel units arranged in 2*2 and axially symmetrical in the vertical and horizontal axes, and the adjacent pixel units share the power supply in the minimum pixel matrix unit, the four pixel units share the power supply, which greatly reduces the area of the pixel, and the adjacent pixel matrix units also share a signal port, and the high resolution can be realized through the multiplexing of the basic units.

[0019] The present application will be further described in detail in combination with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1is a part layout structure schematic diagram of a silicon-based liquid crystal display driving circuit provided by an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a minimum pixel matrix unit provided by an embodiment of the present application;

[0022] Figure 3 is a layout printing schematic diagram provided by an embodiment of the present application;

[0023] Figure 4 is a circuit internal schematic diagram of each minimum pixel matrix unit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application will be further described in detail below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0025] As shown in the drawings, Figure 1 the layout structure of the silicon-based liquid crystal display driving circuit provided by the present application comprises: a plurality of minimum pixel matrix units, each minimum pixel matrix unit is composed of 4 identical pixel units, the 4 pixel units are arranged in 2*2, and are axisymmetric on the vertical axis and the horizontal axis, and are respectively a left upper pixel unit 201, a right upper pixel unit 202, a left lower pixel unit 203, and a right lower pixel unit 204.

[0026] It is worth noting that: by sharing the power supply ground, the area occupied by a single pixel is greatly saved, so that the size of the pixel can be compressed to 3um*4.2um. And such a layout can make the spacing between two adjacent pixels 0.2um without violating the rules set by the process. Through one-dimensional extension of a single pixel in the X and Y directions, the entire pixel unit array can be obtained.

[0027] Referring to Figure 2 , the left upper pixel unit 201 and the right upper pixel unit 202 share a ground terminal GND and a first address terminal GATE1, and the left lower pixel unit 203 and the right lower pixel unit 204 share a ground GND and a second address terminal GATE2; the 4 pixel units share a power supply terminal VDD.

[0028] The left upper pixel unit 201 and the left lower pixel unit 203 share a first data terminal DATA1; the right upper pixel unit 202 and the right lower pixel unit 204 share a second data terminal DATA2.

[0029] The minimum pixel matrix unit is n*m;

[0030] The maximum resolution of the LCOS of the silicon-based liquid crystal display driving circuit is 4096*256. n is the column number of the minimum pixel matrix unit, m is the row number of the minimum pixel matrix unit, the maximum value of n is 256, and the maximum value of m is 4096. The size of each pixel unit is 3 μm*4.2 μm.

[0031] The one-dimensional extension of the pixel unit to the X and Y directions can obtain the array structure of the display driving circuit. Referring to Figure 1 , there are n=256 columns and m=2048 rows in total, according to Figure 1 It can be seen that the GATE ends of the pixels in the same row (n=1, m=1 and n=2, m=1... n=2, m=256) are connected together; the GATE ends of the pixels in the same row (201, 202) are connected together. The GND of the adjacent pixel units (n=1, m=1 and n=1, m=2) is shared. The VDD and DATA of the pixels in each column (n=1, m=1 and n=1, m=2... n=1, m=2048) are connected.

[0032] In combination with Figures 1-3 , the ground ends GND of the minimum pixel matrix units in adjacent rows are shared, the minimum pixel matrix units in the same row share the address ends GATE, and the minimum pixel matrix units in the same column share the data ends DATA and the power supply ends VDD.

[0033] As shown in Figure 4 , each pixel unit is composed of MOS switches M0, M1, M2, M3, M4 and M5;

[0034] The source end of M0 is connected to the substrate end and connected to the power supply end VDD, the gate end of M0 is connected to the gate end of M3, the drain end of M5, the drain end of M4, the drain end of M2, and serves as an output end OUT; the drain end of M0 is connected to the gate end of M4, the gate end of M2 and the drain end of M1; the source end of M4 is connected to the substrate end and connected to the power supply end VDD; the substrate end of M3 is connected to the source end and connected to the ground end GND; the substrate end of M5 is connected to the source end and connected to the ground end GND; the substrate end of M4 is connected to the source end and connected to the ground end GND; the substrate end of M2 is connected to the source end and connected to the ground end GND; the source end of M1 serves as a data end DATA, the gate end serves as an address end GATA, and the gate end of M5 serves as a reset end RST.

[0035] In each of the pixel matrix units, the source end of M1 in the upper left pixel unit 201 shares the source end of M1 in the lower left pixel unit 203; the gate end of M1 in the upper left pixel unit 201 shares the gate end of M1 in the upper right pixel unit 202; the source end of M1 in the upper right pixel unit 202 shares the source end of M1 in the lower right pixel unit 204; and the gate end of M1 in the lower left pixel unit 203 shares the gate end of M1 in the lower right pixel unit 204.

[0036] The present application provides a partial layout structure of a silicon-based liquid crystal display driving circuit, which comprises a plurality of minimum pixel matrix units, each of which is composed of four identical pixel units arranged in 2*2 and axially symmetrical in vertical and horizontal axes, and the four pixel units share a power supply in the layout inside the minimum pixel matrix unit, which greatly reduces the area of the pixel, and the adjacent pixel matrix units also share a signal port and realize high resolution through multiplexing of the basic units.

[0037] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0038] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality.

[0039] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and the specific implementation of the present application should not be limited to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the scope of protection of the present application.

Claims

1. A layout structure of a liquid crystal on silicon display driving circuit, characterized in that: include: A plurality of minimum pixel matrix units, each minimum pixel matrix unit is composed of four identical pixel units, the four pixel units are arranged in a 2*2 pattern and are axisymmetric about the vertical axis and the horizontal axis, and are respectively an upper left pixel unit (201), an upper right pixel unit (202), a lower left pixel unit (203), and a lower right pixel unit (204); The upper left pixel unit (201) and the upper right pixel unit (202) share a ground terminal (GND) and a first address terminal (GATE1); the lower left pixel unit (203) and the lower right pixel unit (204) share a ground terminal (GND) and a second address terminal (GATE2); and the four pixel units share a power supply terminal (VDD); The upper left pixel unit (201) and the lower left pixel unit (203) share a first data terminal (DATA1); the upper right pixel unit (202) and the lower right pixel unit (204) share a second data terminal (DATA2); each pixel unit is composed of MOS switches M0, M1, M2, M3, M4 and M5; Among them, the source end of M0 is connected to the substrate end and connected to the power supply end (VDD), the gate end of M0 is connected to the gate end of M3, the drain end of M5, the drain end of M4, and the drain end of M2, and serves as the output end (OUT); the drain end of M0 is connected to the gate end of M4, the gate end of M2, and the drain end of M1 respectively; the source end of M4 is connected to the substrate end and connected to the power supply end (VDD); the substrate end of M3 is connected to its source end and connected to the ground end (GND); the substrate end of M5 is connected to its source end and connected to the ground end (GND); the substrate end of M4 is connected to its source end and connected to the ground end (GND); the substrate end of M2 is connected to its source end and connected to the ground end (GND); the source end of M1 As a data terminal (DATA), the gate terminal serves as an address terminal (GATA), and the gate terminal of the M5 serves as a reset terminal (RST); in each pixel matrix unit, the source terminal of the M1 in the upper left pixel unit (201) is shared with the source terminal of the M1 in the lower left pixel unit (203); the gate terminal of the M1 in the upper left pixel unit (201) is shared with the gate terminal of the M1 in the upper right pixel unit (202); the source terminal of the M1 in the upper right pixel unit (202) is shared with the source terminal of the M1 in the lower right pixel unit (204); and the gate terminal of the M1 in the lower left pixel unit (203) is shared with the gate terminal of the M1 in the lower right pixel unit (204).

2. The layout structure of a silicon-based liquid crystal display driving circuit according to claim 1, wherein, The maximum resolution of the LCOS of the silicon-based liquid crystal display driving circuit is 4096*256.

3. The layout structure of a silicon-based liquid crystal display driving circuit according to claim 2, wherein, The minimum pixel matrix unit is one; Wherein, n is the number of columns of the minimum pixel matrix unit, m is the number of rows of the minimum pixel matrix unit, the maximum value of n is 256, and the maximum value of m is 4096.

4. The layout structure of a silicon-based liquid crystal display driving circuit according to claim 2, wherein, The size of each pixel unit is 3µm*4.2µm.

5. The layout structure of a silicon-based liquid crystal display driving circuit according to claim 2, wherein, The minimum pixel matrix units in adjacent rows share a common ground terminal (GND), the minimum pixel matrix units in the same row share a common address terminal (GATE), and the minimum pixel matrix units in the same column share a common data terminal (DATA) and a power supply terminal (VDD).

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