Display panel

Abstract

The application provides a display panel, which comprises a plurality of first lead groups and a plurality of second lead groups arranged on a substrate, the first lead groups and the second lead groups are located at different layers, each of the first lead groups and the second lead groups comprises at least two gate leads, each of the gate leads is electrically connected with a corresponding gate scanning line, and each of the first lead groups has a voltage difference between every two adjacent gate leads, and each of the second lead groups also has a voltage difference between every two adjacent gate leads, so that adjacent gate leads at the same layer transmit different signals, when a short circuit occurs between adjacent gate leads at the same layer, the voltage on the gate leads after the short circuit will obviously change due to the short circuit between different signals, and then the short circuit can be detected through a lighting test, thereby effectively reducing the missed detection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] In the manufacturing process of the display panel, in order to timely detect the defective product, the display panel will be subjected to the cell test. For this purpose, a detection circuit capable of detecting the short circuit of the signal line and other malfunctions will be designed on the array substrate. For example, a gate detection circuit for detecting the gate scanning line, and in order to improve the detection efficiency, two kinds of detection signals will be used. At the same time, in order to reduce the frame of the display panel, the metal traces for transmitting the two kinds of detection signals will be arranged on two metal layers, and the metal traces on each metal layer transmit one kind of detection signal. However, when the short circuit occurs between the adjacent metal traces on the same metal layer, the short circuit between the same signals cannot be detected by the cell test, which will result in the missed detection. SUMMARY

[0003] The present application provides a display panel to alleviate the technical problem of the missed detection in the cell test process of the existing display panel.

[0004] To solve the above problems, the technical scheme provided by the present application is as follows:

[0005] The display panel provided by the present application comprises a display area and a first non-display area located on one side of the display area, and further comprises:

[0006] a substrate substrate;

[0007] a plurality of gate scanning lines arranged on the substrate substrate and located in the display area, each of the gate scanning lines extending along a first direction, and the plurality of gate scanning lines being arranged at intervals along a second direction;

[0008] a plurality of first lead groups arranged on the substrate substrate and located in the first non-display area, each of the first lead groups comprising at least two gate leads extending along the first direction, each of the gate leads being electrically connected to a corresponding one of the gate scanning lines, and each of the adjacent two gate leads having a voltage difference therebetween; and

[0009] a plurality of second lead groups arranged on the substrate substrate and located in the first non-display area, each of the second lead groups comprising at least two gate leads extending along the first direction, each of the gate leads being electrically connected to a corresponding one of the gate scanning lines, and each of the adjacent two gate leads having a voltage difference therebetween;

[0010] The first lead group and the second lead group are located at different layers, and the orthogonal projection of the gate lead in the second lead group on the substrate substrate and the orthogonal projection of the gate lead in the first lead group on the substrate substrate are arranged alternately.

[0011] In the display panel provided in the embodiments of the present application, each first lead group further comprises a plurality of connection traces, and in the same first lead group, each connection trace is electrically connected with a corresponding gate trace, and each adjacent two connection traces have a voltage difference therebetween.

[0012] Each second lead group further comprises a plurality of connection traces, and in the same second lead group, each connection trace is electrically connected with a corresponding gate trace, and each adjacent two connection traces have a voltage difference therebetween.

[0013] The orthogonal projection of the connection trace in the first lead group on the substrate substrate and the orthogonal projection of the connection trace in the second lead group on the substrate substrate at least partially overlap.

[0014] In the display panel provided in the embodiments of the present application, the number of gate leads in the first lead group is equal to the number of gate leads in the second lead group, and the voltage on the gate lead in the first lead group is the same as the voltage on the corresponding gate lead in the second lead group.

[0015] In the display panel provided in the embodiments of the present application, the first lead group comprises adjacent first and second gate leads, the second lead group comprises adjacent third and fourth gate leads, the voltage on the first gate lead is the same as the voltage on the third gate lead, and the voltage on the second gate lead is the same as the voltage on the fourth gate lead.

[0016] In the display panel provided in the embodiments of the present application, the display panel further comprises a plurality of third lead groups and a plurality of fourth lead groups arranged in the same layer as the first lead group, one third lead group and one fourth lead group are arranged between each adjacent two first lead groups, the third lead group and the fourth lead group each comprise at least two gate leads, and each adjacent two gate leads in the third lead group have a voltage difference therebetween, and each adjacent two gate leads in the fourth lead group have a voltage difference therebetween.

[0017] The voltage on at least one gate lead in the third lead group is different from the voltage on the gate lead in the first lead group, and in adjacent first and third lead groups, the gate lead in the third lead group close to the first lead group and the gate lead in the first lead group close to the third lead group have a voltage difference therebetween.

[0018] The voltage on at least one gate lead line in the fourth lead line group is different from the voltage on the gate lead line in the first lead line group, and in the adjacent first lead line group and fourth lead line group, there is a voltage difference between the gate lead line close to the first lead line group in the fourth lead line group and the gate lead line close to the fourth lead line group in the first lead line group; and in the adjacent third lead line group and fourth lead line group, there is a voltage difference between the gate lead line close to the fourth lead line group in the third lead line group and the gate lead line close to the third lead line group in the fourth lead line group.

[0019] In the display panel provided by the embodiment of the present application, the first lead line group comprises adjacent first and second gate lead lines; the third lead line group comprises the first gate lead line and a fifth gate lead line, the fifth gate lead line has a voltage difference with the second gate lead line, and in the adjacent first lead line group and third lead line group, the fifth gate lead line is close to the first lead line group.

[0020] The fourth lead line group comprises the second gate lead line and a sixth gate lead line, the sixth gate lead line has a voltage difference with the first gate lead line, and in the adjacent first lead line group and fourth lead line group, the sixth gate lead line is close to the first lead line group.

[0021] In the display panel provided by the embodiment of the present application, the voltage on the fifth gate lead line is the same as the voltage on the sixth gate lead line.

[0022] In the display panel provided by the embodiment of the present application, the display panel further comprises a second non-display area located on the other side of the display area, the second non-display area and the first non-display area are oppositely arranged, and the first lead line group and the second lead line group are arranged in the second non-display area, wherein the first lead line group and the second lead line group of the first non-display area are electrically connected with the gate scanning lines of the odd-numbered rows, and the first lead line group and the second lead line group of the second non-display area are electrically connected with the gate scanning lines of the even-numbered rows.

[0023] In the display panel provided by the embodiment of the present application, the display panel further comprises a second non-display area located on the other side of the display area, the second non-display area and the first non-display area are oppositely arranged, and the first lead line group and the second lead line group are arranged in the second non-display area, wherein the first lead line group of the first non-display area is symmetrically arranged with the first lead line group of the second non-display area, and the second lead line group of the first non-display area is symmetrically arranged with the second lead line group of the second non-display area.

[0024] In the display panel provided by the embodiment of the present application, the first lead group or the second lead group is arranged in the same layer as the gate scanning line.

[0025] The display panel provided by the present application has the following beneficial effects: the display panel includes a plurality of first lead groups and a plurality of second lead groups arranged on a substrate, the first lead groups and the second lead groups are located in different layers, each of the first lead groups and the second lead groups includes at least two gate leads, each gate lead is electrically connected to a corresponding gate scanning line, and each adjacent two gate leads in the first lead group have a voltage difference, and each adjacent two gate leads in the second lead group also have a voltage difference, so that adjacent gate leads in the same layer transmit different signals, when short circuit occurs between adjacent gate leads in the same layer, the voltage on the gate lead after the short circuit will change obviously due to the short circuit between different signals, and thus the short circuit can be detected through the lighting test, thereby effectively reducing the missed detection. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0027] Figure 1 A top view structural schematic diagram of the display panel provided by the embodiment of the present application.

[0028] Figure 2 For Figure 1 A detailed structure schematic diagram of the first non-display area in the embodiment.

[0029] Figure 3 For Figure 2 A sectional structure schematic diagram along the direction of M-M' in the embodiment.

[0030] Figure 4 For Figure 2 A sectional structure schematic diagram along the direction of N-N' in the embodiment.

[0031] Figure 5 Another top view structural schematic diagram of the display panel provided by the embodiment of the present application.

[0032] Figure 6 For Figure 5 A detailed structure schematic diagram of the first non-display area in the embodiment.

[0033] Figure 7 Another top view structural schematic diagram of the display panel provided by the embodiment of the present application. DETAILED DESCRIPTION

[0034] The following description of the embodiments refers to the accompanying drawings, which are used to exemplify specific embodiments of the present application that can be practiced. Directional terms as used in this application, such as [up], [down], [front], [back], [left], [right], [inward], [outward], [side], and the like, are only used with reference to the accompanying drawings. The directional terms are used to illustrate and understand the present application, and are not used to limit the present application. In the drawings, similar elements are denoted by the same reference numerals. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0035] Please refer to Figures 1 to 4 , Figure 1 a top view structural schematic diagram of a display panel provided in the embodiments of the present application, Figure 2 is Figure 1 a detailed structural schematic diagram of a first non-display area in the display panel, Figure 3 is Figure 2 a sectional structural schematic diagram along the direction of M-M' in the display panel, Figure 4 is Figure 2 a sectional structural schematic diagram along the direction of N-N' in the display panel. The display panel 100 includes a display area AA and a non-display area surrounding the display area AA, the non-display area including a first non-display area NA1, a second non-display area NA2, and a third non-display area NA3, the first non-display area NA1 being located at one side of the display area AA, the second non-display area NA2 being located at the other side of the display area AA, that is, the second non-display area NA2 being located at the side of the display area AA away from the first non-display area NA1, so that the first non-display area NA1 and the second non-display area NA2 are oppositely arranged. The third non-display area NA3 is located between the first non-display area NA1 and the second non-display area NA2. Optionally, the display panel 100 includes a liquid crystal display panel, an OLED display panel, etc.

[0036] The display panel 100 further includes a substrate 10 and a plurality of gate scanning lines GL, a plurality of data lines DL, a plurality of first lead groups R1, and a plurality of second lead groups R2 disposed on the substrate 10. Optionally, the substrate 10 is a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it can include a hard substrate such as a glass substrate; when the substrate 10 is a flexible substrate, it can include a flexible substrate such as a polyimide (PI) film, an ultra-thin glass film, etc.

[0037] Please refer to Figure 1A plurality of gate scan lines GL are disposed on the substrate 10 and located in the display area AA. Each of the gate scan lines GL extends along a first direction X, and the gate scan lines GL are arranged along a second direction Y. A plurality of data lines DL are disposed on the substrate 10 and located in the display area AA. Each of the data lines DL extends along the second direction Y, and the data lines DL are arranged along the first direction X. The gate scan lines GL and the data lines DL cross to define a plurality of pixels. The gate scan lines GL are configured to provide gate driving signals to the pixels, and the data lines DL are configured to provide data signals to the pixels. The first direction X is a horizontal direction, and the second direction Y is a vertical direction, but the present application is not limited thereto.

[0038] A plurality of first lead groups R1 are disposed on the substrate 10 and located in the first non-display area NA1. Each of the first lead groups R1 includes at least two gate leads extending along the first direction X. Each of the gate leads is electrically connected to a corresponding one of the gate scan lines GL, and each adjacent two of the gate leads have a voltage difference therebetween.

[0039] A plurality of second lead groups R2 are disposed on the substrate 10 and located in the first non-display area NA1. Each of the second lead groups R2 includes at least two gate leads extending along the first direction X. Each of the gate leads is electrically connected to a corresponding one of the gate scan lines GL, and each adjacent two of the gate leads have a voltage difference therebetween. In this way, adjacent gate leads in the same layer transmit different signals. When short circuit occurs between adjacent gate leads in the same layer, the voltage on the gate leads after the short circuit will change significantly due to the short circuit between different signals, and thus the short circuit can be detected through a light-on test, effectively reducing the missed detection.

[0040] The first lead groups R1 and the second lead groups R2 are located in different layers, and the projection of the gate leads in the second lead groups R2 on the substrate 10 is arranged alternately with the projection of the gate leads in the first lead groups R1 on the substrate 10.

[0041] Optionally, the first lead groups R1 are formed by a first metal layer, the second lead groups R2 are formed by a second metal layer, and the first metal layer is located on a side of the second metal layer away from the substrate 10. The first lead groups R1 or the second lead groups R2 are disposed in the same layer as the gate scan lines GL. The number of the gate leads in the first lead groups R1 is equal to the number of the gate leads in the second lead groups R2, and the voltage on the gate leads in the first lead groups R1 is the same as the voltage on the corresponding gate leads in the second lead groups R2.

[0042] Optionally, in combination with the aboveFigure 1 and Figure 2 The first wire group R1 includes a first gate wire G1 and a second gate wire G2 adjacent to each other, both of which extend along the first direction X, and are spaced apart and insulated from each other. There is a voltage difference between the first gate wire G1 and the second gate wire G2, for example, the voltage on the first gate wire G1 is 9V, and the voltage on the second gate wire G2 is -7V.

[0043] The second wire group R2 includes a third gate wire G3 and a fourth gate wire G4 adjacent to each other, both of which extend along the first direction X, and are spaced apart and insulated from each other. The voltage on the third gate wire G3 is the same as the voltage on the first gate wire G1, and the voltage on the fourth gate wire G4 is the same as the voltage on the second gate wire G2. Here, the same voltage means that the amplitudes of the voltages are the same, for example, the voltage on the third gate wire G3 is also 9V, and the voltage on the fourth gate wire G4 is also -7V.

[0044] At the same time, since the first wire group R1 and the second wire group R2 are located in different metal layers, the first gate wire G1 and the third gate wire G3 are located in different metal layers, and the second gate wire G2 and the fourth gate wire G4 are located in different metal layers, as shown in Figure 3 An interlayer insulating layer 20 is provided between the first gate wire G1 and the third gate wire G3 to insulate the gate wires in the first wire group R1 from the gate wires in the second wire group R2.

[0045] Further, with reference to Figure 1 and Figure 2each of the first lead groups R1 further comprises a plurality of connection traces, each of the connection traces is electrically connected with a corresponding gate trace in the same first lead group R1, and each adjacent two of the connection traces have a voltage difference. The connection traces in the first lead group R1 and the gate traces in the first lead group R1 are formed by the same metal layer. Optionally, the first lead group R1 further comprises a first connection trace C1 and a second connection trace C2 adjacent to each other, the first connection trace C1 is electrically connected with the first gate lead G1, and part of the first connection trace C1 extends along the second direction Y. The second connection trace C2 is electrically connected with the second gate lead G2, and part of the second connection trace C2 extends along the second direction Y. In the first direction X, the first connection trace C1 and the second connection trace C2 are arranged at intervals, and the first connection trace C1 and the second connection trace C2 are insulated from each other.

[0046] each of the second lead groups R2 further comprises a plurality of connection traces, each of the connection traces is electrically connected with a corresponding gate trace in the same second lead group R2, and each adjacent two of the connection traces have a voltage difference. In this way, adjacent connection traces in the same layer transmit different signals. When a short circuit occurs between adjacent connection traces in the same layer, the voltage on the connection traces after the short circuit will change significantly due to the short circuit between different signals, and thus the short circuit can be detected through the light-on test, further effectively reducing the probability of missed detection. Of course, to further reduce the probability of missed detection, in the first direction X, there is a voltage difference between any adjacent two connection traces on the same metal layer.

[0047] The connection traces in the second lead group R2 and the gate traces in the first lead group R1 are formed by the same metal layer, so that the connection traces in the second lead group R2 and the connection traces in the first lead group R1 are located on different metal layers, thereby reducing the width of the first non-display area NA1 in the first direction X, and further reducing the frame of the display panel 100.

[0048] Optionally, the second lead group R2 further comprises a third connection trace C3 and a fourth connection trace C4 adjacent to each other, the third connection trace C3 is electrically connected with the third gate lead G3, and part of the third connection trace C3 extends along the second direction Y. The fourth connection trace C4 is electrically connected with the fourth gate lead G4, and part of the fourth connection trace C4 extends along the second direction Y. In the first direction X, the third connection trace C3 and the fourth connection trace C4 are arranged at intervals, and the third connection trace C3 and the fourth connection trace C4 are insulated from each other.

[0049] Optionally, to further reduce the width of the first non-display area NA1 in the first direction X, the orthographic projection of the connection traces in the first lead group R1 onto the substrate 10 at least partially overlaps with the orthographic projection of the connection traces in the second lead group R2 onto the substrate 10. For example... Figure 2 As shown, some connecting traces in the first lead group R1 cover some connecting traces in the second lead group R2. For example, some of the first connecting trace C1 covers some of the fourth connecting trace C4, and some of the second connecting trace C2 covers some of the third connecting trace C3. The "covering" refers to the positional relationship between the orthographic projections of the connecting traces in the first lead group R1 and the second lead group R2 on the substrate 10. For example, if some of the first connecting trace C1 covers some of the fourth connecting trace C4, it means that the orthographic projections of the first connecting trace C1 and the fourth connecting trace C4 on the substrate 10 overlap in the first direction X. However, the first connecting trace C1 and the fourth connecting trace C4 are also separated by the interlayer insulating layer 20, making them insulated from each other. Figure 4 As shown.

[0050] It should be noted that, Figure 2 To clearly show the connection traces in the second lead group R2, which are obscured by the connection traces in the first lead group R1. Figure 2 The connection traces within the first lead group R1 above the connection traces within the second lead group R2 have been removed. For example... Figure 2 The second connection trace C2 covers the third connection trace C3, so that the third connection trace C3 is obscured by the second connection trace C2. In order to clearly show the third connection trace C3, the portion of the second connection trace C2 above the third connection trace C3 is removed.

[0051] Furthermore, the second non-display area NA2 is also provided with multiple first lead groups R1 and multiple second lead groups R2. The first lead groups R1 of the second non-display area NA2 have the same structure as the first lead groups R1 of the first non-display area NA1, and the second lead groups R2 of the second non-display area NA2 have the same structure as the second lead groups R2 of the first non-display area NA1. The difference is that the first lead groups R1 and R2 of the first non-display area NA1 are electrically connected to the gate scan lines GL in odd-numbered rows, while the first lead groups R1 and R2 of the second non-display area NA2 are electrically connected to the gate scan lines GL in even-numbered rows.

[0052] Further, the third non-display area NA3 is provided with a terminal area, which includes a first gate terminal area GP1 and a second gate terminal area GP2, and a source terminal area SP between the first gate terminal area GP1 and the second gate terminal area GP2. The first gate terminal area GP1 and the second gate terminal area GP2 are both provided with gate terminals GP. The gate terminals GP in the first gate terminal area GP1 are electrically connected with the first lead group R1 and the second lead group R2 in the first non-display area NA1, for providing gate driving signals to the first lead group R1 and the second lead group R2 in the first non-display area NA1. The gate terminals GP in the second gate terminal area GP2 are electrically connected with the first lead group R1 and the second lead group R2 in the second non-display area NA2, for providing gate driving signals to the first lead group R1 and the second lead group R2 in the second non-display area NA2. The source terminal area SP is provided with a source terminal SP, which is electrically connected with the data lines DL in the display, for providing data signals to the data lines DL.

[0053] Of course, in order to electrically connect the gate terminals GP in the third non-display area NA3 with the first lead group R1 and the second lead group R2, the third non-display area NA3 is further provided with fan-out wires, which are electrically connected with the corresponding connection wires in each lead group (including the first lead group R1, the second lead group R2, etc.).

[0054] In order to provide different voltage signals to the connection wires and the gate leads in each lead group, the third non-display area NA3 is further provided with a first signal access point GS1 and a second signal access point GS2, which provide different voltages, for example, the first signal access point GS1 provides a voltage of 9V, and the second signal access point GS2 provides a voltage of -7V. The first gate lead G1, the third gate lead G3, the first connection wire C1 and the third connection wire C3 are connected with the voltage of the first signal access point, and the second gate lead G2, the fourth gate lead G4, the second connection wire C2 and the fourth connection wire C4 are connected with the voltage of the second signal access point.

[0055] In an embodiment, referring to Figures 1 to 6 , Figure 5 Another top view structural schematic diagram of a display panel provided by the embodiment of the present application, Figure 6 is provided Figure 5FIG. 4 is a schematic diagram of a detailed structure of a first non-display region according to another embodiment of the present application. Unlike the above embodiment, the display panel 101 further includes a plurality of third lead groups R3 and a plurality of fourth lead groups R4 disposed in the same layer as the first lead groups R1. One third lead group R3 and one fourth lead group R4 are disposed between each pair of adjacent first lead groups R1. Each of the third lead groups R3 and the fourth lead groups R4 includes at least two gate leads. Each pair of adjacent gate leads in the third lead groups R3 has a voltage difference therebetween. Each pair of adjacent gate leads in the fourth lead groups R4 has a voltage difference therebetween.

[0056] The voltage of at least one gate lead in the third lead groups R3 is different from the voltage of a gate lead in the first lead groups R1. In adjacent first lead groups R1 and third lead groups R3, a gate lead in the third lead group R3 close to the first lead group R1 has a voltage difference from a gate lead in the first lead group R1 close to the third lead group R3.

[0057] The voltage of at least one gate lead in the fourth lead groups R4 is different from the voltage of a gate lead in the first lead groups R1. In adjacent first lead groups R1 and fourth lead groups R4, a gate lead in the fourth lead group R4 close to the first lead group R1 has a voltage difference from a gate lead in the first lead group R1 close to the fourth lead group R4. In adjacent third lead groups R3 and fourth lead groups R4, a gate lead in the third lead group R3 close to the fourth lead group R4 has a voltage difference from a gate lead in the fourth lead group R4 close to the third lead group R3.

[0058] The third lead groups R3 include a fifth gate lead G5 adjacent to the first gate lead G1. The fifth gate lead G5 has a voltage difference from the second gate lead G2. In adjacent first lead groups R1 and third lead groups R3, the fifth gate lead G5 is close to the first lead group R1. The fourth lead groups R4 include a sixth gate lead G6 adjacent to the second gate lead G2. The sixth gate lead G6 has a voltage difference from the first gate lead G1. In adjacent first lead groups R1 and fourth lead groups R4, the sixth gate lead G6 is close to the first lead group R1.

[0059] Correspondingly, the display panel 100 further comprises a plurality of fifth lead groups R5 and a plurality of sixth lead groups R6 which are arranged in the same layer as the second lead groups R2, one fifth lead group R5 and one sixth lead group R6 are arranged between every two adjacent second lead groups R2, each of the fifth lead group R5 and the sixth lead group R6 comprises at least two gate leads, and there is a voltage difference between every two adjacent gate leads in the fifth lead group R5 and the sixth lead group R6.

[0060] The voltage on at least one gate lead in the fifth lead group R5 is different from the voltage on the gate lead in the second lead group R2, and in the adjacent second lead group R2 and fifth lead group R5, the gate lead in the fifth lead group R5 close to the second lead group R2 has a voltage difference with the gate lead in the second lead group R2 close to the fifth lead group R5.

[0061] The voltage on at least one gate lead in the sixth lead group R6 is different from the voltage on the gate lead in the second lead group R2, and in the adjacent second lead group R2 and sixth lead group R6, the gate lead in the sixth lead group R6 close to the second lead group R2 has a voltage difference with the gate lead in the second lead group R2 close to the sixth lead group R6; and in the adjacent fifth lead group R5 and sixth lead group R6, the gate lead in the fifth lead group R5 close to the sixth lead group R6 has a voltage difference with the gate lead in the sixth lead group R6 close to the fifth lead group R5.

[0062] The fifth lead group R5 comprises the seventh gate lead G7 and the first gate lead G1 which are adjacent, the sixth gate lead G6 has a voltage difference with the second gate lead G2, and in the adjacent second lead group R2 and fifth lead group R5, the sixth gate lead G6 is close to the second lead group R2. The sixth lead group R6 comprises the eighth gate lead G8 and the second gate lead G2 which are adjacent, the eighth gate lead G8 has a voltage difference with the first gate lead G1, and in the adjacent second lead group R2 and sixth lead group R6, the eighth gate lead G8 is close to the second lead group R2.

[0063] Optionally, the voltage on the fifth gate lead G5 is the same as the voltage on the sixth gate lead G6, the voltage on the seventh gate lead G7 is the same as the voltage on the eighth gate lead G8, and the voltage on the fifth gate lead G5 is the same as the voltage on the seventh gate lead G7. In this way, only a third signal access point GS3 needs to be added in the third non-display area NA3, avoiding adding too many signal access points, thereby reducing the difficulty of the light-on test.

[0064] It can be understood that, with reference to Figure 6 , the third lead group R3, the fourth lead group R4, the fifth lead group R5, and the sixth lead group R6 each further include a connection trace electrically connected with the gate lead. Optionally, the third lead group R3 includes the first connection trace C1 and the fifth connection trace C5 adjacent to each other, the fourth lead group R4 includes the second connection trace C2 and the sixth connection trace C6 adjacent to each other, the fifth lead group R5 includes the third connection trace C3 and the seventh connection trace C7 adjacent to each other, and the sixth lead group R6 includes the fourth connection trace C4 and the eighth connection trace C8 adjacent to each other. In the first direction X, any two connection traces adjacent to each other on the same metal layer have a voltage difference. For other descriptions, please refer to the above embodiments, which will not be repeated here.

[0065] In an embodiment, please refer to Figures 1 to 7 , Figure 7 is another top view structural schematic diagram of a display panel provided by the embodiment of the present application. Different from the above embodiments, the display panel 102 further includes a second non-display area NA2 located on the other side of the display area AA, the second non-display area NA2 and the first non-display area NA1 are oppositely arranged, and the first lead group R1 and the second lead group R2 are arranged in the second non-display area NA2. The first lead group R1 of the first non-display area NA1 is symmetrically arranged with the first lead group R1 of the second non-display area NA2, and the second lead group R2 of the first non-display area NA1 is symmetrically arranged with the second lead group R2 of the second non-display area NA2. For other descriptions, please refer to the above embodiments, which will not be repeated here.

[0066] According to the above embodiments, it can be known that:

[0067] The application provides a display panel, which comprises a plurality of first lead groups and a plurality of second lead groups arranged on a substrate, the first lead groups and the second lead groups are located at different layers, each of the first lead groups and the second lead groups comprises at least two gate leads, each of the gate leads is electrically connected with a corresponding gate scanning line, and each of the first lead groups has a voltage difference between every two adjacent gate leads, and each of the second lead groups also has a voltage difference between every two adjacent gate leads, so that adjacent gate leads at the same layer transmit different signals, when short circuit occurs between adjacent gate leads at the same layer, the voltage on the gate leads after the short circuit changes obviously due to the short circuit between different signals, and then the short circuit can be detected through a lighting test, and the missed detection is effectively reduced.

[0068] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0069] The embodiments of the application are described in detail above, and the principle and implementation mode of the application are described by applying specific examples; the above embodiment description is only used to help understand the technical solution and core idea of the application; those skilled in the art should understand that the technical solution recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and the modification or replacement does not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the application.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a first non-display area located at one side of the display area, and further comprises: a substrate substrate; a plurality of gate scanning lines arranged on the substrate substrate and located in the display area, each of the gate scanning lines extending along a first direction, and the plurality of gate scanning lines being arranged at intervals along a second direction; a plurality of first lead groups arranged on the substrate substrate and located in the first non-display area, each of the first lead groups comprising at least two gate leads extending along the first direction, each of the gate leads being electrically connected to a corresponding one of the gate scanning lines, and each of two adjacent gate leads having a voltage difference therebetween; and a plurality of second lead groups arranged on the substrate substrate and located in the first non-display area, each of the second lead groups comprising at least two gate leads extending along the first direction, each of the gate leads being electrically connected to a corresponding one of the gate scanning lines, and each of two adjacent gate leads having a voltage difference therebetween; wherein the first lead groups and the second lead groups are located at different layers, and the orthographic projection of at least two gate leads in the second lead groups on the substrate substrate is located at one side of the orthographic projection of at least two gate leads in the first lead groups on the substrate substrate; wherein each of the first lead groups further comprises a plurality of connection traces extending along the second direction, each of the connection traces being electrically connected to a corresponding one of the gate traces; each of the second lead groups further comprises a plurality of connection traces extending along the second direction, each of the connection traces being electrically connected to a corresponding one of the gate traces; the orthographic projection of the connection traces in the first lead groups on the substrate substrate at least partially overlaps the orthographic projection of the connection traces in the second lead groups on the substrate substrate.

2. The display panel of claim 1, wherein, each of two adjacent connection traces has a voltage difference therebetween.

3. The display panel of claim 2, wherein, the number of gate leads in the first lead groups is equal to the number of gate leads in the second lead groups, and the voltage on the gate leads in the first lead groups is the same as the voltage on the corresponding gate leads in the second lead groups.

4. The display panel of claim 3, wherein, the first lead groups comprise adjacent first and second gate leads, the second lead groups comprise adjacent third and fourth gate leads, the voltage on the first gate lead is the same as the voltage on the third gate lead, and the voltage on the second gate lead is the same as the voltage on the fourth gate lead.

5. The display panel of claim 2, wherein, the display panel further comprises a plurality of third lead groups and a plurality of fourth lead groups arranged at the same layer as the first lead groups, one third lead group and one fourth lead group being arranged between each of two adjacent first lead groups, each of the third and fourth lead groups comprising at least two gate leads, each of two adjacent gate leads in the third lead group having a voltage difference therebetween, and each of two adjacent gate leads in the fourth lead group having a voltage difference therebetween. The voltage on at least one gate lead line in the third lead line group is different from the voltage on the gate lead line in the first lead line group, and in the adjacent first lead line group and third lead line group, there is a voltage difference between the gate lead line close to the first lead line group in the third lead line group and the gate lead line close to the third lead line group in the first lead line group. The voltage on at least one gate lead line in the fourth lead line group is different from the voltage on the gate lead line in the first lead line group, and in the adjacent first lead line group and fourth lead line group, there is a voltage difference between the gate lead line close to the first lead line group in the fourth lead line group and the gate lead line close to the fourth lead line group in the first lead line group, and in the adjacent third lead line group and fourth lead line group, there is a voltage difference between the gate lead line close to the fourth lead line group in the third lead line group and the gate lead line close to the third lead line group in the fourth lead line group.

6. The display panel of claim 5, wherein, The first lead line group comprises adjacent first gate lead line and second gate lead line; the third lead line group comprises adjacent fifth gate lead line and the first gate lead line, and the fifth gate lead line has a voltage difference with the second gate lead line, and in the adjacent first lead line group and third lead line group, the fifth gate lead line is close to the first lead line group. The fourth lead line group comprises adjacent sixth gate lead line and the second gate lead line, and the sixth gate lead line has a voltage difference with the first gate lead line, and in the adjacent first lead line group and fourth lead line group, the sixth gate lead line is close to the first lead line group.

7. The display panel of claim 6, wherein, The voltage on the fifth gate lead line is the same as the voltage on the sixth gate lead line.

8. The display panel of any of claims 1-7, wherein, The display panel further comprises a second non-display area on the other side of the display area, the second non-display area and the first non-display area are oppositely arranged, and the first lead line group and the second lead line group are arranged in the second non-display area, wherein the first lead line group and the second lead line group of the first non-display area are electrically connected with the gate scanning lines of the odd rows, and the first lead line group and the second lead line group of the second non-display area are electrically connected with the gate scanning lines of the even rows.

9. The display panel of any one of claims 1-7, wherein, The display panel further comprises a second non-display area on the other side of the display area, the second non-display area and the first non-display area are oppositely arranged, and the first lead line group and the second lead line group are arranged in the second non-display area, wherein the first lead line group of the first non-display area is symmetrically arranged with the first lead line group of the second non-display area, and the second lead line group of the first non-display area is symmetrically arranged with the second lead line group of the second non-display area.

10. The display panel of any one of claims 1-7, wherein, The first lead line group or the second lead line group is arranged in the same layer as the gate scanning lines.

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