System for handling interrupts

Abstract

The present invention provides a system for processing interrupts, the system comprising: a processor, the processor being configured to service interrupts, the processor comprising an input port; and a first circuit, the first circuit being configured to convert an input first signal into a second signal and output the second signal; wherein the first circuit is connected in series between the first signal and the input port of the processor, the first signal being an edge-triggered interrupt signal, the second signal being a steady-state level signal within a first time period, and the second signal being the same as the first signal within a second time period following the first time period; wherein the processor interrogates the input port within the second time period to detect whether an interrupt exists in the received signal.

Description

Technical Field

[0001] The present invention relates to the field of electronic equipment, and in particular to a system for interrupt processing and detection. Background Art

[0002] In the prior art, electronic devices use a processor (such as a central processing unit (CPU), a microcontroller (MCU), or a digital signal controller (DSC)) to process and control signals. Input ports receive input data and perform corresponding detection and processing on the input signals to obtain relevant information. Output ports are used to output data and provide special signals. For example, general-purpose input / output (GPIO) ports can be used as both input and output ports. Some GPIO ports can also be configured to perform special functions to meet the needs of increasingly diverse applications. However, when detecting ADC or PWM signals, because the input signal continuously provides interrupt signals (or rising and falling edges of the waveform) to the GPIO port, the GPIO port must continuously perform detection, store a large amount of information in a register, and provide it to the controller for processing. This continuous detection and information processing places a significant burden on the controller, directly affecting its overall performance. Therefore, reducing the detection of rising and falling edges, especially signals with a large number of continuous rising and falling edges, is particularly important. Summary of the Invention

[0003] The object of the present invention is to provide a system for processing interrupt signals in advance, which can greatly reduce the interrupt detection burden of the processor for the corresponding port and improve the overall performance of the processor.

[0004] To achieve the above object, the present invention provides a system for processing interrupts, comprising:

[0005] a processor for interrupt servicing, the processor comprising an input port; and

[0006] a first circuit configured to convert an input first signal into a second signal and output the second signal; wherein the first circuit is connected in series between the first signal and the input port of the processor, the first signal is an edge-triggered interrupt signal, the second signal is a steady-state level signal within a first time period, and the second signal is the same as the first signal within a second time period following the first time period;

[0007] The first circuit includes: a first input terminal of a first NOR gate for connecting to the first signal, an output terminal of the first NOR gate connected to the first terminal of a first capacitor; a second terminal of the first capacitor connected to a power supply voltage via a first resistor, and a second terminal of the first capacitor connected to the input terminal of a second NOR gate; an output terminal of the second NOR gate connected to the second input terminal of the first NOR gate, and an output terminal of the second NOR gate outputting the second signal; or, the first circuit includes: a first input terminal of a first NAND gate for connecting to the first signal, an output terminal of the first NAND gate connected to the first terminal of a first capacitor; a second terminal of the first capacitor connected to ground via a first resistor, and a second terminal of the first capacitor connected to the input terminal of a second NOR gate; an output terminal of the second NOR gate connected to the second input terminal of the first NAND gate, and an output terminal of the second NOR gate outputting the second signal;

[0008] The processor queries the input port during the second time period to detect whether there is an interruption in the received signal.

[0009] Preferably, the first signal includes a rising edge triggered interrupt signal and / or a falling edge triggered interrupt signal.

[0010] Preferably, the first signal is a pulse width modulation (PWM) signal or an analog-to-digital conversion (ADC) signal.

[0011] Preferably, the input port of the processor is a general purpose input and output (GPIO) port.

[0012] Preferably, when the first circuit includes a first NOR gate, the first input terminal of the first NOR gate is further grounded through a third resistor.

[0013] Preferably, the second NOT gate is a NOR gate, and the second end of the first capacitor is connected to the two input ends of the NOR gate; or, the second NOT gate is a NAND gate, and the second end of the first capacitor is connected to the two input ends of the NAND gate.

[0014] Preferably, a second circuit is used to convert the second signal into a third signal; wherein, the second circuit is connected in series between the first circuit and the input port of the processor, and the second circuit includes along the signal transmission direction: a first diode, the N end of the first diode is also grounded through a second capacitor and a second resistor connected in parallel, and the N end of the first diode outputs the third signal.

[0015] Further preferably, the second circuit further includes a Schmitt trigger, the input end of the Schmitt trigger is used to connect to the second signal, and the output end of the Schmitt trigger is connected to the P end of the first diode.

[0016] Further preferably, the second capacitor and the second resistor are selected so that the time constant of the second capacitor and the second resistor is greater than 1 second.

[0017] Compared with the prior art, the system for processing interrupts provided by the present invention uses a circuit to pull the first input signal into a steady-state high-level or low-level signal within a specific time period. The processor only detects and processes the interrupt requirements of the input port through timed polling outside this time period. In this way, the processor does not need to detect the rising edge or falling edge of the input signal in real time, which greatly reduces the burden on the processor and improves the overall performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit diagram of a system for processing interrupts according to a first embodiment of the present invention;

[0019] Figure 2 is a circuit diagram of a system for processing interrupts according to a second embodiment of the present invention;

[0020] Figure 3A for Figure 1 Schematic diagram of the waveform of the signal at point A;

[0021] Figure 3B for Figure 1 Waveform diagram of the signal at point B;

[0022] Figure 3C for Figure 1 Schematic diagram of the waveform of the signal at point C. DETAILED DESCRIPTION

[0023] In order to provide a further understanding of the purpose, structure, features, and functions of the present invention, the present invention is described in detail below with reference to the embodiments.

[0024] Certain terms are used throughout the specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components by name, but rather by their functional differences. Throughout the specification and claims, the term "including" is open-ended and should be interpreted as meaning "including, but not limited to."

[0025] Reference Figure 1 FIG. 1 is a schematic diagram of a first embodiment of a system for processing interrupts according to the present invention. The system includes a processor and a circuit for processing interrupts.

[0026] The processor is used for interrupt service, and the processor includes an input port and receives an interrupt signal from the input port. The processor can be a central processing unit CPU, a microcontroller MCU, or a digital signal controller DSC. Figure 1The MCU is taken as an example, but the present invention is not limited thereto. The processor has an input port, such as Figure 1 Taking the GPIO port as an example, some GPIO ports can be used to receive and detect interrupt information. The processor queries the GPIO port to detect whether there is an interrupt in the received signal, and then executes the corresponding interrupt service program when there is an interrupt.

[0027] The circuit for processing interrupts is located between the first signal and the input port and is configured to process the input first signal. The first signal is an edge-triggered interrupt signal, which can be a rising-edge-triggered interrupt signal and / or a falling-edge-triggered interrupt signal. The signal obtained after processing ensures that the signal received by the GPIO port has no rising and / or falling edges within a specific time period. Preferably, the first signal is a pulse-width modulation signal (PWM) or an analog-to-digital conversion signal (ADC). In traditional interrupt processing, these two interrupt signals have too many rising and falling edges, which places a heavy burden on interrupt detection or acquisition.

[0028] In this embodiment, if Figure 1 As shown, the circuit for processing interrupts includes a first circuit (see Figure 1 The first circuit I is connected in series with the first signal ( Figure 1 The signal at point A in the middle, hereinafter referred to as SA) and the GPIO port of the MCU is used to convert the first signal into the second signal ( Figure 1 The first circuit 1 outputs the signal at point B in the circuit (hereinafter referred to as SB). Within a first time period τ, the first circuit 1 converts the first signal SA into a steady-state level signal SB1, which can be a steady-state high-level signal or a steady-state low-level signal. Within a second time period following the first time period τ, the first circuit 1 directly transmits the first signal SA to point B, generating a second signal SB2 identical to the first signal SA.

[0029] Figure 1 A specific implementation circuit of the first circuit I is also provided, which converts the first signal SA into a second signal SB1 of a stable high level in a first time period. Figure 3A Given Figure 1 The waveform of the first signal SA at point A, here taking the PWM signal as an example, Figure 3B Given Figure 1 The waveform of the second signal SB at point B in FIG. The following is explained based on the direction of signal transmission: the first input terminal of the first NOR gate U1 is used to connect the first signal ( Figure 1The first input terminal of the first NOT gate U1 is connected to point A), the output terminal of the first NOR gate U1 is connected to the first terminal of the first capacitor C1, the second terminal of the first capacitor C1 is connected to a first pull-up resistor R1 (or in other words, the second terminal of the first capacitor C1 is connected to the power supply voltage VCC via the first resistor R1), the second terminal of the first capacitor C1 is also connected to the input terminal of the second NOT gate U2, the output terminal of the second NOT gate U2 is connected to the second input terminal of the first NOR gate U1, and the output terminal of the second NOT gate U2 also outputs a second signal.

[0030] In one embodiment, the second NOT gate U2 may also be a NOR gate. In this case, the second end of the first capacitor C1 is connected to the two input ends of the NOR gate U2, and the output end of the NOR gate U2 is connected to the second input end of the first NOR gate U1. In another embodiment, the second NOT gate U2 may also be a NAND gate. In this case, the second end of the first capacitor C1 is connected to the two input ends of the NAND gate U2, and the output end of the NAND gate U2 is connected to the second input end of the first NOR gate U1.

[0031] In one embodiment, a third pull-down resistor R3 is further connected to point A (or point A is grounded via the third resistor R3). In one embodiment, a fourth pull-down resistor R4 is further connected to point B (or point B is grounded via the fourth resistor R4).

[0032] During the first time period τ, if the first NOR gate U1 initially outputs a low level (represented by 0), the first capacitor C1 begins charging due to the presence of the first pull-up resistor R1. The two sides of the first capacitor C1 can be considered equal in level. After the inversion operation by U2, a high level 1 is obtained at point B. At this time, the second input of the first NOR gate U1 inputs a high level 1, and after the NOR operation, the first NOR gate U1 outputs a low level 1. That is, during the charging process of the first capacitor C1, regardless of whether the first signal SA input to the first input of the first NOR gate U1 is a high level 1 or a low level 0, the second signal SB1 output at point B remains a high level 1.

[0033] After the first capacitor C1 is fully charged, no current flows through the first resistor R1. At this point, the voltage at the second terminal of the first capacitor C1 is equal to VCC, or a high level 1. After being inverted by U2, the second signal SB2 output at point B is a low level 0. At this point, the signal input to the second input terminal of the first NOR gate U1, which outputs the opposite signal to the first terminal of the first capacitor C1 after the NOR operation, is the opposite of the first signal SA. At this point, if the first signal SA is a high level 1, the signal at the first terminal of the first capacitor C1 is a low level 0. At this point, the first capacitor C1 is discharged to ground, the second terminal of the first capacitor C1 is a low level 0, and after being inverted by U2, a high level 1 is output at point B. If the first signal SA is a low level 0, the signal at the first terminal of the first capacitor C1 is a high level 1. The first capacitor C1 does not charge or discharge, the second terminal of the first capacitor C1 is a high level 1, and after being inverted by U2, a low level 0 is output at point B. In summary, in the second time period after the first time period τ, the first circuit I directly transmits the first signal SA to point B, and the second signal SB2 is equal to the first signal SA.

[0034] In summary, Figure 1 As an example, a first circuit I is used to pull a first signal SA to a steady-state high level during a first time period τ, so that the input port of the MCU does not receive edge-triggered interrupt signals during the first time period τ. In particular, for input signals with multiple consecutive rising and / or falling edges, there is no need to identify each rising and / or falling edge and perform complex interrupt detection procedures, thus saving MCU resources.

[0035] In another embodiment, Figure 2 As shown, the specific implementation circuit of the first circuit I' converts the first signal SA into a stable low-level second signal SB1' within the first time period τ'. The following is explained based on the direction of signal transmission: the first input terminal of the first NAND gate U1' is used to connect the first signal ( Figure 1The first input terminal of the first NAND gate U1' is connected to point A. The output terminal of the first NAND gate U1' is connected to the first terminal of the first capacitor C1', and the second terminal of the first capacitor C1' is connected to the first pull-down resistor R1' (or, in other words, the second terminal of the first capacitor C1' is grounded via the first resistor R1'). The second terminal of the first capacitor C1' is also connected to the input terminal of the second NOT gate U2', and the output terminal of the second NOT gate U2' is connected to the second input terminal of the first NAND gate U1'. The output terminal of the second NOT gate U2' also outputs the second signal SB'. In one embodiment, the second NOT gate U2' can also function as a NAND gate, in which case the second terminal of the first capacitor C1' is connected to the two input terminals of the NAND gate U2', and the output terminal of the NAND gate U2' is connected to the second input terminal of the first NAND gate U1'. In another embodiment, the second NOT gate U2' can also function as a NOR gate, in which case the second terminal of the first capacitor C1' is connected to the two input terminals of the NOR gate U2', and the output terminal of the NOR gate U2' is connected to the second input terminal of the first NAND gate U1'. In one embodiment, a third pull-down resistor R3 is further connected to point A (or, point A is grounded via the third resistor R3). In one embodiment, a fourth pull-down resistor R4 is further connected to point B (or, point B is grounded via the fourth resistor R4). τ' is determined by R1' and C1'.

[0036] exist Figure 2 In the embodiment, during a first time period τ', while the first capacitor C1 is charging, regardless of whether the first signal SA input to the first input terminal of the first NAND gate U1' is a high level 1 or a low level 0, the second signal SB1' output at point B is always a low level 0. During a second time period following the first time period τ', the first circuit I' directly transmits the first signal SA to point B, and the second signal SB2' is equivalent to the first signal SA.

[0037] Figure 1 and Figure 2 Two implementations of the first circuit I are shown respectively, but the present invention is not limited thereto.

[0038] In a preferred embodiment, the circuit for processing interrupts further includes a second circuit II for further processing the second signal SB output by the first circuit I, so that the obtained third signal SC ( Figure 1 and Figure 2 The signal at point C in the figure has a rising edge signal or a falling edge signal with a slope, which is more suitable for detection and processing by the GPIO port of the MCU. Figure 1 As shown in 3,

[0039] Figure 1 and Figure 2 The specific implementation circuit of the second circuit II is also given. Figure 1For example, the second circuit II is connected in series between the first circuit I and the input port of the MCU. Regarding signal transmission, the second circuit II includes: the P-terminal of the first diode D1 serves as the input terminal, and the N-terminal of the first diode D1 is connected to the pull-down second capacitor C2 and the pull-down second resistor R2. In other words, the N-terminal of the first diode D1 is grounded via the parallel connection of the second capacitor C2 and the second resistor R2. The N-terminal of the first diode D1 also outputs the third signal SC. Thus, when the second signal SB is high, the first diode D1 conducts, charging the second capacitor C2. When the second signal SB is low, the first diode D1 is not conducting, and the second capacitor C2 discharges to ground through the second resistor R2. The time constant of the second capacitor C2 and the second resistor R2 is designed to be greater than the period of the input pulse signal. In this way, in the high-level pulse area of ​​the pulse signal, the second capacitor C2 is always in a charging state; in the low-level pulse area of ​​the input pulse signal, the second capacitor C2 is always discharged to the ground through the second resistor R2, thereby converting the input pulse signal with a steeper rising edge and falling edge into a signal with a gentler rising edge and falling edge, which is more convenient to be detected and identified. Preferably, the time constant of the second capacitor C2 and the second resistor R2 is designed to be greater than 1 second. Through the processing of the second circuit II, the second time period Figure 3B The second signal SB is processed as follows Figure 3C The corresponding third signal SC.

[0040] In a preferred embodiment, a Schmitt trigger U3 is connected in series between the P-terminal of the first diode D1 and point B. The input of the Schmitt trigger U3 is connected to point B for inputting the second signal, and the output of the Schmitt trigger U3 is connected to the P-terminal of the first diode D1. The Schmitt trigger U3 buffers the input signal and, when the input second signal SB is at a low level of 0, allows the second capacitor C2 to release charge more quickly, maintaining the gradient and amplitude of the signal.

[0041] exist Figure 1 and Figure 2 In the illustrated embodiment, the processor MCU can also be configured to poll the input port only during a second time period to detect whether there is an interrupt in the received signal. In this way, the processor MCU handles the interrupt request of the input port through a periodic polling method, thereby greatly improving the efficiency of the MCU processor.

[0042] In summary, the system for processing interrupts provided by the present invention uses a circuit to pull the first input signal into a steady-state high-level or low-level signal within a specific time period. The processor only detects and processes the interrupt requirements of the input port through timed polling outside this time period. In this way, the processor does not need to detect the rising edge or falling edge of the input signal in real time, which greatly reduces the burden on the processor and improves the overall performance of the processor.

[0043] The present invention has been described with reference to the above embodiments. However, the above embodiments are merely exemplary embodiments of the present invention. It should be noted that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and improvements that do not depart from the spirit and scope of the present invention are intended to be protected by the present invention.

Claims

1. A system for handling interrupts, characterized in that The system includes: a processor for interrupt servicing, the processor comprising an input port; and a first circuit configured to convert an input first signal into a second signal and output the second signal; wherein the first circuit is connected in series between the first signal and the input port of the processor, the first signal is an edge-triggered interrupt signal, the second signal is a steady-state level signal within a first time period, and the second signal is the same as the first signal within a second time period following the first time period; The first circuit includes: a first input terminal of a first NOR gate for connecting to the first signal, an output terminal of the first NOR gate connected to the first terminal of a first capacitor; a second terminal of the first capacitor connected to a power supply voltage via a first resistor, and a second terminal of the first capacitor connected to the input terminal of a second NOR gate; an output terminal of the second NOR gate connected to the second input terminal of the first NOR gate, and an output terminal of the second NOR gate outputting the second signal; or, the first circuit includes: a first input terminal of a first NAND gate for connecting to the first signal, an output terminal of the first NAND gate connected to the first terminal of a first capacitor; a second terminal of the first capacitor connected to ground via a first resistor, and a second terminal of the first capacitor connected to the input terminal of a second NOR gate; an output terminal of the second NOR gate connected to the second input terminal of the first NAND gate, and an output terminal of the second NOR gate outputting the second signal; The processor queries the input port during the second time period to detect whether there is an interruption in the received signal.

2. The system for handling interrupts according to claim 1, wherein: The first signal includes a rising edge triggered interrupt signal and / or a falling edge triggered interrupt signal.

3. The system for handling interrupts according to claim 1, wherein: The first signal is a pulse width modulation (PWM) signal or an analog-to-digital conversion (ADC) signal.

4. The system for handling interrupts according to claim 1, wherein: The input port of the processor is a general-purpose input / output (GPIO) port.

5. The system for handling interrupts according to claim 1, wherein: When the first circuit includes a first NOR gate, the first input terminal of the first NOR gate is further grounded through a third resistor.

6. The system for handling interrupts according to claim 1, wherein: The second NOT gate is a NOR gate, and the second end of the first capacitor is connected to the two input ends of the NOR gate; or the second NOT gate is a NAND gate, and the second end of the first capacitor is connected to the two input ends of the NAND gate.

7. The system for handling interrupts according to claim 1, wherein: A second circuit is used to convert the second signal into a third signal; wherein the second circuit is connected in series between the first circuit and the input port of the processor, and the second circuit includes, along the signal transmission direction: a first diode, the N-end of the first diode is also grounded through a second capacitor and a second resistor connected in parallel, and the N-end of the first diode outputs the third signal.

8. The system for processing interrupts according to claim 7, wherein: The second circuit further includes a Schmitt trigger, wherein the input end of the Schmitt trigger is used to connect to the second signal, and the output end of the Schmitt trigger is connected to the P end of the first diode.

9. The system for processing interrupts according to claim 7, wherein: The second capacitor and the second resistor are selected such that a time constant of the second capacitor and the second resistor is greater than 1 second.

Images