An automated test method for a single board of an airborne stores management system

Abstract

The present invention discloses an automated testing method for a single board of an airborne stores management system. The main functions are as follows: for a specific single board, prepare a test resource spreadsheet containing a discrete quantity address table and a test case table; prepare test bench software for the single board to be tested; connect the board under test and the test bench, and connect the test bench and the PC. After preparing the PC software and importing the test resource table, the automated testing of the single board can be started. The present invention can automatically execute tests and timely count the results, has convenient operability and strong versatility, and improves the efficiency and completeness of single board hardware testing.

Description

Technical Field

[0001] The invention belongs to the technical field of aircraft suspension management, and particularly relates to an automatic testing method for a single board of an airborne suspension management system. Background Art

[0002] An important function of an airborne avionics suspension management system is to manage the signal path between the carrier aircraft and the suspension, and determine under what conditions to output specific signals, or timely collect signals and report them. According to the main signal and auxiliary power interface signal groups specified by GJB1188A, the signal path management functions for multiple hanging points and multiple types are realized by product single boards of different models.

[0003] For a product single board with a CAN bus, it communicates with the main CPU through the CAN bus, receives commands and writes to a memory address, and then the FPGA realizes signal output at the bottom layer; or collects signals by reading the memory address and reports them upward using the CAN bus. For a product single board with only an LBE bus, the main CPU directly writes the command to be output to the memory address, or collects signals by reading the memory address.

[0004] Therefore, the product single board has the characteristics of dense signal paths and rich input / output condition logics. The previous testing method requires connecting a debugging cable to a dedicated single board test bench and the board under test, and inputting the discrete quantity addresses and values of the signals to be tested one by one in the serial port monitoring software, and inputting the discrete quantity addresses of the signals to be tested for viewing. This method highly depends on the manual operation of the tester, and the same repetitive operations need to be performed on each single board of the same model, with a large workload, easy to make mistakes, difficult to handle the situations involving multiple conditions and multiple outputs, and unable to test the single board that communicates with the main CPU board using the CAN bus. Summary of the Invention

[0005] In order to overcome the deficiencies of the prior art, the invention provides an automatic testing method for a single board of an airborne suspension management system. The main functions are as follows: for a specific single board, prepare a test resource spreadsheet containing a discrete quantity address table and a test case table; prepare test bench software for the single board under test; connect the board under test and the test bench, and connect the test bench and the PC. After preparing the PC software and importing the test resource table, the automatic testing of the single board can be started. The invention can automatically execute the test and timely count the results, has convenient operability and strong versatility, and improves the efficiency and completeness of the single board hardware testing.

[0006] The technical solution adopted by the invention to solve its technical problems includes the following steps:

[0007] Step 1: The DUT (Device Under Test) boards are divided into two types: the DUT board with only the LBE bus - abbreviated as the LBE DUT board, and the DUT board with both LBE and CAN buses - abbreviated as the CAN bus DUT board; First, prepare the test resource table;

[0008] Step 1-1: The test resource table includes: the test address table, test cases, and test options. Among them, the test address table is pre-edited, which describes the direction of the DUT signal, the involved memory addresses and offsets, and the definition information of the valid values; The format of the test address table is shown in Table 1;

[0009] Table 1 Test Address Table

[0010]

[0011] Among them, the signals with "IN" in the signal name refer to the acquisition signals of the LBE DUT board. After the test bench outputs the excitation to the write address, it needs to read the corresponding acquisition results from the read address; For the CAN bus DUT board, after reading the data at the read address, it sends it to the test bench through the CAN bus;

[0012] The signals with "OUT" in the signal name refer to the output signals of the LBE DUT board. After the test bench outputs a value to the write address, it needs to read the corresponding output results from the read address; For the CAN bus DUT board, the test bench sends the address and value to be written to the DUT board for execution;

[0013] If the DUT signal depends on preconditions, it is noted in the remarks. After the PC software reads the data, it will be displayed on the interface as a prompt; There can be more than one precondition; If there are multiple expected results, they can be edited in columns 2, 3, and 4 of the read address, with a maximum of 4 expected results supported;

[0014] Step 1-2: For the addresses where the valid value for writing or reading is 0 and the invalid value is 1, when editing the test address table, fill in "Yes" in the write 0 valid or read 0 valid column;

[0015] When the PC software executes the test line, for such signals, it will flip the value of the connect / disconnect column before outputting, or flip the received value before comparing;

[0016] Step 1-3: After the PC software reads the resource table, it is displayed on the software interface and updated and saved to the spreadsheet according to the operator's editing;

[0017] Step 2: Edit the test cases;

[0018] After the PC software reads the resource table, it displays the address table on the user interface. The operator selects the DUT signals according to the test needs, and the name elements of the DUT signals will be displayed in the test area; The display in the test area is also in tabular form, and the format is shown in Table 2:

[0019] Table 2 Test Area Table

[0020]

[0021] The operator performs operations of adding, deleting, modifying, and selecting test rows in the test area; if a new test row is added and a signal name is filled in, the PC software can automatically retrieve the relevant address resources corresponding to this signal name;

[0022] Step 3: Prepare test software and hardware;

[0023] Step 3-1: Prepare the test bench software;

[0024] For the DUT (Device Under Test) with only the LBE bus, the test bench software implements the following functions:

[0025] a) Acquisition test: Periodically receive the test stimuli from the PC through the RS232 bus, write to the corresponding address, then read the address to be collected, and report to the PC software through the RS232 bus when it changes;

[0026] b) Output test: Periodically receive the commands from the PC through the RS232 bus, write to the address to be output, and read the result from the corresponding address and report to the PC software;

[0027] For the DUT with both LBE and CAN buses, the test bench software implements the following functions:

[0028] a) Acquisition test: Periodically receive the test stimuli from the PC through the RS232 bus, write to the corresponding address, then collect the values read by the DUT through the CAN bus, and report to the PC software through the RS232 bus when it changes;

[0029] b) Output test: Periodically receive the write address commands from the PC through the RS232 bus, send them to the DUT through the CAN bus, then read the result from the corresponding address of the test bench and report to the PC software;

[0030] For DUTs of different models, the memory address resources they use are different, and the test bench software needs to initialize the corresponding resources during initialization; therefore, before conducting tests on DUTs of different models, the initialization part of the test bench software needs to be edited, compiled, and downloaded;

[0031] For DUTs of the same model, the software used by the test bench is the same;

[0032] Step 3-2: Prepare the DUT program with CAN bus;

[0033] For the DUT with only the LBE bus, it has no own processor and application program, and is equivalent to being mounted on the main CPU of the test bench. The test bench software directly accesses its resources by reading and writing discrete address values;

[0034] For the DUT board with LBE and CAN bus, it has its own processor and application software, and communicates with the main CPU of the test bench through the CAN bus. Therefore, a dedicated hardware test software program needs to be developed for it. For DUT boards of the same model, the test program used is the same. The test program implements the following functions:

[0035] a) Store the address resources that the single board can access;

[0036] b) Periodically read the addresses that need to be collected and report them to the test bench through the CAN bus when they change;

[0037] c) Periodically receive commands from the test bench through the CAN bus and write them to the addresses that need to be output;

[0038] Step 4: Test execution;

[0039] Step 4-1: Test the communication content;

[0040] The communication content between the PC software and the test bench includes a message header and valid message content. The content of the message header is shown in Table 3:

[0041] Table 3

[0042] Message header element name Meaning Header word Fixed value Message content length The number of bytes of the message content. Command type Initialization or normal test

[0043] The message content sent by the PC software is any number of elements + checksum. The specific element content is shown in Table 4:

[0044] Table 4

[0045]

[0046] The message content received by the PC software is any number of elements + checksum. The specific element content is shown in Table 5:

[0047] Table 5

[0048]

[0049] Between the test bench and the LBE DUT board, communication is only carried out by reading and writing discrete quantity addresses;

[0050] Between the test bench and the CAN bus DUT board, communication is not only carried out by reading and writing discrete quantity addresses, but also through the CAN bus;

[0051] The content sent by the test bench to the DUT CAN bus single board is shown in Table 6. The CAN bus message needs to define the message ID and does not need to define the message header:

[0052] Table 6

[0053] Valid message content element name Meaning Address The address to be output from the test bench to the DUT Bit offset The offset to be output from the test bench to the DUT Value The value to be output from the test bench to the DUT

[0054] The data content received by the test bench from the board under test via the CAN bus is shown in Table 7:

[0055] Table 7

[0056] Valid message content element name Meaning Address The address transmitted by the DUT via the CAN bus Value The current value of this address (up to 32 bits)

[0057] In summary, the communication content between the PC software and the test bench corresponds to the communication content between the test bench and the board under test;

[0058] Step 4-2: Communication check;

[0059] Power on the test bench and click the communication check button on the toolbar. When the data path is normal, the PC software performs a communication check:

[0060] a) Send an initialization command to the test bench software. The initialization command contains all the discrete quantity addresses that the test bench software needs to read periodically subsequently;

[0061] b) After receiving the initialization command, the test bench software returns all the read addresses to the PC software. After receiving them, the PC software considers the communication check normal;

[0062] If the PC software performs tests without performing a communication check, it will prompt that the communication has not been initialized and tests cannot be performed; if the communication check is successful, the PC software gives a prompt;

[0063] Step 4-3: Signal test;

[0064] After the communication check is successful, testing begins; the operator selects some signals or all signals for testing on the PC software; the PC software provides a signal timeout option for calibrating the execution time of each test line; a pure excitation waiting option is provided, which specifies the execution time of the pure excitation output line. For signals in the test address table that only have write addresses and no read addresses, the PC software considers them to be pure excitation outputs;

[0065] When starting to execute a test line, the PC software sends a test command to the test bench and, when the execution duration expires, checks the changed acquisition data sent back by the test bench and displays the check result on the software interface;

[0066] There are 5 types of test results for each test line. The specific meanings are shown in Table 8:

[0067] Table 8

[0068]

[0069] The PC software displays the address, offset, value, and time of the received data in a specific area for the operator to view.

[0070] The beneficial effects of the present invention are as follows:

[0071] The present invention simplifies the manual operation link when performing multiple signal tests on a single board, and avoids the workload of manually inputting the FPGA logical address through the serial port to view the signal input / output. When the test cases are pre-edited and the product batch test is carried out, the technician only needs to connect the board under test, the test bench, and the PC, and it can automatically execute the test and timely count the results, with convenient operability and strong versatility, improving the efficiency and completeness of the single-board hardware test. Brief Description of the Drawings

[0072] Figure 1 It is the equipment participating in the test of the present invention, the single board under test of the LBE bus and the data stream.

[0073] Figure 2 It is the single board under test of the present invention with both LBE bus / CAN bus and the data stream.

[0074] Figure 3 It is the execution flowchart of the PC software of the present invention. Detailed Embodiment

[0075] The present invention will be further described below in conjunction with the drawings and embodiments.

[0076] The present invention mainly designs an automated method for single-board testing of an airborne store management system based on a general single-board test bench, which can conveniently test the signal correctness of single boards with only the LBE bus and single boards with both LBE / CAN buses commonly found in the store management system.

[0077] Aiming at the disadvantages of the previous manual testing using a dedicated single-board test bench, a general single-board test bench with an embedded processor and rich communication interfaces (such as RS232 / LBE / CAN buses, etc.) is used. For the signal conditions / output combinations of the single board under test, a test resource table is designed. The PC software outputs test commands according to the test resource table. The general test bench receives the commands from the PC through the RS232 bus and makes test excitation actions. After collecting the response of the board under test, it is sent back to the PC software through the RS232 bus, and the PC software makes a judgment.

[0078] An automated testing method for a single board of an airborne store management system includes the following steps:

[0079] Step 1: The board under test is divided into a board under test with only the LBE bus - abbreviated as the LBE board under test, and a board under test with both LBE and CAN buses - abbreviated as the CAN bus board under test; first, prepare the test resource table;

[0080] Step 1-1: The test resource table includes: the test address table, test cases, and test options. Among them, the test address table is pre-edited and describes the direction of the signal under test, the involved memory addresses and offsets, and the definition information of valid values. The format of the test address table is shown in Table 1;

[0081] Table 1 Test Address Table

[0082]

[0083] Among them, the signals with IN in the signal name refer to the acquisition signals of the LBE under-test board. After the test bench outputs the excitation to the write address, it needs to read the corresponding acquisition results from the read address; for the CAN bus under-test board, after reading the data at the read address, it sends it to the test bench through the CAN bus;

[0084] The signals with OUT in the signal name refer to the output signals of the LBE under-test board. After the test bench outputs a value to the write address, it needs to read the corresponding output results from the read address; for the CAN bus under-test board, the test bench sends the address and value to be written to the under-test board for execution;

[0085] If the signal under test depends on preconditions, it is noted in the remarks, and the PC software will display it on the interface as a prompt after reading the data; there can be more than one precondition; if there are multiple expected results, they can be edited in columns 2, 3, and 4 of the read address, and up to 4 expected results are supported;

[0086] Step 1-2: For the addresses where the valid value for writing or reading is 0 and the invalid value is 1, when editing the test address table, fill in "Yes" in the Write 0 Valid or Read 0 Valid column;

[0087] When the PC software executes the test line, for such signals, it will flip the value in the Connect / Disconnect column and then output it, or flip the received value and then compare it;

[0088] Step 1-3: After the PC software reads the resource table, it is displayed on the software interface and updated and saved to the spreadsheet according to the operator's editing;

[0089] Step 2: Edit test cases;

[0090] After the PC software reads the resource table, it displays the address table on the user interface. The operator selects the signal to be tested according to the test needs, and the name elements of the signal to be tested will be displayed in the test area; the display in the test area is also in tabular form, and the format is shown in Table 2:

[0091] Table 2 Test Area Table

[0092]

[0093] The operator performs operations of adding, deleting, modifying, and selecting test lines in the test area; if a new test line is added and a signal name is filled in, the PC software can automatically retrieve the relevant address resources corresponding to this signal name;

[0094] Step 3: Prepare the test software and hardware;

[0095] Step 3-1: Prepare the test bench software;

[0096] For the DUT (Device Under Test) with only the LBE bus, the test bench software implements the following functions:

[0097] c) Acquisition test: Periodically receive the test stimuli from the PC through the RS232 bus, write to the corresponding address, then read the address to be acquired, and report it to the PC software through the RS232 bus when it changes;

[0098] d) Output test: Periodically receive the commands from the PC through the RS232 bus, write to the address to be output, and read the result from the corresponding address and report it to the PC software;

[0099] For the DUT with both LBE and CAN buses, the test bench software implements the following functions:

[0100] c) Acquisition test: Periodically receive the test stimuli from the PC through the RS232 bus, write to the corresponding address, then collect the values read by the DUT through the CAN bus, and report it to the PC software through the RS232 bus when it changes;

[0101] d) Output test: Periodically receive the write address commands from the PC through the RS232 bus, send them to the DUT through the CAN bus, then read the result from the corresponding address of the test bench and report it to the PC software;

[0102] For different models of DUTs, the memory address resources they use are different, and the test bench software needs to initialize the corresponding resources during initialization; therefore, before testing different models of DUTs, the initialization part of the test bench software needs to be edited, compiled, and downloaded;

[0103] For the same model of DUT, the software used by the test bench is the same;

[0104] Step 3-2: Prepare the program of the DUT with the CAN bus;

[0105] For the DUT with only the LBE bus, it has no own processor and application program, and is equivalent to being mounted on the main CPU of the test bench. The test bench software directly accesses its resources by reading and writing discrete addresses;

[0106] For the DUT board with LBE and CAN bus, it has its own processor and application software, and communicates with the main CPU of the test bench through the CAN bus. Therefore, a dedicated hardware test software program needs to be developed for it. For DUT boards of the same model, the test program used is the same. The test program realizes the following functions:

[0107] d) Store the address resources that the single board can access;

[0108] e) Periodically read the addresses to be collected, and report them to the test bench through the CAN bus when they change;

[0109] f) Periodically receive commands from the test bench through the CAN bus and write them to the addresses to be output;

[0110] Step 4: Test execution;

[0111] Step 4-1: Test the communication content;

[0112] The communication content between the PC software and the test bench includes a message header and valid message content. The content of the message header is shown in Table 3:

[0113] Table 3

[0114] Message header element name Meaning Header word Fixed value Message content length The number of bytes of the message content. Command type Initialization or normal test

[0115] The message content sent by the PC software is any number of elements + checksum. The specific element content is shown in Table 4:

[0116] Table 4

[0117]

[0118] The message content received by the PC software is any number of elements + checksum. The specific element content is shown in Table 5:

[0119] Table 5

[0120]

[0121] Between the test bench and the LBE DUT board, communication is only carried out by reading and writing discrete address;

[0122] Between the test bench and the CAN bus DUT board, communication is not only carried out by reading and writing discrete addresses, but also through the CAN bus;

[0123] The content sent by the test bench to the DUT CAN bus single board is shown in Table 6. The CAN bus message needs to define the message ID and does not need to define the message header:

[0124] Table 6

[0125] Valid message content element name Meaning Address The address to be output from the test bench to the DUT Bit offset The offset to be output from the test bench to the DUT Value The value to be output from the test bench to the DUT

[0126] The data content received by the test bench from the DUT board via the CAN bus is shown in Table 7:

[0127] Table 7

[0128] Valid message content element name Meaning Address The address transmitted by the DUT via the CAN bus Value The current value of this address (up to 32 bits)

[0129] In summary, the communication content between the PC software and the test bench corresponds to the communication content between the test bench and the DUT board;

[0130] Step 4-2: Communication check;

[0131] Power on the test bench, click the communication check button on the toolbar. When the data path is normal, the PC software performs a communication check:

[0132] a) Send an initialization command to the test bench software. The initialization command contains all the discrete quantity addresses that the test bench software needs to read periodically later;

[0133] b) After receiving the initialization command, the test bench software returns all the read addresses to the PC software. After receiving them, the PC software considers the communication check normal;

[0134] If the PC software performs tests without performing a communication check, it will prompt that the communication has not been initialized and testing cannot be performed; if the communication check is successful, the PC software gives a prompt;

[0135] Step 4-3: Signal testing;

[0136] After the communication check is successful, testing begins; the operator selects some signals or all signals for testing on the PC software; the PC software provides a signal timeout option for calibrating the execution time of each test line; provides a pure excitation waiting option that specifies the execution time of the pure excitation output line. For signals that only have write addresses and no read addresses in the test address table, the PC software considers them to be pure excitation outputs;

[0137] When the PC software starts to execute a test line, it sends a test command to the test bench and, when the execution duration expires, checks the changed acquisition data sent back by the test bench and displays the check result on the software interface;

[0138] There are 5 types of test results for each test line. The specific meanings are shown in Table 8:

[0139] Table 8

[0140]

[0141] The PC software displays the address, offset, value, and time of the received data in a specific area for the operator to view.

Claims

1. An automated test method for a single board of an airborne store management system, characterized in that It includes the following steps: Step 1: The DUT (Device Under Test) board is divided into two types: the DUT board with only the LBE bus - abbreviated as the LBE DUT board, and the DUT board with both LBE and CAN buses - abbreviated as the CAN bus DUT board; First, prepare the test resource table; Step 2: Edit the test cases; After the PC software reads the resource table, it displays the address table on the user interface. The operator selects the signals to be tested according to the test requirements, and the name elements of the signals to be tested will be displayed in the test area; The display in the test area is also in tabular form, and the format is as shown in Table 2: Table 2 Test Area Table The operator performs operations of adding, deleting, modifying, and selecting test rows in the test area; If a new test row is added and the signal name is filled in, the PC software can automatically retrieve the relevant address resources corresponding to this signal name; Step 3: Prepare the test software and hardware; Step 3-1: Prepare the test bench software; For the DUT board with only the LBE bus, the test bench software implements the following functions: a) Acquisition test: Periodically receive the test stimuli from the PC through the RS232 bus, write to the corresponding address, then read the address to be collected, and report to the PC software through the RS232 bus when it changes; b) Output test: Periodically receive the commands from the PC through the RS232 bus, write to the address to be output, and read the results from the corresponding address and report to the PC software; For the DUT board with both LBE and CAN buses, the test bench software implements the following functions: a) Acquisition test: Periodically receive the test stimuli from the PC through the RS232 bus, write to the corresponding address, then collect the values read by the DUT board through the CAN bus, and report to the PC software through the RS232 bus when it changes; b) Output test: Periodically receive the write address commands from the PC through the RS232 bus, send them to the DUT board through the CAN bus, and then read the results from the corresponding address of the test bench and report to the PC software; For different models of DUT boards, the memory address resources they use are different. The test bench software needs to initialize the corresponding resources during initialization; Therefore, before testing different models of DUT boards, the initialization part of the test bench software needs to be edited, compiled, and downloaded; For the same model of DUT board, the software used by the test bench is the same; Step 3-2: Prepare the DUT board program with the CAN bus; For the DUT board with only the LBE bus, it has no own processor and application program, and is equivalent to being mounted on the main CPU of the test bench. The test bench software directly accesses its resources by reading and writing discrete address; For the DUT board with both LBE and CAN buses, it has its own processor and application software, and communicates with the main CPU of the test bench through the CAN bus. Therefore, a special software program for hardware testing needs to be developed for it; For the same model of DUT board, the test program used is the same; The test program implements the following functions: a) Store the address resources that the single board can access; b) Periodically read the addresses to be collected, and report to the test bench through the CAN bus when it changes; c) Periodically receive the commands from the test bench through the CAN bus and write to the address to be output; Step 4: Execute the test.

2. The automated test method for a single board of an airborne suspension management system according to claim 1, wherein step 1 is specifically as follows: Step 1-1: The test resource table includes: The test address table, test cases, and test options, where the test address table is pre-edited and describes the direction of the signal under test, the involved memory addresses and offsets, and the definition information of valid values; the format of the test address table is shown in Table 1; Table 1 Test Address Table Among them, the signals with IN in the signal name refer to the acquisition signals of the LBE board under test. After the test bench outputs the excitation to the write address, it needs to read the corresponding acquisition results from the read address; for the CAN bus board under test, after reading the data at the read address, it sends it to the test bench through the CAN bus; The signals with OUT in the signal name refer to the output signals of the LBE board under test. After the test bench outputs a value to the write address, it needs to read the corresponding output results from the read address; for the CAN bus board under test, the test bench sends the address and value to be written to the board under test for execution; If the signal under test depends on preconditions, it shall be noted in the remarks, and the PC software will display it on the interface as a prompt after reading the data; there is more than one precondition; if there are multiple expected results, they shall be edited in columns 2, 3, and 4 of the read address, and up to 4 expected results are supported; Step 1-2: For the addresses with a valid value of 0 and an invalid value of 1 for writing or reading, when editing the test address table, fill in "yes" in the column of write 0 valid or read 0 valid; When the PC software executes the test line, for such signals, it will flip the value in the connect / disconnect column and then output it, or flip the received value and then compare it; Step 1-3: After the PC software reads the resource table, it displays it on the software interface and updates and saves it to the spreadsheet according to the operator's editing.

3. The automated test method for a single board of an airborne suspension management system according to claim 1, wherein step 4 is specifically as follows: Step 4-1: Test the communication content; The communication content between the PC software and the test bench includes a message header and valid message content. The content of the message header is shown in Table 3: Table 3 The message content sent by the PC software is any number of elements + checksum. The specific element content is shown in Table 4: Table 4 The message content received by the PC software is any number of elements + checksum. The specific element content is shown in Table 5: Table 5 Between the test bench and the LBE board under test, communication is only carried out by reading and writing discrete quantity addresses; Between the test bench and the CAN bus board under test, communication is not only carried out by reading and writing discrete quantity addresses, but also through the CAN bus; The content sent by the test bench to the CAN bus single board under test is shown in Table 6. The CAN bus message needs to define the message ID and does not need to define the message header: Table 6 The data content received by the test bench from the CAN bus board under test is shown in Table 7: Table 7 In summary, the communication content between the PC software and the test bench corresponds to the communication content between the test bench and the board under test; Step 4-2: Communication check; Power on the test bench, click the communication check button on the toolbar, and when the data path is normal, the PC software performs a communication check: a) Send an initialization command to the test bench software, and the initialization command contains all the discrete quantity addresses that the test bench software needs to cycle read subsequently; b) After the test bench software receives the initialization command, it returns all read addresses to the PC software. After receiving them, the PC software considers the communication check normal; If the PC software conducts tests without performing a communication check, it will prompt that the communication has not been initialized and tests cannot be performed; if the communication check is successful, the PC software will give a prompt; Step 4-3: Signal testing; After the communication check is successful, testing begins; the operator selects some signals or all signals for testing on the PC software; the PC software provides a signal timeout option for calibrating the execution time of each test line; it also provides a pure excitation waiting option that specifies the execution time of the pure excitation output line. For signals that only have write addresses and no read addresses in the test address table, the PC software considers them to be pure excitation outputs; When starting to execute a test line, the PC software sends a test command to the test bench and, when the execution duration expires, checks the changed acquisition data sent back by the test bench and displays the check result on the software interface; There are five types of test results for each test line, and their specific meanings are shown in Table 8: Table 8 The PC software displays the address, offset, value, and time of the received data in a specific area for the operator to view.

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