An asynchronous memory adaptive clock generation circuit and method

Abstract

The application provides an asynchronous memory adaptive clock generation circuit and method, comprising: a multi-pulse generation convergence circuit, which is used for converging generated multi-path narrow high pulse signals; a filtering and inverting circuit, which is used for filtering and inverting the converged narrow high pulse sequence signals; a clock reconstruction circuit, which is used for performing clock reconstruction processing on the filtered and inverted low pulse signals to generate an adaptive clock; the output end of the multi-pulse generation convergence circuit is connected with the input end of the filtering and inverting circuit, and the output end of the filtering and inverting circuit is connected with the input end of the clock reconstruction circuit; the adaptive clock can stably latch an effective address, the memory can orderly complete a read / write operation in the trigger clock period, and the access rate of the system controller to the memory is improved.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to an asynchronous memory adaptive clock generation circuit and method. Background Technology

[0002] Currently, single-chip parallel asynchronous memory (PARM) is still widely used in electronic systems for data buffering, instruction storage, and in-memory computing, such as RSRAM, parallel NOR flash, parallel MRAM, and parallel RRAM. These asynchronous memories have simple parallel bus interfaces, are easy to interconnect, and facilitate bus sharing; they only respond to changes in address or control signals when reading data, resulting in low power consumption; as instruction caches, they also have the advantage of execute-in-place (XIP) instructions, allowing instruction code to run directly in memory without being read into system RAM, simplifying system program scheduling. Compared to synchronous memories like DDR, PARM asynchronous memories do not have a clock port on their interface. Instead, they use address and chip select signal transitions to trigger memory read and write operations. The address change period is equivalent to the synchronous memory clock cycle, while when the address and chip select control signals are unchanged, the asynchronous memory is in a low-power standby state. Therefore, parallel asynchronous memory contains an address transition detector (ATD) circuit. The main function of this circuit is to detect the transitions of external address and chip select control signals and generate a clock signal. The clock signal controls the writing and reading of data in the memory.

[0003] Due to the delay differences between each output I / O of the front-end controller and the differences in signal board-level routing paths, the arrival times of each signal on the address bus and control lines to the memory pins are unequal, generally referred to as signal input delay skew. Input signal skew acts as an input interference source for the ATD circuit, requiring special filtering. The clock is generated triggered by the transition of the first input signal, and the generated clock latches the address. However, in practice, the skew between addresses differs in each application scenario, which can lead to incorrect or unstable address latching by the clock, ultimately affecting the read of data from unexpected addresses. A common solution is to calculate the skew between signals based on various applications and fix the clock generated by the ATD for a certain period to ensure that the clock can correctly latch stable and valid addresses. However, this method incurs significant memory access delay overhead, especially when the input signal skew remains constant; the ATD clock delay then becomes a bottleneck for improving high-speed memory access time. Summary of the Invention

[0004] This invention provides an adaptive clock generation circuit and method for asynchronous memory, the purpose of which is to generate an adaptive trigger clock by sensing the transition of the address line, thereby reducing the read delay of the asynchronous memory and improving the access speed of the system controller to the memory.

[0005] To achieve the above objectives, the present invention provides an asynchronous memory adaptive clock generation circuit, comprising:

[0006] A multi-pulse generation and convergence circuit is used to converge multiple narrow-high pulse signals generated.

[0007] The filter inversion circuit is used to filter and invert the narrow high-pulse sequence signal obtained after convergence;

[0008] The clock reconstruction circuit is used to reconstruct the clock from the low pulse signal obtained after filtering and inversion, and generate an adaptive clock.

[0009] The output of the multi-pulse generation and convergence circuit is connected to the input of the filter inversion circuit, and the output of the filter inversion circuit is connected to the input of the clock reconstruction circuit.

[0010] Furthermore, the multi-pulse generation and convergence circuit includes: multiple first delay units, multiple XOR gates, and a first OR gate;

[0011] Multiple delay units correspond one-to-one with multiple XOR gates. The output of each delay unit is connected to the input of the XOR gate. The output of each XOR gate is connected to the input of the first OR gate. The output of the first OR gate is connected to the input of the filter inversion circuit.

[0012] Furthermore, the filter inversion circuit includes: a second delay unit, a first AND gate, a second AND gate, a third AND gate, a second OR gate, and a first inverter. The input of the second delay unit is connected to the output of the first OR gate. The output of the second delay unit is connected to the second input of the first AND gate and the first input of the second AND gate. The second input of the second AND gate and the first input of the third AND gate are connected to the output of the first OR gate. The first input of the first AND gate is connected to the output of the second OR gate. The second input of the third AND gate is connected to the output of the second OR gate. The outputs of the first AND gate, the second AND gate, and the third AND gate are all connected to the input of the second OR gate. The output of the second OR gate is connected to the input of the first inverter. The output of the first inverter is connected to the clock reconstruction circuit.

[0013] Furthermore, the clock reconstruction circuit includes: a third delay unit, a second inverter, and a fourth AND gate. The input of the third delay unit is connected to the output of the second OR gate, the output of the third delay unit is connected to the input of the second inverter, the output of the second inverter is connected to the first input of the fourth AND gate, and the second input of the fourth AND gate is connected to the input of the third delay unit.

[0014] Furthermore, it also includes:

[0015] An input latch circuit is used to latch the input signal using an adaptive clock.

[0016] The input latch circuit consists of a set of flip-flops, and the CK port of the flip-flops is connected to the output of the fourth AND gate.

[0017] The present invention also provides an asynchronous memory adaptive clock generation method, applied to the above-mentioned asynchronous memory adaptive clock generation circuit, comprising:

[0018] Step 1: The memory controller accesses the asynchronous memory control address bus;

[0019] Step 2: Cause the rising or falling edge of the address bus to transition, generating multiple narrow high pulse signals with different phases;

[0020] Step 3: Combine multiple narrow high-pulse signals with different phases to generate narrow high-pulse sequence signals with different widths;

[0021] Step 4: Filter and invert the narrow high pulse sequence signals with different widths to obtain the adaptive initial low pulse signal;

[0022] Step 5: Reconstruct the clock from the adaptive initial low pulse signal to generate an adaptive clock.

[0023] Furthermore, step 1 includes:

[0024] The storage controller triggers access to the asynchronous memory based on changes in the address cycle, reads the data stored at the address at the time of access, and collects the data latched at the address at fixed intervals.

[0025] Furthermore, step 4 includes:

[0026] Filter narrow and high pulse sequence signals with different widths to remove glitch low pulses generated during the convergence process of the narrow and high pulse sequence signals;

[0027] The narrow high-pulse sequence signal after filtering out burrs and low pulses is inverted to generate an adaptive initial low-pulse signal.

[0028] The above-described solution of the present invention has the following beneficial effects:

[0029] The adaptive clock generation circuit of this invention generates an adaptive clock by detecting the transition of the last address line within a certain range of address skew. This adaptive clock stably latches valid addresses, allowing the memory to complete read and write operations in an orderly manner within the triggered clock cycle. Compared to traditional ATD circuits, the circuit uses a simple logic gate structure and ensures that each triggered clock cycle is a valid read / write cycle, avoiding multiple invalid accesses and resulting in lower power consumption. It can also be more widely applied to scenarios with different address skews. Especially when the system input signal skew is small, this invention can adaptively follow and shorten the clock generation delay, reducing the read delay of the asynchronous memory and improving the system controller's memory access speed.

[0030] Other beneficial effects of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0031] Figure 1 This is a structural diagram of the adaptive clock generation circuit in an embodiment of the present invention;

[0032] Figure 2 This is a timing diagram for the adaptive clock generation in an embodiment of the present invention;

[0033] Figure 3 This is a flowchart illustrating the adaptive clock generation method in an embodiment of the present invention.

[0034] Figure 4 This is a read timing diagram for asynchronous memory address access control in an embodiment of the present invention. Detailed Implementation

[0035] To make the technical problems, solutions, and advantages of this invention clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0036] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the circuit or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] This invention addresses existing problems by providing an adaptive clock generation circuit and method for asynchronous memory.

[0040] like Figure 1 As shown, an embodiment of the present invention provides an asynchronous memory adaptive clock generation circuit, comprising:

[0041] A multi-pulse generation and convergence circuit is used to converge multiple narrow-high pulse signals generated.

[0042] The filter inversion circuit is used to filter and invert the narrow high-pulse sequence signal obtained after convergence;

[0043] The clock reconstruction circuit is used to reconstruct the clock from the low pulse signal obtained after filtering and inversion, and generate an adaptive clock.

[0044] The output of the multi-pulse generation and convergence circuit is connected to the input of the filter inversion circuit, and the output of the filter inversion circuit is connected to the input of the clock reconstruction circuit.

[0045] Specifically, the multi-pulse generation and convergence circuit includes: multiple first delay units delay0, multiple XOR gates U1, and a first OR gate K1; the multiple delay units correspond one-to-one with the multiple XOR gates U1, the output of each first delay unit delay0 is connected to the input of the XOR gate U1, the output of each XOR gate U1 is connected to the input of the first OR gate K1, and the output of the first OR gate K1 is connected to the input of the filter inversion circuit;

[0046] The signals output from the address lines A[0]~A[n] pass through the first delay unit delay0 and the initial signal without delay, respectively, and are input to the XOR gate U1. The XOR operation generates the initial pulse. The delay of the first delay unit delay0 determines the width of the initial pulse, and finally generates multiple narrow high pulse signals with different phases. The multiple narrow high pulse signals with different phases are converged into a narrow high pulse sequence CK0 with different widths through the first OR gate K1, and the narrow high pulse sequence CK0 with different widths is input to the filter inversion circuit.

[0047] Specifically, the filtering and inverting circuit includes: a second delay unit delay1, a first AND gate I1, a second AND gate I2, a third AND gate I3, a second OR gate K2, and a first inverter J1. The input of the second delay unit delay1 is connected to the output of the first OR gate K1. A narrow pulse sequence CK0 of different widths is input to the second delay unit delay1. The output of the second delay unit delay1 is connected to the second input of the first AND gate I1 and the first input of the second AND gate I2 to filter out narrow pulses with a width less than delay1. To ensure the safe passage of valid pulses (pulse width ≥ delay0), delay0 ≥ 2 * delay1 can be set. The second input of the second AND gate I2 and the first input of the third AND gate I3 are connected to the output of the first OR gate K1 to achieve data latching. The first input of the first AND gate I1 is connected to the output of the second OR gate K2, the second input of the third AND gate I3 is connected to the output of the second OR gate K2, the outputs of the first AND gate I1, the second AND gate I2, and the third AND gate I3 are all connected to the input of the second OR gate K2, the output of the second OR gate K2 is connected to the input of the first inverter J1, and the output of the first inverter J1 is connected to the clock reconstruction circuit. The filtered and extended pulse signal is passed through the first inverter J1 to obtain an adaptive initial low pulse CK1 with different widths. The low pulse width of the initial low pulse CK1 is greater than or equal to delay0. The initial low pulse CK1 is delayed by delay1 relative to the narrow high pulse sequence CK0. The width and minimum interval of the low pulse are determined by the address skew of different application scenarios, which reflects the adaptive feature.

[0048] Specifically, the clock reconstruction circuit includes: a third delay unit delay2, a second inverter J2, and a fourth AND gate I4. The input of the third delay unit delay2 is connected to the output of the second OR gate K2, the output of the third delay unit delay2 is connected to the input of the second inverter J2, the output of the second inverter J2 is connected to the first input of the fourth AND gate I4, and the second input of the fourth AND gate I4 is connected to the input of the third delay unit delay2.

[0049] The adaptive initial low pulse CK1, after passing through the third delay unit delay2 and inverter J2, serves as the first input signal of the fourth AND gate I4. The undelayed adaptive initial low pulse CK1 serves as the second input signal of the fourth AND gate I4. After passing through the fourth AND gate I4, an adaptive clock CK2 is generated. The high pulse width of the adaptive clock CK2 is delay2, and the minimum high pulse interval of the adaptive clock CK2 is delay0 + delay1. The timing sequence for generating the adaptive clock for the asynchronous memory is as follows: Figure 2 As shown.

[0050] Specifically, it also includes:

[0051] An input latch circuit is used to latch signals using an adaptive clock.

[0052] The input latch circuit consists of a flip-flop group, and the CK port of the flip-flop group is connected to the output of the fourth AND gate I4.

[0053] All address bus A[n:0], data bus D[n:0], chip select enable #E, and read / write enable #W signals serve as data inputs to the Flip-flop flip-flop group, while the adaptive clock CK2 serves as the clock input to the Flip-flop flip-flop group. This enables the latching of all memory signals, and the latched address, data, and control signals are synchronized with the adaptive clock CK2.

[0054] After being latched, the address is decoded to select the data in the memory array. The sensitive amplifier is turned on and off by the adaptive clock CK2 to achieve rapid output of the selected data. The minimum high pulse interval of the adaptive clock CK2 is determined by the external logic of the memory (address decoding, sensitive amplification, input / output control logic, etc.) triggered by the adaptive clock CK2 and the maximum delay Tckq from the memory array to the data output. The minimum value of delay0 + delay1 is greater than the maximum value of the delay Tckq.

[0055] like Figure 3 As shown, an embodiment of the present invention also provides an asynchronous memory adaptive clock generation method, applied to the above-described asynchronous memory adaptive clock generation circuit, comprising:

[0056] Step 1: When the storage controller accesses the asynchronous memory, it controls the address bus, which includes address lines A[0] to A[n].

[0057] Step 2: Cause the rising or falling edge of the address bus to transition, generating multiple narrow high pulse signals with different phases;

[0058] Step 3: Combine multiple narrow high-pulse signals with different phases to generate narrow high-pulse sequence signals with different widths;

[0059] Step 4: Filter and invert the narrow high pulse sequence signals with different widths to obtain adaptive initial low pulse signals with different widths;

[0060] Step 5: Reconstruct the clock from the adaptive initial low pulse signals with different widths to generate an adaptive clock.

[0061] Specifically, embodiments of the present invention employ a memory controller such as a DSP or FPGA to access the parallel port asynchronous memory, using address cycles t. AVAV The change triggers access to the parallel port asynchronous memory, and reads valid data t from the parallel port asynchronous memory. AVQV Then, data stored at the address is collected at fixed intervals, with the specific timing as follows: Figure 4 As shown.

[0062] The memory controller accesses the random address of the asynchronous memory, so that the rising or falling edge transition of each address line (A[0]~A[n]) can generate a clock independently. For example, if the address line signal of A[0] is XORed to generate an initial pulse, each address line output by the memory controller may transition to generate a clock. Furthermore, due to the pre-stage driver and PCB wiring, the signal reaching the parallel asynchronous memory port has a delay skew, which ultimately generates multiple narrow high pulse signals with different phases.

[0063] Multiple narrow-high pulse signals with different phases are converged to generate a narrow-high pulse sequence CK0 with different widths.

[0064] The narrow high-pulse sequences CK0 with varying widths are filtered and inverted to remove glitch low pulses generated during the convergence process of the CK0 sequences. The reference rising edge for adaptive clock triggering is then extracted by inverting the filtered CK0 sequences. To ensure the safe passage of valid pulses, the filtered and inverted CK0 sequences are further processed to obtain the adaptive initial low pulse CK1. The pulse width of this adaptive initial low pulse CK1 varies, and its low pulse width and minimum skew interval are determined by the address skew of different application scenarios, reflecting its adaptive nature.

[0065] The adaptive initial low pulse signals with different widths are clocked and reconstructed to generate an adaptive clock CK2 with a fixed pulse width. Specifically, when the adaptive initial low pulse signals with different widths pass through the first delay unit delay2, they output adaptive low pulse signals with different widths for a delay time of delay2. After passing through the second inverter J2, these signals output adaptive high pulse signals with different widths for a delay time of delay2. These signals, together with the original adaptive initial low pulses CK1 with different widths, are passed through the fourth AND gate I4 to finally generate the adaptive high pulse clock CK2 with a fixed pulse width.

[0066] This invention generates an adaptive clock by detecting the transition of the last address line within a certain address skew range. This adaptive clock stably latches valid addresses, allowing the parallel asynchronous memory to complete read and write operations in an orderly manner within this trigger clock cycle. Compared to traditional ATD circuits, this invention detects the change of the last address line within a certain time frame, ensuring that each triggered clock cycle is a valid read / write cycle, avoiding multiple invalid accesses, and resulting in lower power consumption. It can also be more widely applied to scenarios with different skew ranges between addresses. Especially when the system input signal skew is small, this invention can adaptively follow and shorten the clock delay, reducing the read latency of the asynchronous memory and improving the system controller's memory access speed.

[0067] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An adaptive clock generation circuit for an asynchronous memory, characterized in that, include: A multi-pulse generation and convergence circuit is used to converge multiple narrow-high pulse signals generated. The multi-pulse generation and convergence circuit includes: multiple first delay units, multiple XOR gates, and a first OR gate; The filter inversion circuit is used to filter and invert the narrow high-pulse sequence signal obtained after convergence; The clock reconstruction circuit is used to reconstruct the clock from the low pulse signal obtained after filtering and inversion, and generate an adaptive clock. The clock reconstruction circuit includes: a third delay unit, a second inverter, and a fourth AND gate. The input terminal of the third delay unit is connected to the output terminal of the filter inversion circuit. The output terminal of the third delay unit is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the first input terminal of the fourth AND gate. The second input terminal of the fourth AND gate is connected to the input terminal of the third delay unit. Each of the first delay units corresponds one-to-one with the XOR gates. The output of each first delay unit is connected to the first input of each XOR gate. The second input of each XOR gate is used to input the initial signal without delay. The output of each XOR gate is connected to the input of the first OR gate. The output of the first OR gate is connected to the input of the filter inversion circuit. The output of the filter inversion circuit is connected to the input of the clock reconstruction circuit. An input latch circuit is used to latch the input signal using the adaptive clock. The input latch circuit is composed of a set of flip-flops, and the CK port of the set of flip-flops is connected to the output of the fourth AND gate.

2. The asynchronous memory adaptive clock generation circuit according to claim 1, characterized in that, The filtering and inverting circuit includes: a second delay unit, a first AND gate, a second AND gate, a third AND gate, a second OR gate, and a first inverter. The input terminal of the second delay unit is connected to the output terminal of the first OR gate. The output terminal of the second delay unit is connected to the second input terminal of the first AND gate and the first input terminal of the second AND gate. The second input terminal of the second AND gate and the first input terminal of the third AND gate are connected to the output terminal of the first OR gate. The first input terminal of the first AND gate is connected to the output terminal of the second OR gate. The second input terminal of the third AND gate is connected to the output terminal of the second OR gate. The output terminals of the first AND gate, the second AND gate, and the third AND gate are all connected to the input terminal of the second OR gate. The output terminal of the second OR gate is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the clock reconstruction circuit.

3. An asynchronous memory adaptive clock generation method, applied to the asynchronous memory adaptive clock generation circuit according to any one of claims 1-2, characterized in that, include: Step 1: The memory controller controls the address bus when accessing the asynchronous memory; Step 2: The rising or falling edge of the address bus is switched to generate multiple narrow high pulse signals with different phases; Step 3: The multiple narrow high-pulse signals with different phases are converged to generate narrow high-pulse sequence signals with different widths; Step 4: Filter and invert the narrow high pulse sequence signals with different widths to obtain multiple adaptive initial low pulse signals; Step 5: Reconstruct the clock from the multiple adaptive initial low pulse signals to generate an adaptive clock.

4. The asynchronous memory adaptive clock generation method according to claim 3, characterized in that, Step 1 includes: The storage controller accesses the asynchronous memory triggered by changes in the address cycle, reads the data stored at the address at the time of access, and collects the data stored at the address at a fixed period.

5. The asynchronous memory adaptive clock generation method according to claim 4, characterized in that, Step 4 includes: The narrow high pulse sequence signals with different widths are filtered to remove the glitch low pulses generated during the convergence process of the narrow high pulse sequence signals. The narrow high-pulse sequence signal after filtering out the burr low pulses is inverted to generate multiple adaptive initial low-pulse signals.

Images