Non-volatile memory chip testing system and non-volatile memory chip testing method

Abstract

This invention discloses a non-volatile memory chip testing system and method. The testing system includes a host computer, a system control motherboard, and multiple chip-to-test (DUT) daughterboards. The host computer sends test commands and test algorithm data to the system control motherboard and receives test results forwarded by the system control motherboard. The system control motherboard receives and parses the test commands and test algorithm data sent by the host computer, distributes the test commands and test algorithm data to the multiple DUT daughterboards, and forwards the test results generated by the DUT daughterboards to the host computer. Each DUT daughterboard includes a Zynq main control unit and a non-volatile memory chip. The Zynq main control unit receives and parses the test commands, completes the test of the non-volatile memory chip using a test graphics algorithm, and acquires and analyzes the test data of the non-volatile memory chip to generate and forward test results to the system control motherboard. This solution can improve chip testing efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a non-volatile memory chip testing system and a non-volatile memory chip testing method. Background Technology

[0002] With the development of the memory industry, the testing of non-volatile memory chips is playing an increasingly important role. It is an indispensable step for a memory chip to reach the market, ensuring its stability and reliability. Testing modes for non-volatile memory chips generally include scan, BIST (Built-in Self-Test), and IO (input / output) testing, each with different testing objectives. Currently, chip testing largely relies on large-scale ATE (automatic test equipment) test machines. By applying specific stimuli to the chip's IO pins and observing the return values, comparing them with expected values, it can be determined whether the chip is functioning correctly. However, ATE test machines often cost millions, making it difficult for ordinary laboratories to possess an ATE testing environment. Furthermore, in chip testing modes, ATE test machines cannot use traditional software debugging methods, greatly limiting their flexibility. Therefore, providing a low-cost, highly flexible, and configurable testing system has become an urgent problem to be solved. Summary of the Invention

[0003] The main technical problem solved by this invention is to provide a non-volatile memory chip testing system and a non-volatile memory chip testing method to improve the testing efficiency of non-volatile memory chips.

[0004] To address the aforementioned technical problems, one technical solution adopted by this invention is to provide a non-volatile memory chip testing system. The non-volatile memory chip testing system includes a host computer, a system control motherboard, and multiple chip daughterboards under test. The host computer is connected to the system control motherboard via a network communication protocol. The host computer is used to send test commands and test algorithm data to the system control motherboard, and to receive test results forwarded by the system control motherboard, and generate a test report. The system control motherboard is connected to the multiple chip daughterboards under test via an industrial bus. The system control motherboard is used to receive and parse the test commands and test algorithm data sent by the host computer. The system receives and parses the test instructions, distributes the test algorithm data and test commands to the plurality of chip sub-boards under test, and forwards the test results generated by the chip sub-boards under test to the host computer. The chip sub-boards under test include a Zynq main control unit and a non-volatile memory chip, and the Zynq main control unit is connected to the non-volatile memory chip. The Zynq main control unit is used to receive and parse the test instructions, complete the test of the non-volatile memory chip through the test graph algorithm corresponding to the test algorithm data, and acquire and analyze the test data of the non-volatile memory chip to generate and forward the test results to the system control motherboard.

[0005] The network communication protocol includes the MODBUS-TCP protocol, and the host computer is also used to send low-level software upgrade instructions to the system control motherboard; the industrial bus includes EtherCAT bus, RS485 bus and CAN bus, and the system control motherboard is used to update the IP core program of the multiple chip daughterboards under test according to the low-level software upgrade instructions.

[0006] The system control motherboard includes a flash memory unit, a memory unit, and an SD card. The flash memory unit stores the BOOT program and the FPGA program. The memory unit stores the running program and cached data. The SD card stores device log information and is used for production debugging and burning the BOOT program. Alternatively, the chip under test (DUT) daughterboard further includes a high-speed cache unit connected to the Zynq main control unit, which is used for large-capacity data caching.

[0007] The Zynq main control unit includes a processing system module and a programmable logic module. The processing system module and the programmable logic module exchange data via an AXI bus. The processing system module is connected to the system control motherboard and is used to receive and parse the test instructions, use the test pattern algorithm to test the non-volatile memory chip, and receive and analyze the test data of the non-volatile memory chip returned by the programmable logic module to generate and forward the test results to the system control motherboard. The programmable logic module is connected to the non-volatile memory chip and is used to complete the timing control of the non-volatile memory chip and the high and low levels of the logic pins of the non-volatile memory chip according to the read and write requests corresponding to the test pattern algorithm, thereby completing the read and write function test of the non-volatile memory chip.

[0008] The non-volatile memory chip is a NAND Flash memory chip.

[0009] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a non-volatile memory chip testing method. This method is applied to a non-volatile memory chip testing system, which includes a host computer, a system control motherboard, and multiple chip-to-test (DUT) daughterboards. The host computer is connected to the system control motherboard via a network communication protocol, and the system control motherboard is connected to the multiple DUT daughterboards via an industrial bus. Each DUT daughterboard includes a Zynq main control unit and a non-volatile memory chip, with the Zynq main control unit connected to the non-volatile memory chip. The non-volatile memory chip testing method includes: the host computer sending test commands and test algorithm data to the system control motherboard; the system... The system control motherboard receives and parses the test instructions and test algorithm data sent by the host computer, and distributes the test instructions and test algorithm data to the multiple chip-under-test (UTC) daughterboards. In each UTC daughterboard, the Zynq main control unit receives and parses the test instructions, completes the test of the non-volatile memory chip using the test graph algorithm corresponding to the test algorithm data, acquires and analyzes the test data of the non-volatile memory chip, generates test results based on the test data, and forwards the test results to the system control motherboard. The system control motherboard receives and forwards the test results returned by the multiple UTC daughterboards to the host computer. The host computer receives the test results returned by the system control motherboard and generates a test report.

[0010] The network communication protocol includes the MODBUS-TCP protocol, and the industrial bus includes the EtherCAT bus, RS485 bus, and CAN bus. The method further includes: the host computer sending a low-level software upgrade instruction to the system control motherboard; and the system control motherboard updating the IP core program of the multiple chip daughterboards under test according to the low-level software upgrade instruction.

[0011] The Zynq main control unit includes a processing system module and a programmable logic module. The processing system module and the programmable logic module exchange data via an AXI bus. The processing system module is connected to the system control motherboard, and the programmable logic module is connected to the non-volatile memory chip. The Zynq main control unit receives and parses the test instructions, performs testing on the non-volatile memory chip using the test pattern algorithm corresponding to the test algorithm data, acquires and analyzes the test data of the non-volatile memory chip, generates test results based on the test data, and forwards the test results to the system control motherboard. Specifically, the steps include: the processing system module receiving and parsing the test instructions and performing testing on the non-volatile memory chip using the test pattern algorithm; the programmable logic module performing timing control and setting the high and low levels of the logic pins of the non-volatile memory chip according to the read / write requests corresponding to the test pattern algorithm; and the processing system module receiving and analyzing the test data of the non-volatile memory chip returned by the programmable logic module to generate and forward the test results to the system control motherboard.

[0012] The step of testing the non-volatile memory chip using the test pattern algorithm includes: reading the chip ID of the non-volatile memory chip and determining whether the chip ID is consistent with the chip technical manual; if consistent, testing the memory array of the non-volatile memory chip using the test pattern algorithm; if inconsistent, determining that the non-volatile memory chip is unqualified.

[0013] The step of testing the storage array of the non-volatile memory chip using the test pattern algorithm includes: testing the current storage block of the storage array; writing and reading data from the current storage block according to the test pattern algorithm; determining whether the written data and the read data are the same; if they are the same, erasing the data in the current storage block to determine that the current storage block has passed the test, and testing the next storage block; if they are different, determining that the current storage block has failed the test, and recording the address information of the current storage block.

[0014] The beneficial effects of this invention are as follows: Unlike existing technologies, the non-volatile memory chip testing system of this invention includes a host computer, a system control motherboard, and multiple chip daughterboards under test (DUTs). The host computer is connected to the system control motherboard via a network communication protocol. The host computer is used to send test commands and test algorithm data to the system control motherboard, receive test results forwarded by the system control motherboard, and generate test reports. The system control motherboard is connected to the multiple DUTs via an industrial bus. The system control motherboard is used to receive and parse the test commands and test algorithm data sent by the host computer, distribute the test commands and test algorithm data to the multiple DUTs, and forward the test results generated by the DUTs to the host computer. The DUTs include a Zynq main control unit and a non-volatile memory chip, and the Zynq main control unit is connected to the non-volatile memory chip. The Zynq main control unit is used to receive and parse the test commands, complete the test of the non-volatile memory chip using the test graph algorithm corresponding to the test algorithm data, and acquire and analyze the test data of the non-volatile memory chip to generate and forward the test results to the system control motherboard. By placing the Zynq main control unit and the non-volatile memory chip on the same chip under test (DUT) daughterboard, a high-speed transmission frequency of up to 200MHz can be achieved. Under the same test pattern algorithm complexity, test time can be shortened and test efficiency improved. In addition, the system control motherboard is connected to multiple DUT daughterboards via an industrial bus. Thus, the system control motherboard can distribute test commands and test algorithm data to multiple DUT daughterboards, enabling multiple DUT daughterboards to test the non-volatile memory chip simultaneously, thereby improving test efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0016] Figure 1 This is a schematic diagram of the structure of an embodiment of the non-volatile memory chip testing system of this application;

[0017] Figure 2 for Figure 1 A schematic diagram of the structure of an embodiment of the central system control motherboard;

[0018] Figure 3 for Figure 1 A schematic diagram of the structure of a chip-to-beam sub-board according to an embodiment;

[0019] Figure 4 This is a flowchart illustrating an embodiment of the non-volatile memory chip testing method of this application;

[0020] Figure 5 for Figure 4 A flowchart illustrating step S43 of an embodiment;

[0021] Figure 6 This is a schematic diagram of the process of testing the memory array of the non-volatile memory chip using the test graphics algorithm described in this application.

[0022] Figure 7 for Figure 6 Step S62 is a flowchart of an embodiment.

[0023] Figure 8 This is a flowchart illustrating the process of testing a non-volatile memory chip's memory array using a test graphics algorithm in an application scenario. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] Please see Figures 1 to 3 ,in, Figure 1 This is a schematic diagram of one embodiment of the non-volatile memory chip testing system of this application. Figure 2 for Figure 1 A schematic diagram of the structure of an embodiment of the central system control motherboard. Figure 3 for Figure 1A schematic diagram of the structure of an embodiment of the chip daughterboard under test. In one embodiment, the non-volatile memory chip testing system includes a host computer 10, a system control motherboard 20, and multiple chip-under-test (DUT) daughter boards 30. The host computer 10 is connected to the system control motherboard 20 via a network communication protocol. The host computer 10 is used to send test commands and test algorithm data to the system control motherboard 20, receive test results forwarded by the system control motherboard 20, and generate test reports. The system control motherboard 20 is connected to the multiple DUT daughter boards 30 via an industrial bus. The system control motherboard 20 is used to receive and parse the test commands and test algorithm data sent by the host computer 10, distribute the test commands and test algorithm data to the multiple DUT daughter boards 30, and forward the test results generated by the DUT daughter boards 30 to the host computer 10. The DUT daughter board 30 includes a Zynq master control unit 300 and a non-volatile memory chip 301, and the Zynq master control unit 300 is connected to the non-volatile memory chip 301. The Zynq master control unit 300 is used to receive and parse the test commands, and use the test pattern algorithm corresponding to the test algorithm data. The algorithm completes the testing of the non-volatile memory chip 301, and acquires and analyzes the test data of the non-volatile memory chip 301 to generate and forward the test results to the system control motherboard 20.

[0026] Specifically, the non-volatile memory chip testing system of this application consists of a host computer 10, a system control motherboard 20, and multiple chip-under-test (UTC) daughterboards 30. In one embodiment, the network communication protocol includes the MODBUS-TCP protocol. The host computer 10 is the user interface, specifically a PC, and is connected to the MODBUS-TCP port on the system control motherboard 20 via its MODBUS-TCP port. The MODBUS-TCP port can transmit and receive data in real time, allowing the host computer 10 to send test commands and receive test results via the MODBUS-TCP protocol. The system control motherboard 20 is the task allocation center, responsible for parsing the test commands and test algorithm data sent by the host computer 10, distributing commands and data to each UTC daughterboard 30, and receiving return data from each UTC daughterboard 30. In one embodiment, the aforementioned industrial bus includes an EtherCAT bus and an RS485 bus. Specifically, the system control motherboard 20 is connected to each chip under test (DUT) daughterboard 30 via an EtherCAT transceiver 200. The EtherCAT protocol enables real-time data transmission and reception. The system control motherboard 20 is connected to each DUT daughterboard 30 via an RS485 transceiver 201. The RS485 protocol enables parameter and algorithm debugging during operation. The functions of the DUT daughterboard 30 include implementing test graphics algorithms, receiving data returned by the non-volatile memory chip 301, and analyzing the test results.

[0027] The above solution, by placing the Zynq main control unit 300 and the non-volatile memory chip 301 on the same chip under test (DUT) daughterboard 30, can achieve a high-speed transmission frequency of up to 200MHz. Under the same test pattern algorithm complexity, it can shorten the test time and improve the test efficiency. In addition, the system control motherboard 20 is connected to multiple DUT daughterboards 30 through EtherCAT transceiver 200 and RS485 transceiver 201 respectively. Thus, the system control motherboard 20 can distribute test instructions and test algorithm data to multiple DUT daughterboards 30, enabling multiple DUT daughterboards 30 to test the non-volatile memory chip 301 simultaneously, thereby improving the test efficiency.

[0028] Furthermore, the network communication protocol includes the MODBUS-TCP protocol, and the host computer 10 is also used to send low-level software upgrade commands to the system control motherboard 20. The industrial bus also includes a CAN bus. Specifically, the system control motherboard 20 is also connected to multiple chip-under-test (DUT) daughterboards 30 via CAN transceivers 202. The system control motherboard 20 is used to update the IP core programs of the multiple DUT daughterboards 30 according to the low-level software upgrade commands. Specifically, the system control motherboard 20 is connected to each DUT daughterboard 30 via CAN transceivers 202. The CAN protocol enables online upgrades and program downloads for the ZYNQ program. The host computer 10 can send low-level software upgrade commands via the MODBUS-TCP protocol, and the system control motherboard 20 updates the IP core programs of the multiple DUT daughterboards 30 according to the low-level software upgrade commands.

[0029] Please combine Figure 2 Specifically, the system control motherboard 20 includes a flash memory unit 203, a memory unit 204, and an SD card 205. The flash memory unit 203 stores the BOOT program and the FPGA program, the memory unit 204 stores the running program and cached data, and the SD card 205 stores device log information and is used for production debugging and BOOT program burning. The flash memory unit 203 can store the BOOT program and the FPGA program, the memory unit 204 (DDR3) stores the running program and cached data, and the SD card 205 stores device log information and is used for production debugging and BOOT program burning. It is understood that the system control motherboard 20 may also include a ZYNQ chip 206, which parses the test commands and test algorithm data sent by the host computer 10 and distributes the commands and data to each chip daughterboard 30 under test.

[0030] Please combine Figure 3In one embodiment, the Zynq master control unit 300 includes a processing system module 3001 and a programmable logic module 3002. The processing system module 3001 and the programmable logic module 3002 exchange data via an AXI bus. The processing system module 3001 is connected to the system control motherboard 20. The processing system module 3001 is used to receive and parse test instructions, use test pattern algorithms to test the non-volatile memory chip 301, and receive and analyze the test data of the non-volatile memory chip 301 returned by the programmable logic module 3002 to generate and forward the test results to the system control motherboard 20. The programmable logic module 3002 is connected to the non-volatile memory chip 301. The programmable logic module 3002 is used to complete the timing control of the non-volatile memory chip 301 and the high and low levels of the logic pins of the non-volatile memory chip 301 according to the read and write requests corresponding to the test pattern algorithms, thereby completing the read and write function test of the non-volatile memory chip 301.

[0031] Furthermore, the chip daughterboard 30 under test also includes a cache unit 302, which is connected to the Zynq main control unit 300. The cache unit 302 is used for large-capacity data caching.

[0032] The chip under test (DUT) daughterboard 30 mainly consists of three parts: a Zynq main control unit 300, a non-volatile memory chip 301, and a high-speed cache unit 302 (DDR3). Specifically, the Zynq main control unit 300 is a SoC platform developed by Xilinx, integrating an ARM core and FPGA logic, namely a processing system module 3001 (PS) and a programmable logic module 3002 (PL). The processing system module 3001 and the programmable logic module 3002 are connected via various buses, including AXI, enabling fast and efficient data exchange. The function of the processing system module 3001 is to parse the test commands sent by the host computer 10 and implement test graphics algorithms, such as using test graphics algorithms to perform full address read / write operations on the memory chip to detect faults. In addition, the processing system module 3001 can also receive data from the programmable logic module 3002 and analyze it to obtain test results. The memory chips in the high-speed cache unit 302 are used for large-capacity data caching. In one embodiment, the non-volatile memory chip 301 can specifically be a NAND Flash memory chip. The non-volatile memory chip 301 is connected to the pins of the corresponding programmable logic module 3002. Based on the read / write requests sent by the test system, the module controls the timing of the memory chip and the high / low levels of its logic pins, thereby completing the read / write function test of the non-volatile memory chip 301 under test. The programmable logic module 3002 adopts a modular design and mainly includes a NAND Flash controller. Its functions mainly include block erasure, page programming, page reading, read status, and timing control.

[0033] The non-volatile memory chip testing system of this application adopts a highly flexible testing scheme. For different non-volatile memory chips 301, the Zynq main control unit 300 can be flexibly configured with pins and NAND Flash controllers. Furthermore, IP core adaptation is possible. The Zynq main control unit 300 and the non-volatile memory chip 301 are located on the same chip-under-test (DUT) daughterboard 30, enabling high-speed transmission frequencies up to 200MHz. Under the same test pattern algorithm complexity, this shortens testing time and improves testing efficiency. EtherCAT / RS485 / CAN / MODBUS-TCP buses are all industrial-grade fieldbuses, offering reliable transmission, high real-time performance, long transmission distances, a large number of nodes, and strong anti-interference capabilities. Through industrial Ethernet fieldbus protocols such as EtherCAT / MODBUS-TCP, daisy-chain network topologies can be implemented. While Ethernet communication supporting TCP / IP typically exhibits uncertainty, with a response time usually around 100ms, industrial Ethernet protocols using a modified Media Access Control (MAC) layer can achieve very low latency and deterministic response.

[0034] This application also provides a method for testing non-volatile memory chips, which can be implemented using any of the aforementioned non-volatile memory chip testing systems. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a flowchart illustrating an embodiment of the non-volatile memory chip testing method of this application. In this embodiment, the non-volatile memory chip testing method is applied to a non-volatile memory chip testing system. The non-volatile memory chip testing system includes a host computer, a system control motherboard, and multiple chip-to-test (DUT) daughter boards. The host computer is connected to the system control motherboard via a network communication protocol. The system control motherboard is connected to the multiple DUT daughter boards via an industrial bus. Each DUT daughter board includes a Zynq main control unit and a non-volatile memory chip. The Zynq main control unit is connected to the non-volatile memory chip. Optionally, the non-volatile memory chip can be a NAND Flash memory chip. The non-volatile memory chip testing method in this embodiment includes the following steps:

[0035] S41: The host computer sends test commands and test algorithm data to the system control motherboard.

[0036] S42: The system control motherboard receives and parses the test instructions and test algorithm data sent by the host computer, and distributes the test instructions and test algorithm data to the multiple chip daughterboards under test.

[0037] S43: In each of the chip daughterboards under test, the Zynq main control unit receives and parses the test instructions, completes the test of the non-volatile memory chip through the test graph algorithm corresponding to the test algorithm data, acquires and analyzes the test data of the non-volatile memory chip, generates test results based on the test data, and forwards the test results to the system control motherboard.

[0038] S44: The system control motherboard receives and forwards the test results returned by the multiple chip sub-boards under test to the host computer.

[0039] S45: The host computer receives the test results returned by the system control motherboard and generates a test report.

[0040] Furthermore, the network communication protocol includes the MODBUS-TCP protocol, and the industrial bus includes the EtherCAT bus, RS485 bus, and CAN bus; the method further includes: the host computer sending a low-level software upgrade instruction to the system control motherboard; the system control motherboard updating the IP core program of the multiple chip daughterboards under test according to the low-level software upgrade instruction.

[0041] Specifically, the host computer can set test information such as current and voltage, as well as test pattern algorithms, to generate a test program. This test program can then be sent to the system control motherboard along with test instructions and test algorithm data. The system control motherboard can distribute the test instructions and test algorithm data to N chip daughterboards under test (DUTs). These N DUTs can then upgrade and update their IPR cores online. Within each DUT, the DUT can call the test pattern algorithm corresponding to the test algorithm data to complete the test of the non-volatile memory chip, acquiring and analyzing the test data. The system control motherboard can receive and summarize the test data and voltage alarm information returned by each DUT, and then upload the test results returned by each DUT to the host computer. The host computer can receive the test results uploaded by the system control motherboard and generate a test report.

[0042] Please combine Figure 5 , Figure 5 for Figure 4 A flowchart illustrating an embodiment of step S43 is provided. Further, the Zynq main control unit includes a processing system module and a programmable logic module. The processing system module and the programmable logic module exchange data via an AXI bus. The processing system module is connected to the system control motherboard, and the programmable logic module is connected to the non-volatile memory chip. Step S43 may specifically include:

[0043] S431: The processing system module receives and parses the test command, and uses the test graphics algorithm to test the non-volatile memory chip.

[0044] S432: The programmable logic module completes the timing control of the non-volatile memory chip and the high and low levels of the logic pins of the non-volatile memory chip according to the read and write requests corresponding to the test graphics algorithm.

[0045] S433: The processing system module receives and analyzes the test data of the non-volatile memory chip returned by the programmable logic module, so as to generate and forward the test results to the system control motherboard.

[0046] Please combine Figure 6 , Figure 6 This is a schematic diagram illustrating the process of testing the memory array of the non-volatile memory chip using the test pattern algorithm described in this application. In one embodiment, the steps of testing the non-volatile memory chip using the test pattern algorithm in the non-volatile memory chip testing method of this application may specifically include:

[0047] S61: Read the chip ID of the non-volatile memory chip and determine whether the chip ID matches the chip datasheet. If they match, proceed to step S62; otherwise, proceed to step S63.

[0048] S62: The memory array of the non-volatile memory chip is tested using the test graphics algorithm.

[0049] S63: Determine that the non-volatile memory chip is defective.

[0050] Please combine Figure 7 , Figure 7 for Figure 6 A flowchart illustrating step S62 in one embodiment. In one embodiment, step S62 may specifically include:

[0051] S621: Test the current storage block of the storage array. Write and read data from the current storage block according to the test graph algorithm, and determine whether the written and read data are the same. If they are the same, proceed to step S622; if they are different, proceed to step S623.

[0052] S622: Erase the data in the current storage block, determine that the current storage block has passed the test, and test the next storage block.

[0053] S623: Determine that the current storage block fails the test, and record the address information of the current storage block.

[0054] Please combine Figure 8 , Figure 8 This is a flowchart illustrating the process of testing a non-volatile memory chip array using a test pattern algorithm in an application scenario. During testing, the chip ID of the non-volatile memory chip is first read and compared with the chip's technical datasheet. If they do not match, the chip is considered unqualified, and the test stops; if they match, the test continues. Specifically, for example, starting the test on the Nth memory block of the array, data is written to and read from the Nth memory block according to the test pattern algorithm. The written and read data are compared; if they match, the data on the Nth memory block is erased, confirming that the Nth memory block has passed the test, and the next memory block is tested. If they do not match, the Nth memory block has failed the test, and its address information is recorded, i.e., the bad block address is recorded.

[0055] Understandably, during the test, all memory arrays of the non-volatile memory chip are written to, read from, and compared. If the read data is the same as the written data, it proves that the memory is functionally intact. The format of the written data depends on the selected test pattern algorithm. Different test pattern algorithms have different test fault coverage rates. In this application embodiment, the March algorithm can be used. The March algorithm has the advantages of high fault coverage and low time complexity. The test process includes reading, writing, and erasing the entire block. If data inconsistency is found, the test system records the bad block address.

[0056] The non-volatile memory chip testing system and method described in this application improve testing efficiency. By designing a complete control circuit around the non-volatile memory chip, its read / write logic functions are tested. Different test pattern algorithms are used to detect faults in the memory cells of the non-volatile memory chip, including functional failures caused by bad metal connections, faulty components, or chip logic errors. The control circuit utilizes the fully programmable chip Zynq to implement reliability testing of the non-volatile memory chip. Parsing test commands sent from the host computer and implementing test pattern algorithms run on the PS (ARM) side of the Zynq main control unit. The complex timing control of the non-volatile memory chip is designed using the PL (FPGA) side of the Zynq main control unit. The PS and PL sides use an AXI transmission channel to achieve high-speed data transmission between them.

[0057] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0058] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or principle transformations made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A non-volatile memory chip testing system, characterized in that, The non-volatile memory chip testing system includes a host computer, a system control motherboard, and multiple chip sub-boards under test; The host computer is connected to the system control motherboard via a network communication protocol; the host computer is used to send test commands and test algorithm data to the system control motherboard, receive test results forwarded by the system control motherboard, and generate test reports. The system control motherboard is connected to the multiple chip-under-test sub-boards via an industrial bus. The system control motherboard is used to receive and parse the test instructions and test algorithm data sent by the host computer, distribute the test instructions and test algorithm data to the multiple chip sub-boards under test, and forward the test results generated by the chip sub-boards under test to the host computer. The chip under test (DUT) includes a Zynq main control unit and a non-volatile memory chip. The Zynq main control unit is connected to the non-volatile memory chip. The Zynq main control unit is used to receive and parse the test instructions, complete the test of the non-volatile memory chip through the test graph algorithm corresponding to the test algorithm data, and acquire and analyze the test data of the non-volatile memory chip to generate and forward the test results to the system control motherboard.

2. The non-volatile memory chip testing system according to claim 1, characterized in that, The network communication protocol includes the MODBUS-TCP protocol, and the host computer is also used to send low-level software upgrade instructions to the system control motherboard. The industrial bus includes EtherCAT bus, RS485 bus and CAN bus. The system control motherboard is used to update the IP core program of the multiple chip daughterboards under test according to the underlying software upgrade instructions.

3. The non-volatile memory chip testing system according to claim 1, characterized in that, The system control motherboard includes a flash memory unit, a memory unit, and an SD card. The flash memory unit is used to store the BOOT program and the FPGA program. The memory unit is used to store the running program and cached data. The SD card is used to store device log information and to burn the BOOT program for production debugging. And / or, the chip under test sub-board further includes a cache unit, which is connected to the Zynq main control unit and is used for large-capacity data caching.

4. The non-volatile memory chip testing system according to claim 1, characterized in that, The Zynq main control unit includes a processing system module and a programmable logic module, and the processing system module and the programmable logic module exchange data via an AXI bus. The processing system module is connected to the system control motherboard. The processing system module is used to receive and parse the test instructions, use the test graphics algorithm to test the non-volatile memory chip, and receive and analyze the test data of the non-volatile memory chip returned by the programmable logic module, so as to generate and forward the test results to the system control motherboard. The programmable logic module is connected to the non-volatile memory chip. The programmable logic module is used to complete the timing control of the non-volatile memory chip and the high and low levels of the logic pins of the non-volatile memory chip according to the read and write requests corresponding to the test graphics algorithm, thereby completing the read and write function test of the non-volatile memory chip.

5. The non-volatile memory chip testing system according to claim 1, characterized in that, The non-volatile memory chip is a NAND Flash memory chip.

6. A testing method for non-volatile memory chips, characterized in that, The non-volatile memory chip testing method is applied to a non-volatile memory chip testing system, which includes a host computer, a system control motherboard, and multiple chip-to-test (DUT) daughter boards. The host computer is connected to the system control motherboard via a network communication protocol, and the system control motherboard is connected to the multiple DUT daughter boards via an industrial bus. Each DUT daughter board includes a Zynq main control unit and a non-volatile memory chip, and the Zynq main control unit is connected to the non-volatile memory chip. The non-volatile memory chip testing method includes: The host computer sends test commands and test algorithm data to the system control motherboard; The system control motherboard receives and parses the test instructions and test algorithm data sent by the host computer, and distributes the test instructions and test algorithm data to the multiple chip daughterboards under test; In each of the chip daughterboards under test, the Zynq main control unit receives and parses the test instructions, completes the test of the non-volatile memory chip through the test graph algorithm corresponding to the test algorithm data, acquires and analyzes the test data of the non-volatile memory chip, generates test results based on the test data, and forwards the test results to the system control motherboard. The system control motherboard receives and forwards the test results returned by the multiple chip sub-boards under test to the host computer; The host computer receives the test results returned by the system control motherboard and generates a test report.

7. The non-volatile memory chip testing method according to claim 6, characterized in that, The network communication protocol includes the MODBUS-TCP protocol, and the industrial bus includes the EtherCAT bus, RS485 bus, and CAN bus; the method further includes: The host computer sends a low-level software upgrade command to the system control motherboard; The system control motherboard updates the IP core programs of the multiple chip daughterboards under test according to the underlying software upgrade instructions.

8. The non-volatile memory chip testing method according to claim 6, characterized in that, The Zynq main control unit includes a processing system module and a programmable logic module. The processing system module and the programmable logic module exchange data via an AXI bus. The processing system module is connected to the system control motherboard, and the programmable logic module is connected to the non-volatile memory chip. The Zynq main control unit receives and parses the test command, completes the test of the non-volatile memory chip using the test graph algorithm corresponding to the test algorithm data, acquires and analyzes the test data of the non-volatile memory chip, generates test results based on the test data, and forwards the test results to the system control motherboard. The specific steps include: The processing system module receives and parses the test command, and uses the test graphics algorithm to test the non-volatile memory chip; The programmable logic module completes the timing control of the non-volatile memory chip and the high and low levels of the logic pins of the non-volatile memory chip according to the read and write requests corresponding to the test graphics algorithm. The processing system module receives and analyzes the test data of the non-volatile memory chip returned by the programmable logic module, so as to generate and forward the test results to the system control motherboard.

9. The non-volatile memory chip testing method according to claim 8, characterized in that, The step of testing the non-volatile memory chip using the test graphics algorithm includes: Read the chip ID of the non-volatile memory chip and determine whether the chip ID is consistent with the chip technical datasheet; If they match, the memory array of the non-volatile memory chip is tested using the aforementioned test graphics algorithm. If there is a discrepancy, the non-volatile memory chip is determined to be defective.

10. The non-volatile memory chip testing method according to claim 9, characterized in that, The step of testing the memory array of the non-volatile memory chip using the test graphics algorithm includes: The current storage block of the storage array is tested, and data is written and read from the current storage block according to the test graph algorithm. It is then determined whether the written data and the read data are the same. If they are the same, the data in the current storage block is erased to determine that the current storage block has passed the test, and the next storage block is then tested. If they are different, the current storage block is determined to be unqualified, and the address information of the current storage block is recorded.

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