Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate; forming a protection layer on a first region of the substrate; and forming a gate oxide layer on a second region of the substrate, wherein the protection layer is oxidized into an oxide layer during the formation of the gate oxide layer. In the present disclosure, the protection layer capable of reacting with oxygen and generating an oxide layer is formed on the substrate, so that the protection layer can absorb oxygen by chemical reaction to reduce the oxygen content during the gate oxidation process, and the protection layer after absorbing oxygen forms an oxide layer which can also physically block oxygen to achieve sufficient protection of the substrate. Moreover, the process of removing the oxide layer is compatible with conventional technology and does not affect subsequent processes.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In some process technologies, the substrate and some material layers disposed on the substrate are formed before the gate oxidation process. The substrate and these material layers are very sensitive to oxygen. If these structures are not protected or are not properly protected during the gate oxidation process, they are very likely to be oxidized, which will affect the performance of the semiconductor device.

[0003] In conventional approaches, a double oxide layer is typically formed to block oxygen diffusion and protect the substrate and other structures. However, the double oxide layer has limited effectiveness in blocking oxygen, and there is still a risk that the substrate and other structures may be oxidized. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] According to a first aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0006] Provide a base;

[0007] A protective layer is formed in a first region of the substrate;

[0008] A gate oxide layer is formed in a second region of the substrate, and during the formation of the gate oxide layer, the protective layer is oxidized into an oxide layer.

[0009] In one embodiment, a protective layer is formed in a first region of the substrate, comprising:

[0010] A first material layer and a second material layer are sequentially formed on the top surface of the substrate, wherein the first material layer covers the top surface of the substrate and the second material layer covers the top surface of the first material layer.

[0011] The first material layer and the second material layer covering the second region of the substrate are removed, and the first material layer and the second material layer remaining in the first region of the substrate form the protective layer;

[0012] The protective layer being oxidized into an oxide layer includes: at least the second material layer being oxidized into an oxide layer.

[0013] In one embodiment, removing the first material layer and the second material layer covering the second region of the substrate includes:

[0014] A first photoresist layer is formed, which covers the top surface of the second material layer located in a first region of the substrate;

[0015] Using the first photoresist layer as a mask, a portion of the first material layer and a portion of the second material layer in the second region are removed.

[0016] In one embodiment, the material of the first material layer includes an oxide.

[0017] In one embodiment, the material of the second material layer comprises polycrystalline silicon, and the material of the oxide layer comprises SiO2; or

[0018] The material of the second material layer includes nitrides, and the material of the oxide layer includes SiO2 and / or Si2N2O.

[0019] In one embodiment, when the gate oxide layer is formed in the second region of the substrate, the process temperature is 1073K to 1373K.

[0020] In one embodiment, the second region includes a first sub-region and a second sub-region, and the gate oxide layer includes a first gate oxide layer and a second gate oxide layer.

[0021] A gate oxide layer is formed in a second region of the substrate, including:

[0022] Remove the protective layer located in the first sub-region;

[0023] A first gate oxide layer is formed in the first sub-region. During the formation of the first gate oxide layer, the protective layer located in the first region and the second sub-region is oxidized into an oxide layer.

[0024] Remove the oxide layer located in the second sub-region to expose the top surface of the second sub-region of the substrate;

[0025] A second gate oxide layer is formed, which covers the top surface of a second sub-region of the substrate;

[0026] A high-k dielectric layer is formed on the top surface of the first gate oxide layer and the second gate oxide layer, and the high-k dielectric layer also covers the top surface of the oxide layer in the first region;

[0027] Remove the oxide layer and the high-k dielectric layer from the first region.

[0028] In one embodiment, removing the oxide layer located in the second sub-region includes:

[0029] A second photoresist layer is formed, which covers the top surface of the first gate oxide layer and the top surface of the oxide layer in the first region, and the oxide layer covering the second sub-region is exposed;

[0030] Using the second photoresist layer as a mask, the oxide layer covering the second sub-region is removed, exposing the top surface of the second sub-region of the substrate.

[0031] In one embodiment, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer in a direction perpendicular to the upper surface of the substrate.

[0032] The provision of the substrate also includes:

[0033] A channel material layer is formed on the region in the second sub-region used to form a P-type transistor.

[0034] In one embodiment, a substrate is provided, comprising:

[0035] Provide substrate;

[0036] An active storage region and an embedded word line penetrating the active storage region are formed in a first region of the substrate;

[0037] A peripheral active region is formed in the second region of the substrate.

[0038] According to a second aspect of this disclosure, a semiconductor structure is provided, comprising:

[0039] The substrate includes a first region and a second region;

[0040] An oxide layer covers the top surface of the first region of the substrate;

[0041] A gate oxide layer covers the top surface of the second region of the substrate.

[0042] In one embodiment, the material of the oxide layer includes at least one of SiO2 and Si2N2O.

[0043] In one embodiment, the second region includes a first sub-region and a second sub-region; the semiconductor structure further includes:

[0044] An input / output transistor located in the first sub-region, the input / output transistor including a first gate oxide layer covering the top surface of the first sub-region of the substrate;

[0045] A core transistor located in the second sub-region, the core transistor including a second gate oxide layer covering the top surface of the second sub-region of the substrate;

[0046] In a direction perpendicular to the upper surface of the substrate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0047] In one embodiment, the core transistor further includes a channel material layer located between a second sub-region of a second region of the substrate and the second gate oxide layer.

[0048] In one embodiment, the first region of the substrate includes an active storage region and an embedded word line penetrating the active storage region;

[0049] The second region of the substrate includes the peripheral active region.

[0050] In the semiconductor structure fabrication method and semiconductor structure disclosed herein, a protective layer capable of reacting with oxygen to form an oxide layer is formed on the substrate. During the gate oxidation process, the protective layer can absorb oxygen through a chemical reaction to reduce the oxygen content. Furthermore, the oxide layer formed by the oxygen-absorbing protective layer can also physically block oxygen, thus fully protecting the substrate. Moreover, the process for removing the oxide layer is compatible with conventional technologies and will not affect subsequent processes.

[0051] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0053] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0054] Figure 2 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0055] Figure 3 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0056] Figure 4 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0057] Figure 5 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0058] Figure 6 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0059] Figure 7 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0060] Figure 8 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0061] Figure 9 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0062] Figure 10 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0063] Figure label:

[0064] 100. Base;

[0065] 110. First region; 120. Second region; 121. First sub-region; 122. Second sub-region;

[0066] 111. Word line; 112. Isolation structure; 113. Dielectric layer;

[0067] 200. Protective layer; 210. First material layer; 220. Second material layer;

[0068] 300, Gate oxide layer; 310, First gate oxide layer; 320, Second gate oxide layer;

[0069] 400, oxide layer;

[0070] 500. Channel material layer;

[0071] 600, First photoresist layer; 700, Second photoresist layer;

[0072] 800, high-K dielectric layer. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0074] In some process technologies, the substrate and some material layers disposed on the substrate, such as SiGe, are formed before the gate oxidation process. The substrate and these material layers are very sensitive to oxygen. If these structures are not protected or are not properly protected during the gate oxidation process, they are very likely to be oxidized, which will affect the performance of the semiconductor device.

[0075] A double oxide layer is formed to block oxygen diffusion and protect the substrate and other structures. However, the double oxide layer has limited effect in blocking oxygen, and there is still a risk that the substrate and other structures will be oxidized.

[0076] To address the problem that current protective layers cannot effectively protect the substrate during gate oxidation processes, this disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes: providing a substrate; forming a protective layer in a first region of the substrate; and forming a gate oxide layer in a second region of the substrate. During the formation of the gate oxide layer, the protective layer is oxidized into an oxide layer. In this disclosure, by forming a protective layer on the substrate that can react with oxygen to form an oxide layer, the protective layer can absorb oxygen through a chemical reaction during the gate oxidation process, reducing the oxygen content. Furthermore, the oxide layer formed after oxygen absorption can physically block oxygen, achieving sufficient protection of the substrate. The process for removing the oxide layer is compatible with conventional techniques and will not affect subsequent processes.

[0077] This disclosure does not limit the semiconductor structure. The following description uses Dynamic Random Access Memory (DRAM) as an example, but this embodiment is not limited to this; other semiconductor structures are also possible. Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 2 to 10 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 2 to 10 The methods for fabricating semiconductor structures are introduced.

[0078] According to an exemplary embodiment of this disclosure, such as Figure 1 As shown in the figure, this disclosure provides a method for fabricating a semiconductor structure, the method including the following steps:

[0079] Step S100: Provide a substrate.

[0080] In this step, such as Figure 2 As shown, the substrate 100 includes a substrate and components disposed on the substrate, such as transistors and capacitors.

[0081] The substrate is used to support the components disposed on it. The substrate material can be silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide and other group III-V compounds.

[0082] Step S200: Form a protective layer in the first region of the substrate.

[0083] In this step, such as Figure 2 As shown, a protective layer 200 can be formed on the top surface of the first region 110 of the substrate 100 by means of physical vapor deposition, chemical vapor deposition, atomic layer deposition or epitaxial growth.

[0084] In one embodiment, forming a protective layer 200 in a first region 110 of the substrate 100 may specifically include the following steps:

[0085] Step S210: A first material layer and a second material layer are sequentially formed on the top surface of the substrate. The first material layer and the second material layer cover the top surface of the substrate, and the second material layer covers the top surface of the first material layer.

[0086] In this step, such as Figure 2 As shown, firstly, a first material layer 210 can be formed on the entire top surface of the substrate 100 (including the first region 110 and the second region 120) using processes such as deposition and epitaxial growth. The material of the first material layer 210 is an oxide, which can be a metal oxide or a non-metal oxide, such as silicon dioxide (SiO2). Next, a second material layer 220 can be formed on the top surface of the first material layer 210 using processes such as deposition and epitaxial growth. The material of the second material layer 220 can be polysilicon (Poly Si) or nitride. Polysilicon and nitride can react with oxygen to absorb oxygen during the gate oxidation process, thereby improving the oxygen barrier capability of the protective layer.

[0087] In some embodiments, the nitride includes silicon nitride, such as Si3N4.

[0088] In some embodiments, the thickness of the second material layer is less than the thickness of the first material layer, so that the first material layer 210 can ensure that the substrate and other structures are isolated from oxygen in the environment, and the second material layer 220 can be completely oxidized into an oxide layer during the formation of the gate oxide layer and block the diffusion of oxygen in the protective layer, thereby improving the efficiency of subsequent oxide layer removal.

[0089] In order to improve the structural reliability of the first material layer and the second material layer, the top surface of the substrate can be chemically mechanically polished before the first material layer is formed, and the top surface of the first material layer can be chemically mechanically polished before the second material layer is formed.

[0090] Step S220: Remove the first material layer and the second material layer covering the second region of the substrate, and the remaining first material layer and the second material layer in the first region of the substrate form a protective layer.

[0091] In this step, refer to Figure 2 and Figure 8 The first material layer 210 and the second material layer 220 covering the second region 120 of the substrate 100 can be removed by photolithography and etching processes, exposing the top surface of the second region 120 of the substrate 100, thereby forming the gate oxide layer 300 on the second region 120 of the substrate 100 (see reference). Figure 8 The first material layer 210 and the second material layer 220, which are retained on the top surface of the first region 110, form a protective layer 200.

[0092] It should be noted that when removing the first material layer 210 and the second material layer 220 covering the top surface of the second region 120, all the first material layer 210 and the second material layer 220 on the second region 120 can be removed at once.

[0093] Alternatively, a portion of the first material layer 210 and a portion of the second material layer 220 on the second region 120 can be removed firstly. After completing the specified process at the locations where the first material layer 210 and the second material layer 220 have been removed, another portion of the first material layer 210 and the second material layer 220 on the second region 120 can be removed. This allows for the formation of gate oxide layers of varying thicknesses on the second region of the substrate in subsequent gate oxide processes, based on the performance requirements of different locations within the semiconductor device. This results in optimal performance for the semiconductor device. For example, a thinner gate oxide layer can be formed in the core region, enabling faster response times, while a thicker gate oxide layer can be formed in the input / output (I / O) regions to meet the high voltage requirements of the I / O regions and prevent tunneling leakage current.

[0094] In this step, the present disclosure provides an example of a scheme in which a protective layer is formed by a first material layer and a second material layer. This does not limit the technical solution of the present disclosure. The protective layer may also be a stacked structure of three, four or more layers.

[0095] In some embodiments, a protective layer consisting of alternating stacked first and second material layers is formed on the top surface of the substrate. For example, the protective layer may include at least two first material layers and at least one second material layer.

[0096] Step S300: A gate oxide layer is formed in the second region of the substrate. During the formation of the gate oxide layer, the protective layer is oxidized into an oxide layer.

[0097] In this step, refer to Figure 4 and Figure 5 ,as well as Figure 7 and Figure 8 A gate oxide layer 300 can be formed in the second region 120 of the substrate 100 using processes such as thermal oxidation. The material of the gate oxide layer 300 can be, for example, silicon dioxide (SiO2). During the formation of the gate oxide layer 300, the protective layer 200 can be oxidized into an oxide layer 400. When the protective layer 200 is a double-layer structure composed of a first material layer 210 and a second material layer 220, the upper second material layer 220 is oxidized to form the oxide layer 400.

[0098] Taking the material of the second material layer 200 as Si3N4 as an example, the chemical reaction formula for the second material layer 220 to react with oxygen to form the oxide layer 400 includes:

[0099] Si3N4(s)+3 / 2O2(g)→3SiO(g)+2N2(g);

[0100] Si3N4(s)+3O2(g)→3SiO2(s)+2N2(g);

[0101] Si3N4(s)+5O2(g)→3SiO2(s)+4NO(g);

[0102] 4Si3N4(s)+3O2(g)→6Si2N2O(s)+2N2(g).

[0103] Wherein, (s) indicates that the substance is a solid, and (g) indicates that the substance is a gas.

[0104] When the process temperature is between 1073K and 1373K, Si3N4 can be oxidized to oxides. In a practical scenario, each consumption... Si3N4 can generate Oxide. In some embodiments, the thickness of the second material layer 200 is 0.44-1.5 times the thickness of the gate oxide layer 300, which can be formed in one step or in stages.

[0105] As can be seen from the above, during the gate oxidation process, the protective layer 200 can react chemically with oxygen to reduce the oxygen content, and the protective layer 200 after absorbing oxygen can be oxidized to form an oxide layer 400. The oxide layer 400 has a physical barrier effect on oxygen. Compared with conventional solutions, the protective layer 200 in this disclosure solution can effectively block oxygen through chemical and physical means.

[0106] In this embodiment, a protective layer capable of reacting with oxygen and generating an oxide layer is formed on the substrate. Thus, during the gate oxidation process, the protective layer can first absorb oxygen through a chemical reaction to reduce the oxygen content. The oxide layer formed after the protective layer is oxidized can then physically block oxygen, thereby effectively preventing the substrate from being oxidized. Furthermore, the process for removing the oxide layer is compatible with conventional technologies and will not affect subsequent processes.

[0107] In an exemplary embodiment, this embodiment is a further explanation of step S220 in the above embodiment. Step S220 may specifically include the following steps:

[0108] Step S221: Form a first photoresist layer, which covers the top surface of the second material layer located in the first region of the substrate.

[0109] In this step, such as Figure 2 and Figure 3 As shown, photoresist can be either positive or negative. Taking a positive photoresist layer as an example, firstly, a photoresist layer can be formed on the substrate, and then a layer can be formed on top of the substrate. Figure 2 A photomask (not shown) is set in the z direction shown. The photomask at least covers the first region 110 of the substrate 100. Then, the photoresist layer not covered by the photomask can be removed by exposure. The remaining photoresist layer forms the first photoresist layer 600.

[0110] Step S222: Using the first photoresist layer as a mask, remove part of the first material layer and the second material layer in the second region.

[0111] In this step, such as Figure 3 and Figure 4 As shown, the first photoresist layer 600 can be used as a mask, and an etching process can be used to remove the first material layer 210 and the second material layer 220 that are not covered by the first photoresist layer 600, so as to expose at least part of the top surface of the second region 120 of the substrate 100.

[0112] In one embodiment, such as Figure 4As shown, a portion of the first material layer 210 and the second material layer 220 covering the second region 120 of the substrate 100 can be removed. For example, the second region 120 of the substrate 100 includes a first sub-region 121 and a second sub-region 122, and the gate oxide layer 300 formed in the subsequent process includes a first gate oxide layer 310 and a second gate oxide layer 320. The first gate oxide layer 310 is located on the first sub-region 121, and the second gate oxide layer 320 is located on the second sub-region 122. The first sub-region 121 is, for example, the input / output region (I / O) of the peripheral circuit, and the second sub-region 122 is, for example, the core region (Core) of the peripheral circuit. Since the operating voltages of the input / output region and the core region are different, the gate oxide layer 300 of different thicknesses can be set for the input / output region and the core region of the peripheral circuit so that both the input / output region and the core region have optimal performance.

[0113] In one embodiment, step S300 may specifically include the following steps:

[0114] Step S310: Remove the protective layer located in the first sub-region.

[0115] In this step, such as Figure 3 and Figure 4 As shown, the protective layer located in the first sub-region 121 can be removed by photolithography and etching processes to expose the top surface of the first sub-region 121 of the substrate 100.

[0116] Step S320: A first gate oxide layer is formed in the first sub-region. During the formation of the first gate oxide layer, the protective layer located in the first region and the second sub-region is oxidized into an oxide layer.

[0117] In this step, such as Figure 5 As shown, a first gate oxide layer 310 is formed on the first sub-region 121 using a gate oxide process. Since the operating voltage at the input / output region (I / O) is relatively high, a thicker first gate oxide layer 310 can be formed on the first sub-region 121 to avoid poor blocking effect on electrons when the gate oxide layer is too thin, which would lead to tunneling leakage current.

[0118] It should be noted that, referring to Figure 4 and Figure 5 The gate oxidation process is applied to the entire top surface of the substrate 100. During the gate oxidation process, a first gate oxide layer 310 can be formed on the first sub-region 121 of the substrate 100. The second material layer 220 covering the first region 110 and the second sub-region 122 of the substrate 100 can be oxidized. The second material layer 220 reacts chemically with oxygen to reduce the oxygen content. The second material layer 220 can be oxidized to form an oxide layer 400.

[0119] Taking polycrystalline silicon as an example, the material of the second material layer 220 is polycrystalline silicon, and the material of the oxide layer 400 formed by oxidation includes SiO2.

[0120] Taking the material of the second material layer 220 as Si3N4 as an example, the material of the oxide layer 400 formed by oxidation includes any one or more of SiO2 and Si2N2O.

[0121] Step S330: Remove the oxide layer located in the second sub-region to expose the top surface of the second sub-region of the substrate.

[0122] In this step, such as Figure 6 and Figure 7 As shown, the first material layer 210 and oxide layer 400 covering the second sub-region 122 can be removed using photolithography and etching processes, exposing the top surface of the second sub-region 122 of the substrate 100, thereby enabling the formation of the second gate oxide layer 320 on the top surface of the second sub-region 122 (see reference). Figure 8 ).

[0123] In one example, step S330 may specifically include the following steps:

[0124] Step S331: Form a second photoresist layer. The second photoresist layer covers the top surface of the first gate oxide layer and the top surface of the oxide layer in the first region, and exposes the oxide layer covering the second sub-region.

[0125] In this step, such as Figure 6 As shown, a second photoresist layer 700 can be formed on the top surface of the first region 110 and the first sub-region 121 of the substrate 100, while the top surface of the oxide layer 400 covering the second sub-region 122 of the substrate 100 is exposed. The method of forming the second photoresist layer can be the same as the method of forming the first photoresist layer 600 in step S221, and will not be described again here.

[0126] Step S332: Using the second photoresist layer as a mask, remove the oxide layer covering the second sub-region to expose the top surface of the second sub-region of the substrate.

[0127] In this step, such as Figure 6 and Figure 7 As shown, the implementation method of step S332 is the same as that of step S222, and will not be described again here.

[0128] Step S340: Form a second gate oxide layer, which covers the top surface of the second sub-region of the substrate.

[0129] In this step, such as Figure 8As shown, a second gate oxide layer 320 can be formed on the top surface of the second sub-region 122 of the substrate 100 using a gate oxide process. The second sub-region 122 of the substrate 100 can be a core region. The operating voltage of the core region is lower, forming a thinner gate oxide layer, which enables the semiconductor device to have a faster response speed.

[0130] In some embodiments, during the formation of the first gate oxide layer 310, a portion of the second material layer 220 in the protective layer is oxidized into an oxide layer 400, and during the formation of the second gate oxide layer 320, all remaining second material layers 220 in the protective layer are oxidized into an oxide layer 400.

[0131] Step S350: A high-k dielectric layer is formed on the top surface of the first gate oxide layer and the second gate oxide layer, and the high-k dielectric layer also covers the top surface of the oxide layer in the first region.

[0132] In this step, such as Figure 9 As shown, a high-K dielectric layer 800 can be formed on the top surface of a semiconductor device through a deposition process. That is, the high-K dielectric layer 800 can cover the top surface of the first gate oxide layer 310, the second gate oxide layer 320, and the oxide layer 400 covering the first region 110.

[0133] It should be noted that the process for forming a high-k dielectric layer, such as the HKMG process, where HK stands for High-K (high dielectric constant) and MG stands for Metal Gate, involves using a high-k dielectric material to replace or layer the gate oxide layer made of oxide materials in conventional techniques, and using a metal gate instead of a polysilicon gate. The high-k dielectric layer can increase the gate oxide thickness, avoid tunneling leakage current, and improve the performance of semiconductor devices. Materials for the high-k dielectric layer include, but are not limited to, hafnium oxide, aluminum oxide, lanthanum oxide, or tannin oxide.

[0134] Step S360: Remove the oxide layer and high-k dielectric layer in the first region.

[0135] In this step, such as Figure 10 As shown, the oxide layer 400 and the high-K dielectric layer 800 located in the first region 110 can be removed by photolithography, etching and other processes to expose the top surface of the first region 110 of the substrate 100.

[0136] It is understandable that since the first region of the substrate (the active storage region) can use buried word lines, there is no need to perform a gate oxidation process in the first region. Therefore, after the gate oxidation process is completed in the second region of the substrate, the oxide layer and high-k dielectric layer in the first region can be removed.

[0137] In some embodiments, a dielectric layer 113 is formed in the first region of the substrate before the protective layer 200 is formed, the dielectric layer 113 being used to further protect the substrate of the first region 110.

[0138] In an exemplary embodiment, this embodiment is a further explanation of step S100 in the above embodiments, and providing the substrate may specifically include the following steps:

[0139] Step S110: Provide a substrate.

[0140] Step S120: Form a storage active region and an embedded word line through the storage active region in a first region of the substrate.

[0141] In this step, refer to Figure 2 For example, P-well regions, N-well regions, and shallow trench isolation (STI) structures 112 are formed in a first region of the substrate (referring to the first region 110 of the substrate 100) by ion implantation, as well as buried word lines 111 recessed into the substrate. The buried word lines 111 can be along... Figure 2 The y-direction shown in the diagram runs through the active region of the memory and can be used to form an active region for a 1T1C (i.e., each basic memory cell includes only one transistor and one capacitor) memory array.

[0142] Step S130: Form a peripheral active region in the second region of the substrate.

[0143] In this step, refer to Figure 2 P-well regions and N-well regions can be formed in the second region of the substrate (refer to the second region 120 of the substrate 100) by means of ion implantation, and then P-type transistors and N-type transistors can be formed.

[0144] According to an exemplary embodiment of this disclosure, such as Figures 2 to 8 As shown, this disclosure provides a semiconductor structure, which includes a substrate 100, a gate oxide layer 300, and a protective layer 200.

[0145] In this embodiment, as Figure 8 As shown, the substrate 100 includes a first region 110 and a second region 120. (Refer to...) Figure 8 The first region 110 of the substrate 100 is, for example, the active storage region of a semiconductor device. The active storage region is also called the array region. The active storage region includes multiple storage cells arranged in an array. Each storage cell includes transistors, capacitors, etc. Multiple transistors and capacitors are connected by word lines and bit lines arranged in a cross shape. Thus, any storage cell can be selected by word lines and bit lines to read and write data in that storage cell. The principle of word lines and bit lines will not be elaborated on here.

[0146] Reference Figure 8 The second region 120 of the substrate 100 is, for example, the peripheral active region of a semiconductor device, also known as the peripheral circuit region. The peripheral active region contains N-type transistors (NMOS, Negative channel Metal-Oxide-Semiconductor), P-type transistors (PMOS, Positive channel Metal-Oxide-Semiconductor), capacitors, etc. The first sub-region 121 of the second region 120 is the input / output region (I / O), and the second sub-region 122 is the core region.

[0147] In this embodiment, as Figure 8 As shown, the oxide layer 400 covers the top surface of the first region 110 of the substrate 100. As can be seen from the foregoing embodiments, the oxide layer 400 is formed by oxidizing the protective layer 200 during the gate oxidation process. When the protective layer 200 includes a first material layer 210 and a second material layer 220 stacked vertically, the oxide layer 400 may be formed by oxidizing the upper second material layer 220.

[0148] In this embodiment, as Figure 8 As shown, the gate oxide layer 300 covers the top surface of the second region 120 of the substrate 100, and the material forming the gate oxide layer includes silicon dioxide, etc. The thickness of the gate oxide layer can be different. For example, a thinner second gate oxide layer 320 can be provided in the second sub-region 122 (core region) of the second region 120 of the substrate 100, and a thicker first gate oxide layer 310 can be provided in the first sub-region 121 (input / output region) of the second region 120.

[0149] In this embodiment, a protective layer covers a first region of the substrate, and the protective layer can react with oxygen to generate an oxide layer. During the gate oxidation process, the protective layer can absorb oxygen through a chemical reaction to reduce the oxygen content, and the oxide layer formed after absorbing oxygen then physically blocks oxygen to fully protect the substrate. Furthermore, the process for removing the oxide layer is compatible with conventional technology and will not affect subsequent processes.

[0150] In one embodiment, such as Figure 8 As shown, an input / output transistor is disposed in the first sub-region 121, and the input / output transistor includes a first gate oxide layer 310 covering the first sub-region 121 of the substrate 100. A core transistor is disposed in the second sub-region 122, and the core transistor includes a second gate oxide layer 320 covering the second sub-region 122 of the substrate 100. The thickness of the first gate oxide layer 310 is ( Figure 2The z-direction shown (i.e., the direction perpendicular to the upper surface of the substrate) is greater than the second gate oxide layer 320, as described in the previous embodiments, and will not be repeated here.

[0151] Among them, such as Figure 8 As shown, the core transistor also includes a channel material layer 500, which is located between the second sub-region 122 of the second region of the substrate 100 and the second gate oxide layer 320. For example, a portion of the channel material layer 500 is located on the P-type transistor in the second sub-region 122. The material of the channel material layer 500 can be any one or more of silicon germanide and silicon carbide. The channel material layer 500 has a different lattice constant from the substrate, which can generate stress to improve the electron-hole mobility in the channel region of the P-type transistor.

[0152] In one embodiment, such as Figure 2 As shown, the substrate 100 includes a P-well region, an N-well region, and a shallow trench isolation (STI) structure 112, as well as a buried word line (BWZ) recessed into the substrate. The buried word line 111 can extend along... Figure 2 The y-direction shown in the diagram runs through the active region of the memory and can be used to form an active region for a 1T1C (i.e., each basic memory cell includes only one transistor and one capacitor) memory array.

[0153] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0154] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0155] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0156] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0157] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The application provides a method for manufacturing a semiconductor device, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: providing a substrate; forming a protective layer on a first region and a second region of the substrate, the second region comprising a first sub-region and a second sub-region, and a channel material layer being formed on a region of the second sub-region for forming a P-type transistor; forming a gate oxide layer on the second region of the substrate, the gate oxide layer comprising a first gate oxide layer and a second gate oxide layer; forming a gate oxide layer on the second region of the substrate, comprising: removing the protective layer on the first sub-region; forming a first gate oxide layer on the first sub-region, and in the process of forming the first gate oxide layer, the protective layer on the first region and the second sub-region is oxidized into an oxide layer; removing the oxide layer on the second sub-region to expose the top surface of the second sub-region of the substrate; forming a second gate oxide layer, the second gate oxide layer covering the top surface of the second sub-region of the substrate, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer in the direction perpendicular to the upper surface of the substrate; forming a high-K dielectric layer on the top surface of the first gate oxide layer and the second gate oxide layer, and the high-K dielectric layer also covers the top surface of the oxide layer of the first region; 2. The method of fabricating a semiconductor structure of claim 1, wherein, removing the oxide layer of the first region and the high-K dielectric layer. The method for forming a protective layer on a first region of a substrate comprises: sequentially forming a first material layer and a second material layer on the top surface of the substrate, the first material layer covering the top surface of the substrate, and the second material layer covering the top surface of the first material layer; removing the first material layer and the second material layer covering the second region of the substrate, and the first material layer and the second material layer remaining on the first region of the substrate form the protective layer; 3. The method of fabricating a semiconductor structure of claim 2, wherein, oxidizing the protective layer into an oxide layer comprises: at least the second material layer is oxidized into an oxide layer. The method for removing the first material layer and the second material layer covering the second region of the substrate comprises: forming a first photoresist layer, the first photoresist layer covering the top surface of the second material layer on the first region of the substrate; 4. The method of fabricating a semiconductor structure of claim 2, wherein, removing part of the first material layer and part of the second material layer on the second region by taking the first photoresist layer as a mask.

5. The method of fabricating a semiconductor structure of claim 2, wherein, The material of the first material layer comprises an oxide. The material of the second material layer comprises polysilicon, and the material of the oxide layer comprises SiO2; or 6. The method of fabricating a semiconductor structure of claim 1, wherein, The material of the second material layer comprises a nitride, and the material of the oxide layer comprises SiO2 and / or Si2N2O.

7. The method of fabricating a semiconductor structure of claim 1, wherein, When the gate oxide layer is formed on the second region of the substrate, the process temperature is 1073K-1373K. The method for removing the oxide layer on the second sub-region comprises: forming a second photoresist layer, the second photoresist layer covering the top surface of the first gate oxide layer and the top surface of the oxide layer of the first region, and the oxide layer on the second sub-region is exposed; 8. The method of fabricating a semiconductor structure of claim 1, wherein, removing the oxide layer on the second sub-region by taking the second photoresist layer as a mask to expose the top surface of the second sub-region of the substrate. The method for providing a substrate comprises: providing a substrate; forming a storage active region and a buried word line penetrating the storage active region in a first region of the substrate; forming a peripheral active region in a second region of the substrate.

9. A semiconductor structure, characterized by comprising: a substrate comprising a first region and a second region, the second region comprising a first sub-region and a second sub-region; an oxide layer covering a top surface of the first region of the substrate; a gate oxide layer covering a top surface of the second region of the substrate, the gate oxide layer comprising a first gate oxide layer and a second gate oxide layer; an input / output transistor in the first sub-region, the input / output transistor comprising the first gate oxide layer covering a top surface of the first sub-region of the substrate and a high-K dielectric layer on top of the first gate oxide layer; a core transistor in the second sub-region, the core transistor comprising the second gate oxide layer covering a top surface of the second sub-region of the substrate and a high-K dielectric layer on top of the second gate oxide layer, the core transistor further comprising a channel material layer between the second sub-region of the second region of the substrate and the second gate oxide layer; in a direction perpendicular to a top surface of the substrate, a thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer.

10. The semiconductor structure of claim 9, wherein, a material of the oxide layer comprises at least one of SiO2 and Si2N2O.

11. The semiconductor structure of claim 9, wherein, the first region of the substrate comprises a storage active region and a buried word line penetrating the storage active region; the second region of the substrate comprises a peripheral active region.

Images