A method for manufacturing a dual damascene structure
By introducing a sandwich barrier layer as an etching stop layer in the double damask structure and adjusting the thickness and position of the interlayer dielectric layer, the problem of deep hole merging during etching was solved, and the electrical properties and reliability of the metal connection were improved.
Patent Information
- Application Number
- CN202211208854.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-30
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2042-09-30
AI Technical Summary
Existing double damask etching processes are prone to causing the dielectric layers between deep holes to merge during the etching process, and the depth cannot be adjusted, affecting the electrical properties and reliability of the metal connection.
In the fabrication of the double damask structure, a sandwich barrier layer is introduced as an etching stop layer. The thickness and position of the dielectric layer between the first and second layers are adjusted to control the depth and morphology of the trenches and vias. The protective layer and the sandwich barrier layer are used as masks for etching to prevent adjacent vias from connecting.
It effectively adjusts the depth and morphology of through holes, reduces the load effect between adjacent through holes, improves the electrical properties and reliability of metal connections, prevents short circuits, and optimizes metal filling capacity.
Smart Images
Figure CN115547923B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method for fabricating a double damask structure. Background Technology
[0002] In integrated circuit manufacturing processes, double damascene etching is commonly used to form metal interconnects in the back-end BEOL process. To reduce the RC delay of BEOL interconnects, Cu double damascene etching combined with low-k dielectric materials is widely used in 45nm and above processes. Among them, AIO (All-In-One) etching has attracted much attention due to its good low-k damage and chamfer characteristics. In the AIO etching process, because there is no mask between the low-k materials, the dielectric layer between the double damascene deep holes is easily etched away, leading to the merging of adjacent deep holes, and the depth of the two deep holes cannot be quantitatively adjusted. Summary of the Invention
[0003] In view of the above-mentioned defects in the existing double damask process, the present invention provides a method for manufacturing a double damask structure to solve one or more of the above problems.
[0004] To achieve the above objectives, the present invention provides a method for manufacturing a double damask structure, comprising the following steps:
[0005] A substrate is provided, on which a first metal interconnect layer is formed, and an etch stop layer is formed above the first metal interconnect layer;
[0006] A first interlayer dielectric layer, a sandwich barrier layer, a second interlayer dielectric layer, and a protective layer are sequentially formed on the substrate.
[0007] The protective layer and the second interlayer dielectric layer are etched, and the etching stops when a trench is formed in the sandwich barrier layer.
[0008] Etch the sandwich barrier layer and the first interlayer dielectric layer at the location corresponding to the trench to form a through-hole opening;
[0009] Using the protective layer and the sandwich barrier layer as a mask, the first interlayer dielectric layer and the etching stop layer are etched along the opening of the via until the first metal interconnect layer is exposed, forming a via.
[0010] Optionally, the first interlayer dielectric layer and the second interlayer dielectric layer are made of the same material.
[0011] Optionally, the thickness of the first interlayer dielectric layer is greater than or equal to the thickness of the second interlayer dielectric layer, the middle position of the sandwich barrier layer in the thickness direction is at a first distance from the middle position of the first interlayer dielectric layer in the thickness direction, and the middle position of the sandwich barrier layer in the thickness direction is at a second distance from the middle position of the second interlayer dielectric layer in the thickness direction, wherein the first distance is greater than or equal to the second distance.
[0012] Optionally, the thickness of the first interlayer dielectric layer is less than or equal to the thickness of the second interlayer dielectric layer, the middle position of the sandwich barrier layer in the thickness direction is at a first distance from the middle position of the first interlayer dielectric layer in the thickness direction, and the middle position of the sandwich barrier layer in the thickness direction is at a second distance from the middle position of the second interlayer dielectric layer in the thickness direction, wherein the first distance is less than or equal to the second distance.
[0013] Optionally, the thickness of the sandwich barrier layer is between 5 nm and 200 nm.
[0014] Optionally, the first interlayer dielectric layer and the second interlayer dielectric layer are low-k material layers.
[0015] Optionally, the sandwich barrier layer is a SiON layer.
[0016] Optionally, before etching the protective layer and the second interlayer dielectric layer, and before the etching stops at the sandwich barrier layer forming a trench, the method further includes:
[0017] A first mask layer is formed over the protective layer, and a first opening pattern for forming the trench is formed in the first mask layer.
[0018] Optionally, before etching the sandwich barrier layer and the first interlayer dielectric layer at the location corresponding to the trench to form a through-hole opening, the method further includes:
[0019] A back anti-reflective layer is spin-coated in the trench and over the remaining protective layer;
[0020] A second mask layer is formed above the back anti-reflective layer, and a second opening pattern for forming the through-hole opening is formed in the second mask layer;
[0021] The back anti-reflective layer is etched at the location corresponding to the groove.
[0022] Optionally, the method for manufacturing the double damask structure further includes filling the through hole with metal material to form a second metal bonding layer.
[0023] As described above, the method for manufacturing the double damask structure of the present invention has the following beneficial effects:
[0024] In this invention, after forming a first metal interconnect layer and an etch stop layer on a substrate, an interlayer dielectric layer is formed. A sandwich barrier layer is formed within this interlayer dielectric layer, dividing the interlayer dielectric layer into a first interlayer dielectric layer and a second interlayer dielectric layer. This sandwich barrier layer serves as an etch stop layer for trench etching, forming trenches in the second interlayer dielectric layer. After forming the trenches, via openings are first formed in the first interlayer dielectric layer. Then, using the protective layer above the second interlayer dielectric layer and the remaining sandwich barrier layer as a mask, the first interlayer dielectric layer and the etch stop layer are etched further to form vias connecting to the first metal interconnect layer. The position and thickness of the sandwich barrier layer are adjustable; that is, the thicknesses of the first and second interlayer dielectric layers can be adjusted, thereby adjusting the depth of the trench formed in the second interlayer dielectric layer. Correspondingly, the depth and morphology of the subsequently formed vias can be adjusted, and consequently, the electrical properties after subsequent metal filling can be adjusted. Furthermore, the sandwich barrier layer, as a stop layer for trench etching, can reduce the load problem of wiring with different linewidths.
[0025] During via etching, a protective layer above the second interlayer dielectric layer and the remaining sandwich barrier layer are used as masks. The sandwich barrier layer ensures sufficient first interlayer dielectric layer margin between adjacent vias, preventing interconnection between them. Simultaneously, the sandwich barrier layer facilitates adjustment of the via chamfer, optimizes the thickness of the metal filling capability, and ensures good electrical properties of the formed metal interconnect layer. Attached Figure Description
[0026] Figure 1 The diagram shows a flowchart illustrating the manufacturing method of the double damask structure provided in Embodiment 1 of the present invention.
[0027] Figure 2 Displayed as Figure 1 A schematic diagram of the substrate structure provided in step S101 of the method shown.
[0028] Figure 3 Displayed as in Figure 1 A schematic diagram of the structure formed in step S102 of the method shown.
[0029] Figure 4 Displayed as in Figure 3 A schematic diagram of the structure in which the groove is formed.
[0030] Figure 5 Displayed as in Figure 4 A schematic diagram of the spin-coated back anti-reflective layer in the structure shown.
[0031] Figure 6 Displayed as in Figure 5 A schematic diagram of a structure in which a second mask layer is formed on top of the structure shown.
[0032] Figure 7 The diagram shows a structure in which a through-hole opening is formed under the action of the second mask layer.
[0033] Figure 8 The diagram shows the structure after the anti-reflective layer on the back has been removed.
[0034] Figure 9 The diagram shows a structure formed by etching the first interlayer dielectric layer and the etching stop layer to create a through-hole.
[0035] Component designation explanation
[0036] 100 Substrate 107 First mask layer
[0037] 101 First metal bonding layer 1070 First window pattern
[0038] 102 Etching stop layer 1071 Trench
[0039] 103 First interlayer dielectric layer 108 Back anti-reflective layer
[0040] 104 Sandwich barrier layer 109 Second mask layer
[0041] 105 Second interlayer dielectric layer 1090 Second window pattern
[0042] 106 Protective layer 1101 Through-hole opening
[0043] 1061 First protective layer 110 Through hole
[0044] 1062 Second protective layer Detailed Implementation
[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0046] Example 1
[0047] This embodiment provides a method for manufacturing a double damask structure, such as... Figure 1 As shown, the manufacturing method includes the following steps:
[0048] S101: Provide a substrate on which a first metal interconnect layer is formed and an etch stop layer is formed above the first metal interconnect layer;
[0049] like Figure 2As shown, a substrate 100 is first provided, which can be any suitable semiconductor substrate 100 such as a silicon substrate 100, a germanium-silicon substrate 100, or a silicon carbide substrate 100. A first metal interconnect layer 101 is formed in the substrate 100, and the adjacent portions of the metal interconnect layer can be filled with insulating material to form a planarization layer structure. After forming the first metal interconnect layer 101, an etch stop layer 102 is formed above the first metal interconnect layer 101. The etch stop layer 102 can be a SiCN layer or a SiN layer, etc.
[0050] S102: A first interlayer dielectric layer, a sandwich barrier layer, a second interlayer dielectric layer, and a protective layer are sequentially formed on the substrate;
[0051] like Figure 3 As shown, in Figure 2 After forming the etch stop layer, an interlayer dielectric layer is formed above the etch stop layer. In this embodiment, the interlayer dielectric layer includes a first interlayer dielectric layer 103, a sandwich barrier layer 104, and a second interlayer dielectric layer 105, which are sequentially stacked from the etch stop layer. In an optional embodiment, the first interlayer dielectric layer 103 and the second interlayer dielectric layer 105 are made of the same material, preferably a low-k material layer, such as SiOF (fluorine-doped silicon dioxide) or SiOC (carbon-doped silicon dioxide).
[0052] The aforementioned sandwich barrier layer 104 is located between the first interlayer dielectric layer 103 and the second interlayer dielectric layer 105. This sandwich barrier layer 104 serves as an etching stop layer 102 for the subsequent formation of the trench 1071. The position and thickness of the sandwich barrier layer 104 between the first and second interlayer dielectric layers 103 and 105 are adjustable; that is, the thicknesses of the first and second interlayer dielectric layers 103 and 105 are adjustable. Preferably, the thickness of both the first and second interlayer dielectric layers 103 and 105 are adjustable. However, for the same metal interconnect layer to be formed, the total thickness of the first and second interlayer dielectric layers 103 remains constant. This ensures the overall thickness of the low-k dielectric layer and improves the reliability of the device. Optionally, the total thickness of the first interlayer dielectric layer 103 and the second interlayer dielectric layer 105 is between 200 nm and 4 μm, and the total thickness of the first interlayer dielectric layer 103 and the second interlayer dielectric layer 105 can be adjusted accordingly based on the thickness of their corresponding metal interconnect layers. For example, for a thicker top metal interconnect layer, the thickness of the first interlayer dielectric layer 103 and the total thickness of the second interlayer dielectric layer 105 are between 1.5 μm and 4 μm; for other non-top metal interconnect layers, the thickness of the first interlayer dielectric layer 103 and the total thickness of the second interlayer dielectric layer 105 are between 100 nm and 500 nm. Optionally, the thickness of the sandwich barrier layer 104 is between 5 nm and 200 nm.
[0053] Furthermore, the position of the sandwich barrier layer 104 can be adjusted according to actual process requirements. That is, the thickness of the first interlayer dielectric layer 103 and the thickness of the second interlayer dielectric layer 105 can be adjusted according to the actual needs of the process, while ensuring the total thickness requirement. For example, the thickness of the first interlayer dielectric layer 103 can be greater than or equal to the thickness of the second interlayer dielectric layer 105, i.e., as... Figure 3 As shown, the midpoint of the sandwich barrier layer 104 in the thickness direction is at a first distance H1 from the midpoint of the first interlayer dielectric layer 103 in the thickness direction, and the midpoint of the sandwich barrier layer 104 in the thickness direction is at a second distance H2 from the midpoint of the second interlayer dielectric layer 105 in the thickness direction. The first distance H1 is greater than or equal to the second distance H2; or the thickness of the first interlayer dielectric layer 103 is less than or equal to the thickness of the second interlayer dielectric layer 105, that is, the first distance H1 is less than or equal to the second distance H2. In an optional embodiment, the sandwich barrier layer 104 may be a single-layer structure formed from one of SiON, SiCN, carbon, or SiN layers, or a multilayer structure formed from multiple of these materials.
[0054] After forming the second interlayer dielectric layer 105, a protective layer 106 is formed. In this embodiment, the protective layer 106 is preferably a multilayer structure, for example, it may include a first protective layer 1061 and a second protective layer 1062. Although only the two-layer structure of the first protective layer 1061 and the second protective layer 1062 is shown in the figure, it can be understood that the protective layer 106 can be a multilayer structure in which the first protective layer 1061 and the second protective layer 1062 are alternately stacked. In an optional embodiment, the first protective layer 1061 is a TEOS protective layer 106, and the second protective layer 1062 is a TiN layer.
[0055] S103: Etch the protective layer and the second interlayer dielectric layer, and the etching stops to form a trench in the sandwich barrier layer;
[0056] Before etching the protective layer 106 and the second interlayer dielectric layer 105, the same applies. Figure 3 As shown, a first mask layer 107 is formed above the protective layer 106, and a first window pattern 1070 is formed in the first mask layer 107. The first window pattern 1070 is formed at the corresponding position of the first metal interconnect layer 101. Optionally, the first mask layer 107 has a three-layer structure, including a carbon layer, a back anti-reflective layer 108, and a photoresist layer sequentially stacked above the protective layer 106.
[0057] The first window pattern 1070 is used to etch the protective layer 106 and the second interlayer dielectric layer 105, and the etching stops on the sandwich barrier layer 104, as shown. Figure 4As shown, trench 1071 is formed. As described above, since the position of the sandwich barrier layer 104 between the first interlayer dielectric layer 103 and the second dielectric layer is adjustable, the depth of trench 1071 can be adjusted, which is beneficial for adjusting the electrical properties after subsequent Cu filling. In addition, the sandwich barrier layer 104, as a stop layer for trench 1071, can also reduce the load problem of wiring with different linewidths.
[0058] S104: Etch the sandwich barrier layer and the first interlayer dielectric layer at the position corresponding to the trench to form a through hole opening 1101;
[0059] To prevent the etching of the via opening 1101 from affecting the trench 1071, such as Figure 5 As shown, firstly, a back anti-reflective layer 108 is spin-coated in the trench 1071 and above the remaining protective layer 106, and then the back anti-reflective layer 108 is planarized. Then, as... Figure 6 As shown, a second mask layer 109 is formed above the planarized back anti-reflective layer 108. This second mask layer 109 has a first window pattern 1090 formed at the location corresponding to the trench 1071. The opening size of the first window pattern 1090 is smaller than the opening size of the trench 1071. Optionally, two or more first window patterns 1090 are formed at the location corresponding to one trench 1071. In an optional embodiment, the second mask layer 109 is also a multilayer structure, and may also include a carbon layer, the back anti-reflective layer 108, and a photoresist layer sequentially stacked above the protective layer 106.
[0060] like Figure 7 As shown, the back anti-reflective layer 108, the sandwich barrier layer 104 and the first interlayer dielectric layer 103 are etched by the first window pattern 1090. The etching stops in the first interlayer dielectric layer 103, that is, the first interlayer dielectric layer 103 is not etched through, thereby forming a through hole opening 1101 in the first interlayer dielectric layer 103.
[0061] S104: Using the protective layer and the sandwich barrier layer as a mask, continue etching the first interlayer dielectric layer and the etching stop layer along the through-hole opening until the first metal interconnect layer is exposed, forming a through-hole.
[0062] After forming the through-hole opening 1101, firstly, as Figure 8 As shown, the second mask layer 109 and the back anti-reflective layer 108 are removed, exposing the surface protective layer 106, the trench 1071, and the through-hole opening 1101. The bottom of the trench 1071 exposes the remaining sandwich barrier layer 104.
[0063] like Figure 9As shown, using the surface protective layer 106 and the sandwich barrier layer 104 as masks, the first interlayer dielectric layer 103 and the etching stop layer 102 are etched along the via opening 1101 until the first metal interconnect layer 101 is exposed, forming a via 110. During the etching process of the via 110, the surface protective layer 106 and the sandwich barrier layer 104 are used as masks for one etching operation, etching the remaining first interlayer dielectric layer 103 and the bottom etching stop layer 102, stopping at the first metal interconnect layer 101. Under the protection of the sandwich barrier layer 104, the first interlayer dielectric layer 103 between two adjacent vias 110 can ensure sufficient margin of the first interlayer dielectric layer 103 between the vias 110, preventing the vias 110 from merging and preventing short circuits between the vias 110 during subsequent metal filling; at the same time, the sandwich barrier layer 104 also helps to adjust the chamfer of the via 110, optimizing the metal filling capability of the subsequent vias 110.
[0064] After the via 110 is formed, the process further includes filling the via 110 with metal to form a second metal connection layer. In this embodiment, the via 110 is preferably filled with Cu metal. As described above, due to the provision of the sandwich barrier layer 104, the morphology and depth of the via 110 are ensured, and the filling with metal can form an electrically stable connection layer, which is beneficial to improving the reliability of the device.
[0065] This embodiment also provides a metal interconnect structure, which is formed using the above-described method for fabricating a double damask structure. This metal interconnect structure also exhibits good electrical properties and reliability.
[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a double damask structure, characterized in that, Includes the following steps: A substrate is provided, on which a first metal interconnect layer is formed, and an etch stop layer is formed above the first metal interconnect layer; A first interlayer dielectric layer, a sandwich barrier layer, a second interlayer dielectric layer, and a protective layer are sequentially formed on the substrate. The protective layer and the second interlayer dielectric layer are etched, and the etching stops when a trench is formed in the sandwich barrier layer. The sandwich barrier layer and the first interlayer dielectric layer are etched at the position corresponding to the trench. The etching stops in the first interlayer dielectric layer and does not penetrate the first interlayer dielectric layer, so as to form a through hole opening in the first interlayer dielectric layer. Using the protective layer and the sandwich barrier layer as a mask, the first interlayer dielectric layer and the etching stop layer are etched along the opening of the via until the first metal interconnect layer is exposed, forming a via.
2. The method for manufacturing the double damask structure according to claim 1, characterized in that, The first interlayer dielectric layer and the second interlayer dielectric layer are made of the same material.
3. The method for manufacturing the double damask structure according to claim 1, characterized in that, The thickness of the first interlayer dielectric layer is greater than or equal to the thickness of the second interlayer dielectric layer. The middle position of the sandwich barrier layer in the thickness direction is at a first distance from the middle position of the first interlayer dielectric layer in the thickness direction. The middle position of the sandwich barrier layer in the thickness direction is at a second distance from the middle position of the second interlayer dielectric layer in the thickness direction. The first distance is greater than or equal to the second distance.
4. The method for manufacturing the double damask structure according to claim 1, characterized in that, The thickness of the first interlayer dielectric layer is less than or equal to the thickness of the second interlayer dielectric layer. The middle position of the sandwich barrier layer in the thickness direction is at a first distance from the middle position of the first interlayer dielectric layer in the thickness direction. The middle position of the sandwich barrier layer in the thickness direction is at a second distance from the middle position of the second interlayer dielectric layer in the thickness direction. The first distance is less than or equal to the second distance.
5. The method for manufacturing a double damask structure according to claim 1, 3, or 4, characterized in that, The thickness of the sandwich barrier layer is between 5 nm and 200 nm.
6. The method for manufacturing a double damask structure according to claim 1, characterized in that, The first interlayer dielectric layer and the second interlayer dielectric layer are low-k material layers.
7. The method for manufacturing a double damask structure according to claim 1, characterized in that, The sandwich barrier layer is a SiON layer.
8. The method for manufacturing a double damask structure according to claim 1, characterized in that, Before etching the protective layer and the second interlayer dielectric layer, and before the etching stops at the sandwich barrier layer forming a trench, the process further includes: A first mask layer is formed over the protective layer, and a first opening pattern for forming the trench is formed in the first mask layer.
9. The method for manufacturing a double damask structure according to claim 8, characterized in that, Before etching the sandwich barrier layer and the first interlayer dielectric layer at the location corresponding to the trench to form a through-hole opening, the method further includes: A back anti-reflective layer is spin-coated in the trench and over the remaining protective layer; A second mask layer is formed above the back anti-reflective layer, and a second opening pattern for forming the through-hole opening is formed in the second mask layer; The back anti-reflective layer is etched at the location corresponding to the groove.
10. The method for manufacturing a double damask structure according to claim 1, characterized in that, Also includes: The through-hole is filled with metal material to form a second metal bonding layer.
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