Oscillation circuit and memory

Abstract

An embodiment of the present disclosure provides an oscillator circuit and a memory, wherein the oscillator circuit includes: a first buffer circuit, a first delay circuit, a second delay circuit, and a second buffer circuit; wherein: the delay time of the first delay circuit varies with temperature and / or transistor process angle, and the delay time of the second delay circuit is independent of temperature and transistor process angle; the first buffer circuit is used to transmit a received first clock signal to the first delay circuit or the second delay circuit based on an enable signal; the first delay circuit or the second delay circuit is used to delay the first clock signal to obtain a first output signal, and transmit the first output signal to the second buffer circuit; the second buffer circuit is used to transmit the first output signal as the first clock signal to the first buffer circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor integrated circuits, and in particular to, but not limited to, an oscillator circuit and a memory. Background Art

[0002] The Wck oscillation (Oscillation, Osc) circuit is designed to simulate changes in the internal parameters wck2dqi / wck2dqo of the fifth-generation LowPower Double Data Rate 5 (LPDDR5) chip, allowing the controller to keep track of changes in the wck2dqi / wck2dqo parameters within the LPDDR5 chip. wck2dqi represents the delay from the controller's clock signal wck to the data signal dq input, and wck2dqo represents the delay from the controller's clock signal wck to the data signal dq output. During the chip testing phase, the period of the wckOsc output signal is calculated over a period of time, and this period is recorded as tOsc. During the testing phase, due to differences in test methods and transistor process corners, the difference between the introduced period tOsc and wck2dqi / wck2dqo is difficult to control during the design phase. Summary of the Invention

[0003] Embodiments of the present disclosure provide an oscillation circuit and a memory.

[0004] On the one hand, an embodiment of the present disclosure provides an oscillation circuit, which includes: a first buffer circuit, a first delay circuit, a second delay circuit, and a second buffer circuit; wherein: the delay time of the first delay circuit varies with temperature and / or transistor process angle, and the delay time of the second delay circuit is independent of temperature and transistor process angle; the first buffer circuit is used to transmit a received first clock signal to the first delay circuit or the second delay circuit based on an enable signal; the first delay circuit or the second delay circuit is used to delay the first clock signal to obtain a first output signal, and transmit the first output signal to the second buffer circuit; the second buffer circuit is used to transmit the first output signal as the first clock signal to the first buffer circuit.

[0005] In some embodiments, the first delay circuit includes: at least one first sub-delay circuit, the delay time of each first sub-delay circuit varies with temperature and / or transistor process angle, and the delay times of different first sub-delay circuits are different; a first selection circuit, coupled between the first buffer circuit and the at least one first sub-delay circuit, for selecting one of the first sub-delay circuits to delay the first clock signal according to a first selection signal.

[0006] In some embodiments, the first selection circuit includes at least one first NAND gate circuit, the first selection signal includes at least one first selection sub-signal, the first input end of each first NAND gate circuit receives the first clock signal, the second input end of each first NAND gate circuit receives one first selection sub-signal, the output end of each first NAND gate circuit is connected to the input end of one first sub-delay circuit, and the number of the first NAND gate circuits and the number of the first selection sub-signals are the same as the number of the first sub-delay circuits.

[0007] In some embodiments, the first delay circuit includes multiple first sub-delay circuits; the first delay circuit also includes a second NAND gate circuit, multiple input ends of the second NAND gate circuit are respectively connected to the output ends of the multiple first sub-delay circuits, and the output end of the second NAND gate circuit is used to output the first output signal.

[0008] In some embodiments, the first sub-delay circuit includes cascaded first inverters, the input end of the first inverter of each stage is connected to the output end of the first inverter of the previous stage, the input end of the first inverter of the first stage serves as the input end of the first sub-delay circuit, and the output end of the first inverter of the last stage serves as the output end of the first sub-delay circuit, and the delay time of at least part of the first inverters changes with temperature and / or transistor process angle.

[0009] In some embodiments, different first sub-delay circuits have different numbers of first inverters.

[0010] In some embodiments, the first inverter includes: a first P (Positive) type transistor and a first N (Negative) type transistor, the source of the first P type transistor receives a first power supply, the gate of the first P type transistor and the gate of the first N type transistor are input terminals of the first inverter, the drain of the first P type transistor and the drain of the first N type transistor are output terminals of the first inverter, and the source of the first N type transistor is grounded, wherein the first power supply of at least part of the first inverter is related to temperature and / or the transistor process.

[0011] In some embodiments, the second delay circuit includes: at least one second sub-delay circuit, the delay time of each second sub-delay circuit is independent of temperature and transistor process angle, and the delay times of different second sub-delay circuits are different; a second selection circuit, coupled between the first buffer circuit and the at least one second sub-delay circuit, for selecting one of the second sub-delay circuits to delay the first clock signal according to a second selection signal.

[0012] In some embodiments, the second selection circuit includes at least one third NAND gate circuit, the second selection signal includes at least one second selection sub-signal, the first input end of each of the third NAND gate circuits receives the first clock signal, the second input end of each of the third NAND gate circuits receives a second selection sub-signal, the output end of each of the third NAND gate circuits is connected to the input end of a second sub-delay circuit, and the number of the third NAND gate circuits, the number of the second selection sub-signals and the number of the second sub-delay circuits are the same.

[0013] In some embodiments, the second delay circuit includes multiple second sub-delay circuits; the second delay circuit also includes a fourth NAND gate circuit, multiple input ends of the fourth NAND gate circuit are respectively connected to the output ends of the multiple second sub-delay circuits, and the output end of the fourth NAND gate circuit is used to output the first output signal.

[0014] In some embodiments, the second sub-delay circuit includes cascaded second inverters, the input end of the second inverter of each stage is connected to the output end of the second inverter of the previous stage, the input end of the second inverter of the first stage serves as the input end of the second sub-delay circuit, and the output end of the second inverter of the last stage serves as the output end of the second sub-delay circuit. The delay time of the second inverter is independent of temperature and transistor process angle.

[0015] In some embodiments, the second inverter includes: a second P-type transistor and a second N-type transistor, the source of the second P-type transistor receives a second power supply, the gate of the second P-type transistor and the gate of the second N-type transistor are input terminals of the second inverter, the drain of the second P-type transistor and the drain of the second N-type transistor are output terminals of the second inverter, the source of the second N-type transistor is grounded, and the second power supply is independent of temperature and transistor process angle.

[0016] In some embodiments, the voltage of the second power supply is 1.2 volts (V).

[0017] In some embodiments, the oscillation circuit also includes: a third delay circuit and a fourth delay circuit; wherein: the first buffer circuit is also used to transmit the received second clock signal to the third delay circuit or the fourth delay circuit based on the enable signal, the third delay circuit has the same structure as the first delay circuit, and the fourth delay circuit has the same structure as the second delay circuit; the third delay circuit or the fourth delay circuit is used to delay the second clock signal to obtain a second output signal, and transmit the second output signal to the second buffer circuit; the second buffer circuit is used to transmit the second output signal as the second clock signal to the first buffer circuit.

[0018] On the other hand, an embodiment of the present disclosure provides a memory, comprising the oscillation circuit in any of the above embodiments.

[0019] In an embodiment of the present disclosure, an oscillation circuit includes a first buffer circuit, a first delay circuit, a second delay circuit, and a second buffer circuit. During a test phase, different test modes are used to select whether to use a first delay circuit whose delay time varies with temperature and / or transistor process angle or a second delay circuit whose delay time does not vary with temperature and transistor process angle to delay the first clock signal, so that the difference between the period tOsc of the first output signal and the wck2dqi / wck2dqo measured inside the actual chip gradually decreases. In this way, the difference between the period tOsc of the first output signal and wck2dqi / wck2dqo introduced by different test methods, test environments, etc. can be reduced, thereby improving the performance of the oscillation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0021] Figure 1 A schematic diagram of the structure of an oscillator circuit provided in an embodiment of the present disclosure Figure 1 ;

[0022] Figure 2 A schematic diagram of the structure of an oscillator circuit provided in an embodiment of the present disclosure Figure 2 ;

[0023] Figure 3 A schematic diagram of the structure of an oscillator circuit provided in an embodiment of the present disclosure Figure 3 ;

[0024] Figure 4 A schematic diagram of the structure of an oscillator circuit provided in an embodiment of the present disclosure Figure 4 ;

[0025] Figure 5 A schematic diagram of the structure of a first sub-delay circuit provided in an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of the structure of a first inverter provided in an embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of the structure of a second sub-delay circuit provided in an embodiment of the present disclosure;

[0028] Figure 8 A schematic diagram of the structure of a second inverter provided in an embodiment of the present disclosure;

[0029] Figure 9 A schematic diagram of the structure of an oscillator circuit provided in an embodiment of the present disclosure Figure 5 ;

[0030] Figure 10 A schematic diagram of the structure of an oscillator circuit provided in an embodiment of the present disclosure Figure 6 ;

[0031] Figure 11 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0034] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0035] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] The present disclosure provides an oscillating circuit, referring to Figure 1 The oscillation circuit 100 includes a first buffer circuit 10 , a first delay circuit 20 , a second delay circuit 30 and a second buffer circuit 40 .

[0038] The delay time of the first delay circuit 20 varies with temperature and / or transistor process angle, and the delay time of the second delay circuit 30 is independent of temperature and transistor process angle.

[0039] The first buffer circuit 10 is configured to transmit the received first clock signal to the first delay circuit 20 or the second delay circuit 30 based on the enable signal;

[0040] The first delay circuit 20 or the second delay circuit 30 is used to delay the first clock signal to obtain a first output signal, and transmit the first output signal to the second buffer circuit 40;

[0041] The second buffer circuit 40 is configured to transmit the first output signal as a first clock signal to the first buffer circuit 10 .

[0042] It should be noted that the oscillator circuit in the embodiment of the present disclosure can be used in a memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), etc.

[0043] The enable signal is a signal sent externally to the oscillation circuit. When the first buffer circuit in the oscillation circuit receives the enable signal, the oscillation circuit starts to operate. In the embodiment of the present disclosure, both the first buffer circuit and the second buffer circuit may include a buffer.

[0044] Because the first buffer circuit transmits the first clock signal to the first delay circuit or the second delay circuit to obtain the first output signal, and the second buffer circuit then transmits the first output signal as the first clock signal to the first buffer circuit, the signal within the oscillator circuit in the disclosed embodiment is cyclic, and the first clock signal and the first output signal can be the same. During implementation, the first output signal or the first clock signal can be extracted and its period tOsc can be measured to obtain wck2dqi / wck2dqo.

[0045] The first buffer circuit, the first delay circuit (or the second delay circuit), and the second buffer circuit are connected in series to form an oscillator to generate a first output signal. The first delay circuit and the second delay circuit can include any module formed by combining various basic electrical components that can delay the first clock signal, such as an inverter chain, and are not limited in this embodiment of the present disclosure.

[0046] During the test phase, the first delay circuit or the second delay circuit can be enabled according to the test mode. The delay time of the first delay circuit varies with temperature and / or transistor process angle. This means the delay time of the first delay circuit varies within a range, and the specific delay time is affected by temperature and transistor process angle. The delay time of the second delay circuit is independent of temperature and transistor process angle. This means the delay time of the second delay circuit is a constant and unchanging value. The first delay circuit and the second delay circuit can delay the rising edge or falling edge of the first clock signal, thereby changing the period of the first clock signal.

[0047] Corner refers to the variation in transistor parameters during semiconductor device manufacturing due to differences in position on the same wafer or between wafer batches. Corner angles are generally categorized as SS, TT, FF, SF, and FS. FF indicates a circuit composed of the fastest P-type transistor and the fastest N-type transistor, TT indicates a circuit composed of typical P-type transistors and typical N-type transistors, SS indicates a circuit composed of the slowest P-type transistor and the slowest N-type transistor, SF indicates a circuit composed of the slowest P-type transistor and the fastest N-type transistor, and FS indicates a circuit composed of the fastest P-type transistor and the slowest N-type transistor. Fast and slow refer to the short or long delay times of the transistors. If a transistor with a corner angle of FF is used in the first delay circuit, the delay time of the first delay circuit will be short, for example, 30 picoseconds (ps). If a transistor with a corner angle of SS is used in the first delay circuit, the delay time of the first delay circuit will be long, for example, 120 ps.

[0048] Generally, when the temperature rises, the delay time of the first delay circuit will increase, thereby slowing down the oscillation frequency of the oscillation circuit; when the temperature drops, the delay time of the first delay circuit will decrease, thereby increasing the oscillation frequency of the oscillation circuit.

[0049] In an embodiment of the present disclosure, an oscillation circuit includes a first buffer circuit, a first delay circuit, a second delay circuit, and a second buffer circuit. During a test phase, different test modes are used to select whether to use a first delay circuit whose delay time varies with temperature and / or transistor process angle or a second delay circuit whose delay time does not vary with temperature and transistor process angle to delay the first clock signal, so that the difference between the period tOsc of the first output signal and the wck2dqi / wck2dqo measured inside the actual chip gradually decreases. In this way, the difference between the period tOsc of the first output signal and wck2dqi / wck2dqo introduced by different test methods, test environments, etc. can be reduced, thereby improving the performance of the oscillation circuit.

[0050] In some embodiments, the oscillation circuit may further include: a selection circuit for selecting the first delay circuit and the second delay circuit. The selection circuit may include a logic device, such as a NAND gate.

[0051] In some embodiments, reference Figure 2 The first delay circuit 20 may include: at least one first sub-delay circuit 201, wherein the delay time of each first sub-delay circuit 201 varies with temperature and / or transistor process angle, and the delay times of different first sub-delay circuits 201 are different;

[0052] The first selection circuit 202 is coupled between the first buffer circuit 10 and the plurality of first sub-delay circuits 201 , and is configured to select one of the first sub-delay circuits 201 to delay the first clock signal according to a first selection signal.

[0053] Here, the number of first sub-delay circuits in the first delay circuit can be set as needed. For example, three, four, and so on, can be set as needed, and the delay times of different first sub-delay circuits can vary. Taking three first sub-delay circuits as an example, the first first sub-delay circuit can delay the first clock signal by 30 ps, ​​the second first sub-delay circuit can delay the first clock signal by 60 ps, ​​and the third first sub-delay circuit can delay the first clock signal by 120 ps. In implementation, each first sub-delay circuit can be configured with a different number of transistors having the same process angle, or different first sub-delay circuits can be configured with transistors having different process angles, thereby varying the delay times of different first sub-delay circuits.

[0054] The first selection circuit is configured to select a first sub-delay circuit and connect it to the first buffer circuit, thereby enabling the selected first sub-delay circuit to delay the first clock signal transmitted by the first buffer circuit. In some embodiments, the first selection circuit may include a switch that connects a first sub-delay circuit to the first buffer circuit based on a control signal. In other embodiments, the first selection circuit may include at least one logic device, such as a NAND gate, each of which is connected to a first sub-delay circuit. The output of the logic device may be controlled based on a control signal to select a first sub-delay circuit, although this is not a limitation in the present disclosure.

[0055] In the disclosed embodiment, the first delay circuit includes at least one first sub-delay circuit and a first selection circuit. Different first sub-delay circuits have different delay times. Therefore, the first delay circuit or the second delay circuit can be selected first according to the test mode. When the first delay circuit is selected, one of the first sub-delay circuits can be selected according to the required delay time. In this way, the delay time can be adjusted to meet different needs, thereby further improving the performance of the oscillation circuit.

[0056] In some embodiments, continue to refer to Figure 2 The second delay circuit 30 may include: at least one second sub-delay circuit 301, the delay time of each second sub-delay circuit 301 is independent of temperature and transistor process angle, and the delay times of different second sub-delay circuits 301 are different;

[0057] The second selection circuit 302 is coupled between the first buffer circuit 10 and at least one second sub-delay circuit 301 , and is configured to select one of the second sub-delay circuits 301 to delay the first clock signal according to a second selection signal.

[0058] The second sub-delay circuit and the second selection circuit can be understood with reference to the first sub-delay circuit and the first selection circuit described above and will not be further described here. It should be noted that the difference between the first sub-delay circuit and the second sub-delay circuit is at least that the delay time of the first sub-delay circuit varies with temperature and / or transistor process corners, while the delay time of the second sub-delay circuit does not vary with temperature and / or transistor process corners.

[0059] In the disclosed embodiment, the second delay circuit includes at least one second sub-delay circuit and a second selection circuit. Different second sub-delay circuits have different delay times. Therefore, the first delay circuit or the second delay circuit can be selected first according to the test mode. When the second delay circuit is selected, one of the second sub-delay circuits can be selected according to the required delay time. In this way, the delay time can be adjusted to meet different needs, thereby further improving the performance of the oscillation circuit.

[0060] In some embodiments, reference Figure 3 The first selection circuit 202 may include at least one first NAND gate circuit 221. Accordingly, the first selection signal includes at least one first selection sub-signal. Generally speaking, the number of first NAND gate circuits 221 and the number of first selection sub-signals are the same as the number of first sub-delay circuits 201. The first input of each first NAND gate circuit 221 receives the first clock signal, the second input of each first NAND gate circuit 221 receives a first selection sub-signal, and the output of each first NAND gate circuit 221 is connected to the input of one of the first sub-delay circuits 201.

[0061] Here, the first NAND gate circuit is used to perform a NAND operation on a first selection sub-signal and a first clock signal. When the first selection sub-signal is at a high level, the first NAND gate circuit acts as an inverter to output an inverted signal of the first clock signal.

[0062] The first selection signal can be a signal related to the test mode, including at least one first selection sub-signal. When the first clock signal is selected to be delayed through the first delay circuit, one of the first selection sub-signals in the first selection signal can be a high level, and the remaining first selection sub-signals can be a low level, thereby selecting a first sub-delay circuit from at least one first sub-delay circuit to delay the first clock signal.

[0063] In the embodiment of the present disclosure, the first selection circuit includes a simple first NAND gate circuit, which can simplify the circuit composition while realizing the function of selecting a first sub-delay circuit.

[0064] In some embodiments, continue to refer to Figure 3 The second selection circuit 302 includes at least one third NAND gate circuit 321. Correspondingly, the second selection signal includes at least one second selection sub-signal. Generally speaking, the number of third NAND gate circuits 321 and the number of second selection sub-signals are the same as the number of second sub-delay circuits 301. The first input of each third NAND gate circuit 321 receives the first clock signal, the second input of each third NAND gate circuit 321 receives a second selection sub-signal, and the output of each third NAND gate circuit 321 is connected to the input of one of the second sub-delay circuits 301.

[0065] Here, the third NAND gate circuit and the second selection signal can be understood with reference to the first NAND gate circuit and the first selection signal, and will not be described in detail here. It should be noted that since either the first delay circuit or the second delay circuit is selected to delay the first clock signal, when one of the first selection signals is at a high level (i.e., one of the first sub-delay circuits in the first delay circuit is selected to delay the first clock signal), the second selection sub-signals in the second selection signal can all be at a low level. When one of the second selection signals is at a high level (i.e., one of the second sub-delay circuits in the second delay circuit is selected to delay the first clock signal), the first selection sub-signals in the first selection signal can all be at a low level.

[0066] In the embodiment of the present disclosure, the second selection circuit includes a simple third NAND gate circuit, which can simplify the circuit composition while realizing the function of selecting a second sub-delay circuit.

[0067] In some embodiments, reference Figure 4 The first delay circuit 20 includes multiple first sub-delay circuits 201; the first delay circuit 20 may further include a second NAND gate circuit 203, multiple input ends of the second NAND gate circuit 203 are respectively connected to the output ends of the multiple first sub-delay circuits 201, and the output end of the second NAND gate circuit 203 is used to output the first output signal.

[0068] Here, the second NAND gate circuit is used to perform a NAND operation on the outputs of the plurality of first sub-delay circuits. For example, when the number of first sub-delay circuits is three, when the outputs of two first sub-delay circuits remain high, the second NAND gate circuit functions as an inverter and outputs the inverse of the output of the remaining first sub-delay circuit.

[0069] In an embodiment of the present disclosure, the first delay circuit also includes a second NAND gate circuit. The second NAND gate circuit can merge the outputs of multiple first sub-delay circuits and perform a NAND operation on the outputs of multiple first sub-delay circuits to obtain a first output signal. This can simplify the connection between the multiple first sub-delay circuits and the second buffer circuit.

[0070] In some embodiments, continue to refer to Figure 4 The second delay circuit 30 includes multiple second sub-delay circuits 301; the second delay circuit 30 also includes a fourth NAND gate circuit 303, multiple input ends of the fourth NAND gate circuit 303 are respectively connected to the output ends of the multiple second sub-delay circuits 301, and the output end of the fourth NAND gate circuit 303 is used to output the first output signal.

[0071] Here, the fourth NAND gate circuit is used to perform a NAND operation on the outputs of the plurality of second sub-delay circuits. For example, when the number of second sub-delay circuits is three, when the outputs of two second sub-delay circuits are high, the fourth NAND gate circuit functions as an inverter to output the inverse of the output of the remaining second sub-delay circuit.

[0072] In the embodiment of the present disclosure, the second delay circuit also includes a fourth NAND gate circuit. The fourth NAND gate circuit can merge the outputs of multiple second sub-delay circuits and perform NAND operations on the outputs of multiple second sub-delay circuits to obtain a first output signal. This can simplify the connection between the multiple second sub-delay circuits and the second buffer circuit.

[0073] In each of the aforementioned circuits, the specific composition can be specifically designed according to the circuit function to be implemented, and is not limited to a fixed implementation scheme. There are many mature circuit modules that can be selected. The following only provides the specific composition of some circuit modules as an example.

[0074] refer to Figure 5 The first sub-delay circuit 201 may include cascaded first inverters 2011, where the input end of each stage of the first inverter 2011 is connected to the output end of the first inverter 2011 of the previous stage, the input end of the first-stage first inverter 2011 serves as the input end of the first sub-delay circuit 201, and the output end of the last-stage first inverter 2011 serves as the output end of the first sub-delay circuit 201. The delay time of at least part of the first inverters 2011 varies with temperature and / or transistor process angle.

[0075] Here, the first inverter has a preset output hysteresis, meaning that the first inverter can delay the output of the first clock signal by a preset time. During implementation, the number of cascaded first inverters can be set based on the desired delay time, so that the sum of the preset output hysteresis of the cascaded first inverters equals the desired delay time.

[0076] The delay time of the first inverter varies with temperature and / or transistor process angle. For example, when the transistor is at an SS process angle and high temperature, the delay time of the first inverter may be 60 ps; when the transistor is at an FF process angle and low temperature, the delay time of the first inverter may be 40 ps, ​​etc.

[0077] During implementation, different first sub-delay circuits have different numbers of first inverters, and the number of first inverters in the first sub-delay circuit can be set according to the required delay time.

[0078] In some embodiments, reference Figure 4 , from top to bottom, the number of first inverters in the first first sub-delay circuit 201 may be 2, the number of first inverters in the second first sub-delay circuit 201 may be 4, and the number of first inverters in the third first sub-delay circuit 201 may be 6.

[0079] It should be noted that, when the first delay circuit also includes a second NAND gate circuit, if the number of first inverters in a first sub-delay circuit is an odd number, the output of the cascaded first inverter will affect the output of the second NAND gate circuit. Therefore, the number of first inverters in the first sub-delay circuit should be an even number.

[0080] refer to Figure 6 The first inverter 2011 may include: a first P-type transistor P1 and a first N-type transistor N1, the source of the first P-type transistor P1 receives a first power supply Vcc, the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are input terminals of the first inverter 2011, the drain of the first P-type transistor P1 and the drain of the first N-type transistor N1 are output terminals of the first inverter 2011, and the source of the first N-type transistor N1 is grounded, wherein the first power supply Vcc of at least part of the first inverter 2011 is related to temperature and / or transistor process.

[0081] Here, the first power supply Vcc of at least some of the first inverters 2011 being temperature- and / or transistor-process-dependent means that the first power supply of at least one first inverter in a first sub-delay circuit is temperature- and / or transistor-process-dependent, thereby making the delay time of the first delay circuit variable. The first power supply Vcc may be the power supply of the first sub-delay circuit.

[0082] refer to Figure 7The second sub-delay circuit 301 includes cascaded second inverters 3011. The input end of each stage of the second inverter 3011 is connected to the output end of the second inverter 3011 of the previous stage. The input end of the first stage of the second inverter 3011 serves as the input end of the second sub-delay circuit 301, and the output end of the last stage of the second inverter 3011 serves as the output end of the second sub-delay circuit 301. The delay time of the second inverter 3011 is independent of temperature and transistor process angle.

[0083] Here, the delay time of the second inverter is independent of temperature and transistor process angle, that is, the process angle type of the transistors in the second inverter and high temperature and low temperature will not affect the delay time of the second inverter.

[0084] At high temperature and when the process corner of the transistor is FF, by selecting different second sub-delay circuits, the second delay circuit can delay the first clock signal by 30ps, 60ps, or 120ps; at low temperature and when the process corner of the transistor is SS, by selecting different second sub-delay circuits, the second delay circuit can also delay the first clock signal by 30ps, 60ps, or 120ps.

[0085] refer to Figure 8 The second inverter 3011 includes a second P-type transistor P2 and a second N-type transistor N2, the source of the second P-type transistor P2 receives the second power supply VregA, the gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are the input terminals of the second inverter 3011, the drain of the second P-type transistor P2 and the drain of the second N-type transistor N2 are the output terminals of the second inverter 3011, the source of the second N-type transistor N2 is grounded, and the second power supply VregA is independent of temperature and transistor process angle.

[0086] Here, the voltage value of the second power supply can be a larger value, so that the delay time of the transistor is consistent under different process angles and temperatures, so that the delay time of the second delay circuit is not affected by temperature and process angle. In some embodiments, the voltage of the second power supply VregA is 1.2 volts.

[0087] The above embodiments illustrate the composition of the oscillating circuit. In practice, a variety of basic electrical components can be combined to form a specific oscillating circuit. The following is a specific structure of an exemplary oscillating circuit, but this does not constitute a limitation to the embodiments of the present disclosure. Figure 9 , the oscillation circuit in the embodiment of the present disclosure is described in detail by taking the example that the first delay circuit includes three first sub-delay circuits and the second delay circuit includes three second sub-delay circuits.

[0088] refer to Figure 9The first first sub-delay circuit in the oscillation circuit 100 illustratively includes a first NAND gate circuit 221 and six first inverters 2011, the second first sub-delay circuit illustratively includes a first NAND gate circuit 221 and four first inverters 2011, and the third first sub-delay circuit illustratively includes a first NAND gate circuit 221 and two first inverters 2011. One input end of each of the three first NAND gate circuits 221 is used to receive the first clock signal Clk_in, and the other input ends of the three first NAND gate circuits 221 respectively receive the three first selection sub-signals in the first selection signal Code1<2:0>, namely Code1<2:0>. <0> 、Code1 <1> and Code1 <2> The three first NAND gate circuits 221 respectively perform a NAND operation on the first clock signal Clk_in and the three first selector sub-signals, and output the NAND operation results to the input terminals of the corresponding cascaded first inverters 2011. The cascaded first inverters 2011 perform a NAND operation on the NAND operation results to obtain three NAND operation results. The second NAND gate circuit 203 performs a NAND operation on the three NAND operation results to obtain the output signal Clk_out1 of the second NAND gate circuit 203.

[0089] Similarly, the first second sub-delay circuit in the oscillation circuit 100 illustratively includes a third NAND gate circuit 321 and six second inverters 3011, the second second sub-delay circuit illustratively includes a third NAND gate circuit 321 and four second inverters 3011, and the third second sub-delay circuit illustratively includes a third NAND gate circuit 321 and two second inverters 3011. One input end of each of the three third NAND gate circuits 321 is used to receive the first clock signal Clk_in, and the other input ends of the three third NAND gate circuits 321 respectively receive the three second selection sub-signals in the second selection signal Code2<2:0>, namely Code2<2:0>. <0> 、Code2 <1> and Code2 <2> The three third NAND gate circuits 321 perform NAND operations on the first clock signal Clk_in and the three second selector signals, respectively, and output the NAND operation results to the input terminals of the corresponding cascaded second inverters 3011. The cascaded second inverters 3011 perform a NAND operation on the NAND operation results to obtain three NAND operation results. The fourth NAND gate circuit 303 performs a NAND operation on the three NAND operation results to obtain the output signal Clk_out2 of the fourth NAND gate circuit 303.

[0090] The fifth NAND gate circuit 50 performs a NAND operation on the output signal Clk_out1 of the second NAND gate circuit 203 and the output signal Clk_out2 of the fourth NAND gate circuit 303 to obtain a first output signal Clk_out.

[0091] In the case where the first sub-delay circuit in the first delay circuit (i.e., Code1<2:0> is 001, Code2<2:0> is 000, and it is assumed that the delay time of the first sub-delay circuit is 60ps) is selected to delay the first clock signal Clk_in through the test mode and the first selection signal, the first first NAND gate circuit 221 delays the first clock signal and Code1 <0> =1 to perform NAND operation, the output of the first first NAND gate circuit 221 is 0; the second first NAND gate circuit 221 performs NAND operation on the first clock signal and Code1 <1> =0, and the output of the second first NAND gate circuit 221 is 1; the third first NAND gate circuit 221 performs a NAND operation on the first clock signal and Code1. <2> =0, and a NAND operation is performed, and the output of the third first NAND gate circuit 221 is also 1.

[0092] The first inverter of the first cascade delays the output 0 of the first first NAND gate circuit 221, and the output result of the output terminal of the first cascade first inverter is 0; the first inverter of the second cascade operates on the output 1 of the second first NAND gate circuit 221, and the output result of the output terminal of the first inverter of the second cascade is 1. The output result of the output terminal of the first inverter of the third cascade is also 1. In this way, the three input terminals of the second NAND gate circuit 203 are inputted as 011 respectively, and the output signal Clk_out1 of the second NAND gate circuit 203 is 1, which is the inverse of the output result of the first inverter of the first cascade.

[0093] Similarly, for the second delay circuit, the outputs of the first through third third NAND gate circuits 321 are all 1, and the outputs of the first through third cascaded second inverters are all 1. Thus, the inputs to the three input terminals of the fourth NAND gate circuit 303 are 111, respectively. Therefore, the output signal Clk_out2 of the fourth NAND gate circuit 303 is 0. The fifth NAND gate circuit 50 performs a NAND operation on the output signal Clk_out1 of the second NAND gate circuit 203 and the output signal Clk_out2 of the fourth NAND gate circuit 303, resulting in a first output signal Clk_out of 1. Here, the first output signal Clk_out is a signal obtained by delaying the first clock signal Clk_in by 60 ps.

[0094] The present disclosure provides an oscillating circuit, referring to Figure 10 The oscillation circuit 100 includes a first buffer circuit 10 , a first delay circuit 20 , a second delay circuit 30 , a second buffer circuit 40 , a third delay circuit 60 and a fourth delay circuit 70 .

[0095] The first buffer circuit 10 is further configured to transmit the received second clock signal to the third delay circuit 60 or the fourth delay circuit 70 based on the enable signal. The third delay circuit 60 has the same structure as the first delay circuit 20, and the fourth delay circuit 70 has the same structure as the second delay circuit 30.

[0096] The third delay circuit 60 or the fourth delay circuit 70 is used to delay the second clock signal to obtain a second output signal, and transmit the second output signal to the second buffer circuit 40;

[0097] The second buffer circuit 40 is configured to transmit the second output signal as a second clock signal to the first buffer circuit 10 .

[0098] Here, the second clock signal can be a pair of differential clock signals with the first clock signal. During implementation, the first clock signal (or first output signal) or the second clock signal (or second output signal) can be led out and its period tosc can be tested to obtain wck2dqi / wck2dqo.

[0099] During implementation, the first delay circuit and the third delay circuit can be used simultaneously to delay the differential first clock signal and the second clock signal based on the test mode. The delayed first clock signal, i.e., the first output signal, and the delayed second clock signal, i.e., the second output signal, are also a pair of differential clock signals.

[0100] In the embodiment of the present disclosure, the oscillation circuit also includes a third delay circuit and a fourth delay circuit having the same structure as the first delay circuit and the second delay circuit, so that a pair of delayed differential clock signals can be obtained without increasing the design difficulty.

[0101] The present disclosure also provides a memory, referring to Figure 11 The memory 200 includes the oscillator circuit 100 in any of the above embodiments. In the embodiment of the present disclosure, since the oscillator circuit 100 includes a first delay circuit whose delay time varies with temperature and / or transistor process angle and a second delay circuit whose delay time does not vary with temperature and transistor process angle, one of the delay circuits can be selected as needed to delay the first clock signal to obtain a first output signal, thereby reducing the difference between the period tOsc of the first clock signal and wck2dqi / wck2dqo introduced by different test methods, test environments, etc., thereby improving the performance of the oscillator circuit and further improving the performance of the memory.

[0102] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of the units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0103] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0104] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0105] The above are only some implementations of the embodiments of the present disclosure, but the scope of protection of the embodiments of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the embodiments of the present disclosure should be included in the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An oscillation circuit, characterized in that: The oscillation circuit includes: a first buffer circuit, a first delay circuit, a second delay circuit and a second buffer circuit; wherein: The delay time of the first delay circuit varies with temperature and / or transistor process angle, and the delay time of the second delay circuit is independent of temperature and transistor process angle; The first buffer circuit is configured to transmit the received first clock signal to the first delay circuit or the second delay circuit based on an enable signal; The first delay circuit or the second delay circuit is configured to delay the first clock signal to obtain a first output signal, and transmit the first output signal to the second buffer circuit; the second buffer circuit is configured to transmit the first output signal as the first clock signal to the first buffer circuit; The oscillator circuit is configured to: during a test phase, select to use the first delay circuit or the second delay circuit according to different test modes.

2. The oscillation circuit according to claim 1, wherein: The first delay circuit includes: at least one first sub-delay circuit, wherein the delay time of each first sub-delay circuit varies with temperature and / or transistor process angle, and the delay times of different first sub-delay circuits are different; The first selection circuit is coupled between the first buffer circuit and the at least one first sub-delay circuit, and is configured to select one of the first sub-delay circuits to delay the first clock signal according to a first selection signal.

3. The oscillation circuit according to claim 2, wherein: The first selection circuit includes at least one first NAND gate circuit, the first selection signal includes at least one first selection sub-signal, the first input end of each first NAND gate circuit receives the first clock signal, the second input end of each first NAND gate circuit receives one first selection sub-signal, the output end of each first NAND gate circuit is connected to the input end of one first sub-delay circuit, and the number of the first NAND gate circuits and the number of the first selection sub-signals are the same as the number of the first sub-delay circuits.

4. The oscillation circuit according to claim 3, wherein: The first delay circuit includes multiple first sub-delay circuits; the first delay circuit also includes a second NAND gate circuit, multiple input ends of the second NAND gate circuit are respectively connected to the output ends of multiple first sub-delay circuits, and the output end of the second NAND gate circuit is used to output the first output signal.

5. The oscillation circuit according to claim 2, wherein: The first sub-delay circuit includes a cascade of first inverters, wherein the input end of the first inverter of each stage is connected to the output end of the first inverter of the previous stage, the input end of the first inverter of the first stage serves as the input end of the first sub-delay circuit, and the output end of the first inverter of the last stage serves as the output end of the first sub-delay circuit, and the delay time of at least part of the first inverters varies with temperature and / or transistor process angle.

6. The oscillation circuit according to claim 5, wherein: Different first sub-delay circuits have different numbers of first inverters.

7. The oscillation circuit according to claim 5 or 6, characterized in that: The first inverter includes: a first P-type transistor and a first N-type transistor, the source of the first P-type transistor receives a first power supply, the gate of the first P-type transistor and the gate of the first N-type transistor serve as inputs of the first inverter, the drain of the first P-type transistor and the drain of the first N-type transistor serve as outputs of the first inverter, and the source of the first N-type transistor is grounded, wherein the first power supply of at least part of the first inverter is related to temperature and / or the transistor process.

8. The oscillation circuit according to claim 1, wherein: The second delay circuit includes: at least one second sub-delay circuit, the delay time of each second sub-delay circuit is independent of temperature and transistor process angle, and the delay times of different second sub-delay circuits are different; The second selection circuit is coupled between the first buffer circuit and the at least one second sub-delay circuit, and is configured to select one of the second sub-delay circuits to delay the first clock signal according to a second selection signal.

9. The oscillation circuit according to claim 8, wherein: The second selection circuit includes at least one third NAND gate circuit, the second selection signal includes at least one second selection sub-signal, the first input end of each of the third NAND gate circuits receives the first clock signal, the second input end of each of the third NAND gate circuits receives one of the second selection sub-signals, the output end of each of the third NAND gate circuits is connected to the input end of one of the second sub-delay circuits, and the number of the third NAND gate circuits, the number of the second selection sub-signals and the number of the second sub-delay circuits are the same.

10. The oscillation circuit according to claim 9, wherein: The second delay circuit includes multiple second sub-delay circuits; the second delay circuit also includes a fourth NAND gate circuit, multiple input ends of the fourth NAND gate circuit are respectively connected to the output ends of multiple second sub-delay circuits, and the output end of the fourth NAND gate circuit is used to output the first output signal.

11. The oscillation circuit according to claim 8, wherein: The second sub-delay circuit includes cascaded second inverters. The input end of the second inverter of each stage is connected to the output end of the second inverter of the previous stage. The input end of the second inverter of the first stage serves as the input end of the second sub-delay circuit, and the output end of the second inverter of the last stage serves as the output end of the second sub-delay circuit. The delay time of the second inverter is independent of temperature and transistor process angle.

12. The oscillation circuit according to claim 11, wherein: The second inverter includes: a second P-type transistor and a second N-type transistor, the source of the second P-type transistor receives a second power supply, the gate of the second P-type transistor and the gate of the second N-type transistor serve as input terminals of the second inverter, the drain of the second P-type transistor and the drain of the second N-type transistor serve as output terminals of the second inverter, the source of the second N-type transistor is grounded, and the second power supply is independent of temperature and transistor process angle.

13. The oscillation circuit according to claim 12, wherein: The voltage of the second power supply is 1.2V.

14. The oscillation circuit according to claim 1, wherein: The oscillation circuit further includes: a third delay circuit and a fourth delay circuit; wherein: The first buffer circuit is further configured to transmit the received second clock signal to the third delay circuit or the fourth delay circuit based on the enable signal, wherein the third delay circuit has the same structure as the first delay circuit, and the fourth delay circuit has the same structure as the second delay circuit; The third delay circuit or the fourth delay circuit is configured to delay the second clock signal to obtain a second output signal, and transmit the second output signal to the second buffer circuit; The second buffer circuit is configured to transmit the second output signal as the second clock signal to the first buffer circuit.

15. A memory, characterized in that: The oscillator circuit comprises the oscillator circuit according to any one of claims 1 to 14.

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