A readout system, a readout method and an image sensor
By adding a switch-controlled capacitor voltage divider technique to the readout system of a CMOS image sensor, the problem of limited comparator signal reception range is solved, signal processing with a larger dynamic range is achieved, and the signal resolution capability of the image sensor is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-09
- Publication Date
- 2026-03-20
AI Technical Summary
In existing column-level readout systems of CMOS image sensors, the comparator signal receiving range is limited, making it difficult to effectively convert large-range pixel output signals, resulting in a limited dynamic range.
In the readout system of an image sensor, three switches are added to control the coupling capacitors of the cascaded comparators. The pixel output signal is scaled to the range that the comparators can accept through voltage divider technology, and the readout noise remains unchanged during the analog-to-digital conversion process.
It enables effective resolution of signals with a larger pixel output range, expands the dynamic range of the image sensor, avoids proportional amplification of readout noise, and improves signal processing capabilities.
Smart Images
Figure CN115550582B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuit design, and in particular to a readout system of an image sensor, a readout method and an image sensor. BACKGROUND
[0002] At present, CMOS image sensors (CIS) have been widely applied to imaging fields such as video, monitoring, industrial manufacturing, automobile and household appliances. With the increasing requirements of applications, the requirements for the dynamic range of CIS are also higher and higher, which requires improving the process to improve the photosensitive performance of pixels. The most direct method is to expand the pixel output range, but the comparator signal receiving range of the mainstream column-level readout system is limited. The mainstream readout system of CIS is a readout system mainly based on a single-slope analog-to-digital converter (SS-ADC). In order to effectively convert the large-range pixel output signal, the readout system of the SS-ADC needs to be improved to meet the requirements.
[0003] Therefore, the present application provides a new image sensor readout scheme to improve the above problems. SUMMARY
[0004] The embodiment of the present application provides a readout system, a readout method and an image sensor of an image sensor, which are used to effectively distinguish signals of a larger pixel output range, so as to achieve the purpose of expanding the dynamic range of the image sensor.
[0005] In a first aspect, the present application provides a readout system of an image sensor, which is applied to an image sensor, and includes: a slope circuit, which is used to generate a slope signal; a timing controller, which is used to control the slope circuit to generate a slope signal with a corresponding voltage or a corresponding number of times; a comparator, a negative phase input end of the comparator is connected to an output end of a signal adjustment module, a positive phase input end of the comparator is connected to an output end of a first capacitor, an input end of the first capacitor inputs the slope signal, and an output end of the first capacitor outputs a positive phase input signal IP; the signal adjustment module includes a second capacitor and a third capacitor, when an output signal PIX_OUT of a pixel unit of the image sensor is greater than a set threshold value, the second capacitor and the third capacitor are controlled to be connected in series, and the signal adjustment module is used to output a negative phase input signal IN after scaling the output signal PIX_OUT of the pixel unit; an output end of the comparator is connected to an input end of a counter, which is used to compare the size between the positive phase input signal IP and the negative phase input signal IN to obtain a comparison result; and the counter is used to count according to the comparison result of the comparator and output a pixel quantization value.
[0006] In a possible implementation, when the output signal PIX OUT of the pixel unit is less than or equal to the set threshold value, the second capacitor and the third capacitor are controlled to be connected in parallel, and the capacitance value of the second capacitor and the third capacitor connected in parallel is equal to the capacitance value of the first capacitor, and the signal adjustment module is configured to output the negative-phase input signal IN after voltage division.
[0007] In another possible implementation, the ratio of the capacitance values between the second capacitor and the third capacitor is a positive number less than 1.
[0008] In other possible implementations, the signal adjustment module includes a first branch and a second branch, the first branch includes the first switch and the second capacitor connected to the first switch, and the second branch includes the second switch, the third switch, and the third capacitor connected to the second switch and the third switch, where the third switch is grounded.
[0009] In a possible implementation, when the output signal PIX OUT of the pixel unit is greater than the set threshold value, the second capacitor and the third capacitor are controlled to be connected in series, including:
[0010] When the output signal PIX OUT of the pixel unit is greater than the set threshold value, the first switch and the third switch are controlled to be turned on, and the second switch is controlled to be turned off, so that the second capacitor and the third capacitor are connected in series.
[0011] In a possible implementation, when the output signal PIX OUT of the pixel unit is less than or equal to the set threshold value, the second capacitor and the third capacitor are controlled to be connected in parallel, including:
[0012] When the output signal PIX OUT of the pixel unit is less than or equal to the set threshold value, the first switch and the second switch are controlled to be turned on, and the third switch is controlled to be turned off, so that the second capacitor and the third capacitor are connected in parallel.
[0013] In a second aspect, the present application further provides a readout method of an image sensor, applied to an image sensor, obtaining an output signal PIX OUT of a pixel unit of the image sensor;
[0014] generating a corresponding ramp signal;
[0015] When the output signal PIX OUT of the pixel unit is greater than the set threshold value, the negative-phase input signal IN is obtained by scaling the output signal PIX OUT of the pixel unit; and when the output signal PIX OUT of the pixel unit is less than or equal to the set threshold value, the negative-phase input signal IN is obtained by voltage division of the output signal PIX OUT of the pixel unit.
[0016] Comparing the relative size between the positive phase input signal IP and the negative phase input signal IN of the divided voltage of the ramp signal;
[0017] Counting according to the comparison result of the comparator, and outputting a pixel quantization value.
[0018] In a third aspect, the present application further provides an image sensor, comprising a pixel array, an analog-digital conversion unit, a reference signal generator, a timing controller, a decoding driver and an output signal processor, wherein the timing controller is configured to control the image sensor to perform the method provided in any of the embodiments of the first aspect.
[0019] The image sensor readout system and the image sensor readout method provided by the present application have the following beneficial effects: by improving the traditional SS-ADC, three switches are added in the commonly used CIS comparator; when the output signal PIX_OUT of the pixel unit of the image sensor is greater than a set threshold, the coupling capacitor of the comparator is controlled to divide voltage, so as to realize a gain less than 1 times; in this way, the pixel output PIX_OUT can be scaled to the range that can be received by the comparator, and then converted. In this process, the ADC can process the full-range pixel output signal, and the readout noise is not amplified in proportion, so that it can effectively distinguish the signal of a larger pixel output range, so as to realize the purpose of expanding the dynamic range of the image sensor. BRIEF DESCRIPTION OF DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.
[0021] Figure 1 A circuit structure schematic diagram of a CIS standard four-tube pixel unit provided by the prior art;
[0022] Figure 2 A timing control method flowchart schematic diagram of a four-tube pixel unit provided by the prior art;
[0023] Figure 3 A schematic diagram of an image sensor provided by the prior art;
[0024] Figure 4 A CIS readout system operation timing schematic diagram provided by the prior art;
[0025] Figure 5 A CIS readout system schematic diagram provided by the prior art;
[0026] Figure 6A circuit structure schematic diagram of a comparator provided for the prior art;
[0027] Figure 7 A schematic diagram of an image sensor readout system provided for an embodiment of the present application;
[0028] Figure 8 A flowchart of an image sensor readout method provided for an embodiment of the present application. DETAILED DESCRIPTION
[0029] Figure 1 is a four-pixel unit circuit structure of the CIS standard, which is commonly applied to a row exposure CIS, and is composed of a photodiode PD, a charge transfer tube Mtg, a reset tube Mrst, an amplification tube Msf, and a selection tube Msel. The photodiode PD is photosensitive and generates photoelectrons proportional to the intensity of light. The Mtg functions to transfer the photoelectrons in the photodiode PD, and when the transmission signal TX is a high voltage, the charge transfer tube Mtg is turned on to transfer the photoelectrons in the photodiode PD to the floating diffusion region FD. The Mrst functions to reset the pixel unit when the reset signal RX is a high voltage. The Msf is an amplification tube, and when the selection signal SEL is a high voltage, the selection tube Msel is turned on to form a path with the current source to the ground, at which time the Msf is essentially a source follower that follows the change in the potential of the floating diffusion region FD and is ultimately output by PIX_OUT.
[0030] Figure 2For the operation timing of the four-tube pixel unit, it is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the reset stage, both the transmission signal TX and the reset signal RX are high, both the charge transfer tube Mtg and the reset tube Mrst are turned on, the pixel unit is reset and its potential is pulled up to the power supply voltage VDD. Then, both the transmission signal TX and the reset signal RX are low, entering the exposure (Exp) stage, the photodiode PD is photosensitive and accumulates electrons. In the signal reading (Read) stage, the selection signal SEL is high, the reset signal RX is first high to reset the pixel unit, and then the reset signal RX is pulled low, and the transmission signal TX remains low, at this time the amplifier tube Msf is controlled by the pixel unit potential and outputs the reset signal VRST through PIX_OUT. Then, the transmission signal TX is switched to high, transferring the electrons on the photodiode PD to the floating diffusion region FD, at this time the amplifier tube Msf is controlled by the floating diffusion region FD potential and outputs the integration signal VSIG through PIX_OUT. The reset signal VRST and the integration signal VSIG are converted to digital quantities by the subsequent analog-to-digital conversion unit (Analog-to-Digital Converter, ADC) circuit and subjected to subtraction operation, obtaining the digital quantity corresponding to the actual photoelectrons on the photodiode PD. If the bit width of the analog-to-digital conversion unit is 12 bits and the reference voltage range of the analog-to-digital conversion unit is VREF, the final output is DOUT=(VRST-VSIG)×2 12 / VREF.
[0031] Figure 3 The structure diagram of a typical CIS readout system includes a pixel array, an analog-to-digital conversion unit (Analog-to-Digital Converter, ADC), a ramp generator, a timing controller, a decoding driver, and an output signal processor. The pixel array is composed of a plurality of Figure 3 The pixel array is divided into two directions, the first direction is defined as the row direction, and the second direction is defined as the column direction. The pixel array can be read out in a row-by-row manner, and the specific order is ROW(0), ROW(1), …, ROW(n-1), ROW(n). Each column of the pixel array has an output bus, which is PIX_OUT(0), PIX_OUT(1), …, PIX_OUT(N-1), and PIX_OUT(N) respectively. The PIX_OUT output is connected to the ADC. Each column of pixel output corresponds to an ADC. The ADC is composed of a comparator and a counter. The comparator compares the pixel output with the ramp signal RAMP, and the comparison result determines the size of the counter value. The ADC converts the above-mentioned VRST-VSIG difference into a digital quantity and transmits it to the output signal processor for further processing.
[0032] Figure 4 for Figure 3 The CIS readout system currently corresponds to the operating timing sequence, that is... Figure 2 The timing diagram shows the read phase. Upon entering the read phase, the strobe signal SEL is pulled high, and the reset signal RX is also high, resetting the pixel unit. RST_CM, the comparator reset control signal, is also pulled high, causing all ADC comparators in the CIS to enter the reset state. Afterwards, the reset signal RX and the comparator reset control signal RST_CM switch from high to low, and the ADC enters normal operation. The ADC's operation includes two parts: comparison and counting. First, when the ramp signal RAMP begins to fall, the counter CNT starts counting until the comparator signal flips from low to high, at which point the counter CNT stops counting and stores the current count value. However, to complete the analog-to-digital conversion of the pixel signal, the ADC needs to perform the above operation twice. The ramp signal, as the ADC reference, is generated twice. The first ramp phase (i.e....) Figure 4 During the "VR" phase, the ADC will determine and store the reset potential VRST, and the ADC counter CNT will count and store the corresponding count value CN1 within time t1; the second ramp phase (i.e. Figure 4 During the "VS" phase, the ADC will determine and store the reset potential VSIG, and the ADC counter CNT will count and store the count value CN2 corresponding to the time period t2. Finally, the counter CNT will output the count difference ΔCN = CN2 - CN1, which corresponds to the difference between VSIG and VRST.
[0033] Figure 5 In the current CIS readout system, the pixel output is determined by the tail current IS to determine the pixel unit output signal PIX_OUT. The pixel unit output signal PIX_OUT and the ramp reference signal RAMP are respectively connected to two coupling capacitors before the comparator input. According to Figure 4 As shown in the timing diagram, after the comparator completes its reset, the input terminals IP and IN will change according to the ramp signal RAMP and the pixel unit output signal PIX_OUT, respectively, completing the comparison process. The output CM_OUT is used to control the counter's counting. Figure 4 As shown, the pixel unit output signal PIX_OUT with normal amplitude intersects with the ramp signal RAMP in both the "VR" and "VS" stages and can ultimately be correctly converted into the corresponding digital quantity. However, when the signal amplitude is large, they only intersect in the "VR" stage, and there is no intersection in the "VS" stage. This indicates that the signal is out of range, and the ADC counter outputs a full value. In other words, any large-amplitude signal exceeding the ADC's quantization range cannot be correctly converted and distinguished.
[0034] CIS image dynamic range
[0035] wherein FWC is the full well capacity, is the pixel read noise, is the ADC read noise. FWC·µ=Vswing, wherein µ is the conversion gain and Vswing is the pixel output voltage amplitude.
[0036] When FWC is large, that is, the number of photoelectrons stored in the photodiode is large, Vswing will be large. At this time, the read noise of the pixel and the ADC will not increase with the increase of FWC. If all the electrons corresponding to the large FWC can be converted, that is, the large amplitude Vswing can be effectively converted, the effective dynamic range can be improved, and the corresponding Figure 4 The timing needs to convert the over-range signal.
[0037] As Figure 6 shown in the comparator circuit commonly used in the SS-ADC, the circuit has the advantages of simple structure and can provide large gain to realize fast comparison. However, since it is an NMOS input, the input potential needs to satisfy VIN>Vthn+VDS3, wherein Vthn is the threshold voltage of the input pair NMOS, and VDS3 is the saturation drain-source voltage of N3. Generally, Vthn=0.5~0.7V and VDS3=0.3V, so VIN>0.8~1V can make the input tube conduct, but at this time, the input tubes N1 and N2 are in weak conduction, the response speed of the comparator is slow, and the linearity of the entire ADC is poor, so the input signal is generally ensured to be in the range of VIN>1.2V. The comparator will be reset once before working to determine its static working point, at this time, the gate potential of the input tube and the gate potential of N4 are the same, about 2.2V, that is, after the comparator enters the working state, it will start to drop from 2.2V, according to the above analysis, the lowest can be 1.2V, so the input voltage amplitude range that can ensure the effective working of the comparator is about 1V. The part of the amplitude range of the pixel unit output signal PIX_OUT that exceeds 1V cannot be effectively distinguished.
[0038] In order to effectively distinguish this part of the over-range signal, the present application improves the existing readout system. In the present application, the coupling capacitor cascaded at the positive input end of the comparator includes a first capacitor C1, the input end of the first capacitor C1 inputs a ramp signal, and the output end of the first capacitor C1 outputs a positive input signal IP. The coupling capacitor cascaded at the negative input end of the comparator and the three switches form two branches, which can be simply referred to as a signal adjustment module. The coupling capacitor cascaded at the negative input end of the comparator at least includes a second capacitor C2 and a third capacitor C3, and the capacitance value of the parallel connection of the second capacitor C2 and the third capacitor C3 is equal to the capacitance value of the first capacitor C1. Specifically, as Figure 7As shown, the first branch includes the first switch K1 and the second capacitor C2, the second branch includes the second switch K2, the third switch K3 and the third capacitor C3. As shown in the figure, the first end of the first switch K1 is connected to the pixel unit output signal PIX OUT, and the second end of the first switch K1 is connected to the second capacitor C2; the first end of the second switch K2 is connected to the pixel unit output signal PIX OUT, the second end of the second switch K2 is connected to the first end of the third capacitor C3, and the first end of the third switch K3 is connected to the first end of the third capacitor C3, and the second end of the third switch K3 is grounded.
[0039] Based on the improved readout system, when the output signal PIX OUT of the pixel unit of the image sensor is greater than a set threshold value, the first switch and the third switch are controlled to be turned on, and the second switch is controlled to be turned off, so that the second capacitor and the third capacitor are connected in series, and the signal adjustment module is configured to output the negative-phase input signal IN after scaling the output signal PIX OUT of the pixel unit. When the output signal PIX OUT of the pixel unit is less than or equal to the set threshold value, the first switch and the second switch are controlled to be turned on, and the third switch is controlled to be turned off, so that the second capacitor and the third capacitor are connected in parallel, and the capacitance value of the second capacitor and the third capacitor connected in parallel is equal to the capacitance value of the first capacitor, which is equivalent to the signal adjustment module configured to output the negative-phase input signal IN after voltage division by the first capacitor.
[0040] That is, when the pixel unit output signal is an out-of-range large signal, the readout system determines that the ADC output in a certain direction reaches the full amplitude, and then switches the working mode of the image sensor to a large signal mode. In this mode, the first switch K1 and the third switch K3 are turned on, the second switch K2 is turned off, the pixel unit output signal PIX OUT is connected to the signal adjustment module in which the second capacitor C2 and the third capacitor C3 are connected in series, and the potential of the negative-phase input signal IN is equal to the product of the pixel unit output signal PIX OUT and C2 / C3. C2 / C3 is set to q, and q is set to a positive number less than 1. Even if Vswing exceeds the range, as long as q times Vswing is within the comparator input voltage range, the pixel output signal is multiplied by a gain less than 1. Assuming that Vswing=2V and the comparator input voltage range is 1V, as long as C2=C3=C1 / 2, the signal amplitude at the negative-phase input signal IN end is Vswing / 2=1V. The readout noise of the analog-to-digital conversion unit ADC is amplified by 2 times at the negative-phase input signal input end, but the pixel readout noise remains unchanged. According to the formula of the dynamic range, Vswing is expanded by 2 times, and FWC is also expanded by 2 times. The ADC readout noise =4
[0041] ; because the pixel readout noise accounts for about 70%, and the ADC generally accounts for 30%, so there is =0.7 ; ;
[0042] In the normal mode where the output signal PIX_OUT of the pixel unit is less than or equal to the set threshold value, when Vswing=1V, ;
[0043] In the large signal mode, when Vswing=2V, ;
[0044] If DR=70dB, then =75dB.
[0045] It can be seen that the readout system provided by the present application can effectively improve the dynamic range, and through the improvement of the traditional SS-ADC, three switches are added in the commonly used CIS comparator, when the output signal PIX_OUT of the pixel unit of the image sensor is greater than the set threshold value, the coupling capacitors of the comparator are controlled to be divided, and the gain less than 1 times is realized, so that the pixel output PIX_OUT can be scaled to the range that can be received by the comparator, and then converted. Since in this process, the ADC can process the full range pixel output signal, and the readout noise is not amplified in proportion, it can effectively distinguish the signal of a larger pixel output range, and can realize the purpose of expanding the dynamic range of the image sensor.
[0046] As shown in the accompanying drawings, Figure 8 The present application further provides an image sensor readout method, which can be applied to the above-mentioned image sensor, and can specifically include the following steps:
[0047] S801, the readout system acquires the output signal PIX_OUT of the pixel unit of the image sensor.
[0048] S802, the ramp generator generates a corresponding ramp signal, and inputs the ramp signal to the first capacitor, and the first capacitor outputs the divided voltage positive input signal IP to the positive input end of the comparator;
[0049] S803, when the output signal PIX_OUT of the pixel unit is greater than the set threshold value, the signal adjustment module scales the output signal PIX_OUT of the pixel unit to obtain the negative input signal IN; when the output signal PIX_OUT of the pixel unit is less than or equal to the set threshold value, the signal adjustment module divides the output signal PIX_OUT of the pixel unit to obtain the negative input signal IN, and the signal adjustment module outputs the negative input signal IN to the negative input end of the comparator.
[0050] S804, the comparator compares the relative size between the positive phase input signal IP and the negative phase input signal IN of the divided voltage of the ramp signal, and obtains a comparison result.
[0051] S805, the counter counts according to the comparison result of the comparator, and outputs a pixel quantization value.
[0052] In addition, the application further provides an image sensor comprising the improved readout system, which can execute the readout method to obtain an image signal.
[0053] The above-mentioned preferred embodiments of the application are not intended to limit the patent protection scope of the application, and any equivalent structural changes made according to the content of the specification and drawings of the application shall be included in the protection scope of the application.
[0054] The above description of the disclosed embodiments enables those skilled in the art to carry out or use the application.
[0055] Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Accordingly, the application is not to be limited to the embodiments shown herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.
Claims
1. A readout system for an image sensor, applied to the image sensor, characterized in that, The readout system includes: A ramp circuit is used to generate a ramp signal; A timing controller is used to control the ramp circuit to generate a ramp signal of a corresponding voltage or a corresponding number of times; The comparator has its negative input connected to the output of the signal adjustment module and its positive input connected to the output of a first capacitor. The input of the first capacitor is a ramp signal, and the output of the first capacitor is a positive input signal IP. The signal adjustment module is used to scale the output signal PIX_OUT of the pixel unit and output a negative phase input signal IN; the signal adjustment module includes a first branch and a second branch, the first branch includes a first switch and a second capacitor connected to the first switch, the second branch includes a second switch, a third switch, and a third capacitor connected to both the second switch and the third switch, wherein the third switch is grounded; The output of the comparator is connected to the input of the counter, and is used to compare the magnitudes of the positive input signal IP and the negative input signal IN to obtain a comparison result; A counter is used to count based on the comparison result of the comparator and output pixel quantization values.
2. The readout system according to claim 1, characterized in that, When the output signal PIX_OUT of the pixel unit is greater than a set threshold, the second capacitor and the third capacitor are connected in series.
3. The readout system according to claim 2, characterized in that, Also includes: When the output signal PIX_OUT of the pixel unit is less than or equal to the set threshold, the second capacitor and the third capacitor are connected in parallel, and the capacitance value of the second capacitor and the third capacitor after parallel connection is equal to the capacitance value of the first capacitor. The signal adjustment module is used to output the negative phase input signal IN after voltage division.
4. The readout system according to claim 2, characterized in that, The ratio of the capacitance values of the second capacitor and the third capacitor is a positive number less than 1.
5. The readout system according to claim 2, characterized in that, When the output signal PIX_OUT of the pixel unit is greater than a set threshold, the second capacitor and the third capacitor are connected in series, including: When the output signal PIX_OUT of the pixel unit is greater than a set threshold, the first switch and the third switch are turned on, and the second switch is turned off, so that the second capacitor and the third capacitor are connected in series.
6. The readout system according to claim 3, characterized in that, When the output signal PIX_OUT of the pixel unit is less than or equal to the set threshold, the second capacitor and the third capacitor are controlled to be connected in parallel, including: When the output signal PIX_OUT of the pixel unit is less than or equal to the set threshold, the first switch and the second switch are turned on, and the third switch is turned off, so that the second capacitor and the third capacitor are connected in parallel.
7. A readout method for an image sensor, applied to the readout system of the image sensor as described in any one of claims 1 to 6, characterized in that, include: Obtain the pixel unit output signal PIX_OUT of the image sensor; The corresponding ramp signal is generated, and the ramp signal is divided by the first capacitor and output as a non-inverting input signal IP to the non-inverting input terminal of the comparator. When the output signal PIX_OUT of the pixel unit is greater than the set threshold, the output signal PIX_OUT of the pixel unit is scaled to obtain the negative phase input signal IN; when the output signal PIX_OUT of the pixel unit is less than or equal to the set threshold, the output signal PIX_OUT of the pixel unit is divided to obtain the negative phase input signal IN. Compare the relative magnitudes of the positive phase input signal IP and the negative phase input signal IN after the ramp signal is divided by voltage; The pixel quantization value is output based on the comparison result of the comparator.
8. An image sensor, characterized in that, It includes a pixel array, an analog-to-digital converter, a reference signal generator, a timing controller, a decoder driver, and an output signal processor, wherein the timing controller is used to control the image sensor to perform the method described in claim 7.
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