Chip fine line fan-out packaging structure and manufacturing method thereof

Abstract

This application provides a fine-line fan-out chip packaging structure and its fabrication method, relating to the field of chip technology. The fine-line fan-out chip packaging structure provided in this application, and the chip fine-line fan-out chip packaging structure fabricated by the method provided in this application, include an inter-chip fine winding layer and a packaging winding layer. The linewidth and spacing of the inter-chip fine winding layer are smaller than the linewidth and spacing of the packaging winding layer; therefore, users can choose to use different packaging winding layers according to actual needs. Thus, the fine-line fan-out chip packaging structure provided in this application and the packaging structure fabricated by the method provided in this application can meet the user's needs in more scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and in particular, relates to a chip fine line fan-out packaging structure and a manufacturing method thereof. BACKGROUND

[0002] The development of 5G mobile internet, artificial intelligence, Internet of Things, automatic driving, high-performance computing and other technologies requires the wide application of semiconductor devices such as integrated circuits. And according to different scenes and requirements, there are different requirements for the transmission rate, power consumption and other indicators of the circuit. However, the existing chip fine line fan-out packaging structure cannot meet the multiple use requirements of users. SUMMARY

[0003] The present application provides a chip fine line fan-out packaging structure and a manufacturing method thereof, and the purposes at least include improving the problem that the existing chip fine line fan-out packaging structure cannot meet the multiple requirements of users.

[0004] Embodiments of the present application can be implemented as follows:

[0005] In a first aspect, the present application provides a chip fine line fan-out packaging structure, which includes a plurality of chips and a plurality of wire layers,

[0006] The chip includes a device and a pin, and the pin includes a high-density inter-chip interconnection pin and a low-density chip interconnection pin,

[0007] The plurality of wire layers includes an inter-chip fine wire layer and a packaging wire layer, and the line width and distance of the inter-chip fine wire layer are smaller than those of the packaging wire layer,

[0008] The inter-chip fine wire layer is connected to the chip through the high-density inter-chip pin,

[0009] The manufacturing of the fine line fan-out packaging structure includes:

[0010] A first insulating layer is laid on a temporary support material, and an inter-chip fine wire layer is grown on the first insulating layer,

[0011] An adhesive material is used to complete the pin alignment and bonding of the plurality of chips and the inter-chip fine wire layer, and the chips are molded, and then the temporary support material is removed,

[0012] A first interconnection hole is prepared on the inter-chip fine wire layer, and a conductive material is arranged in the first interconnection hole to realize the electrical connection between the chip and the inter-chip fine wire layer,

[0013] At least one packaging wire layer is made on the first insulating layer, and an insulating layer is arranged between each packaging wire layer, and the packaging wire layer is connected to the chip or other wire layer through an interconnection hole filled with a conductive material.

[0014] Optionally, an adhesive layer is formed by an insulating adhesive material or a anisotropic conductive material to adhere the pin side of the chip to the nearest fine inter-chip wiring layer, and the chip pins and the fine inter-chip wiring layer are accurately aligned.

[0015] Optionally, the first interconnection hole penetrates through the first insulating layer, the fine inter-chip wiring layer and the adhesive layer to the high-density inter-chip pins of the chip, and the first interconnection hole is filled with conductive material; the fine inter-chip wiring layer realizes electrical interconnection between different chips through the conductive material filled in the first interconnection hole.

[0016] Optionally, the insulating layer includes a second insulating layer, the interconnection hole includes a second interconnection hole, and the packaging wiring layer includes a first packaging wiring layer; the second insulating layer covers the first insulating layer and the first interconnection hole, and the first packaging wiring layer is arranged on the second insulating layer; the second interconnection hole penetrates through the first insulating layer and the second insulating layer to the fine inter-chip wiring layer, and / or penetrates through the second insulating layer, the first insulating layer, the fine inter-chip wiring layer and the adhesive layer to the low-density inter-chip interconnection pins; only the sidewall of the second interconnection hole is coated with conductive material to realize electrical interconnection between the first packaging wiring layer and the fine inter-chip wiring layer and / or the low-density inter-chip interconnection pins.

[0017] Optionally, the insulating layer further includes a third insulating layer, the interconnection hole further includes a third interconnection hole, and the packaging wiring layer further includes a second packaging wiring layer; the third insulating layer covers the first packaging wiring layer, and the material of the third insulating layer fills the second interconnection hole; the third interconnection hole penetrates through the third insulating layer, the second packaging wiring layer is arranged on the third insulating layer, and the second packaging wiring layer is electrically connected to the first packaging wiring layer through the conductive material in the third interconnection hole.

[0018] Optionally, the line width and line spacing of the packaging wiring layer are greater than those of the fine inter-chip wiring layer; the line width and line spacing of the fine inter-chip wiring layer are 0.5-2 microns, and the line width and line spacing of the first packaging wiring layer are 2-5 microns.

[0019] Optionally, the line width and line spacing of all the wiring layers including the fine inter-chip wiring layer and the packaging wiring layer gradually increase in the direction away from the chip, and the line width of the packaging wiring layer other than the first packaging wiring layer is greater than 5 microns.

[0020] Optionally, the material of the first insulating layer and the insulating layer between the packaging wiring layers includes at least one of polyimide (Polyimide), benzocyclobutene (BCB), parylene, industrial liquid crystal polymer (LCP), epoxy resin, silicon oxide, silicon nitride, ceramic, aluminum oxide and glass.

[0021] Optionally, the conductive material in the first interconnection hole, the second interconnection hole and the third interconnection hole is at least one of copper, aluminum, tungsten, conductive paste, tin-silver alloy, tin-silver-copper alloy and gold-tin alloy.

[0022] Secondly, this application provides a method for fabricating a chip fine-line fan-out package structure, including:

[0023] A first insulating layer, a fine inter-chip winding layer, and an adhesive layer are sequentially fabricated on one side of the temporary support material.

[0024] Multiple chips are mounted on the side of the adhesive layer away from the fine inter-chip winding layer. The chip pins include high-density inter-chip interconnect pins and low-density inter-chip interconnect pins. The chip pins are precisely aligned with the fine inter-chip winding layer.

[0025] Multiple chips are encapsulated with encapsulating material and covered with an adhesive layer;

[0026] Remove temporary support materials;

[0027] A first interconnect hole is formed on the first insulating layer. The first interconnect hole penetrates the first insulating layer, the inter-chip fine winding layer and the adhesive layer and exposes the high-density inter-chip pins of the chip. The first interconnect hole is filled with conductive material so that the inter-chip fine winding layer is electrically connected to the high-density inter-chip pins of the chip.

[0028] A second insulating layer is coated on the first insulating layer, covering the first insulating layer and the first interconnect. A first packaging winding layer is formed on the second insulating layer. A second interconnect is formed, penetrating the first packaging winding layer, the second insulating layer, the first insulating layer, and the inter-chip fine winding layer, exposing low-density chip interconnect pins, and / or penetrating the first packaging winding layer, the second insulating layer, and the first insulating layer to expose the inter-chip fine winding layer. A conductive material is filled in the second interconnect, and the low-density chip interconnect pins are electrically connected to the inter-chip fine winding layer and the first packaging winding layer through the conductive material in the second interconnect.

[0029] At least one insulating layer and at least one packaging winding layer are alternately prepared in the direction away from the chip in the first packaging winding layer. Interconnect holes are made on each insulating layer and the interconnect holes are filled with conductive material. Electrical connections are formed between each packaging winding layer through the conductive material in the interconnect holes. The line width and line spacing of the fine winding layer between the chips are smaller than the line width and line spacing of each packaging winding layer.

[0030] The package winding layer furthest from the chip has pin pads, a solder mask is covered on the package winding layer furthest from the chip, at least part of the solder mask covering the pin pads is removed, and solder balls are planted on the pin pads.

[0031] Optionally, the linewidth and spacing of each winding layer, including the inter-chip fine winding layer, the first package winding layer, and other package winding layers, gradually increase in the direction away from the chip.

[0032] Optionally, the conductive material within the second interconnect hole electrically connects the low-density chip interconnect pins to the first package winding layer, and / or electrically connects the inter-chip fine winding layer to the first package winding layer.

[0033] Optionally, conductive material is coated on the sidewalls and bottom of the second interconnect hole, and the remaining space inside the second interconnect hole is filled with the material of the third insulating layer, or the second interconnect hole is filled with conductive material.

[0034] Optionally, conductive material may be filled into each interconnect hole, including:

[0035] Seed metal layers are deposited by magnetron sputtering or electroless plating on the sidewalls and bottom of the interconnect holes, and conductive material is filled into the interconnect holes using an electroplating process; or conductive material is filled into the interconnect holes by screen / stencil printing.

[0036] Optionally, interconnects can be formed by laser drilling, or by photolithography and dry etching.

[0037] The beneficial effects of the embodiments of this application include, for example:

[0038] The chip fine-line fan-out packaging structure provided in this application, and the chip fine-line fan-out packaging structure fabricated by the manufacturing method provided in this application, have winding layers including inter-chip fine winding layers and packaging winding layers, which have different line widths and spacings. Therefore, users can choose to use different winding layers according to their actual needs. Thus, the chip fine-line fan-out packaging structure provided in this application and the packaging structure fabricated by the manufacturing method provided in this application can meet users' needs in more scenarios. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a chip fine circuit fan-out packaging structure in one embodiment of this application;

[0041] Figure 2 This is a flowchart of a method for fabricating a chip fine circuit fan-out packaging structure in one embodiment of this application;

[0042] Figures 3 to 15 This is a schematic diagram of the fabrication process of a chip fine circuit fan-out packaging structure in one embodiment of this application.

[0043] Icons: 010 - Chip fine-line fan-out package structure; 100 - Chip; 101 - High-density chip interconnect pins; 102 - Low-density chip interconnect pins; 110 - Encapsulation material; 200 - Adhesive layer; 300 - Chip fine winding layer; 400 - First insulating layer; 410 - First interconnect hole; 500 - Second insulating layer; 510 - Second interconnect hole; 600 - First package winding layer; 700 - Third insulating layer; 710 - Third interconnect hole; 800 - Second package winding layer; 900 - Solder mask; 910 - Solder ball; 020 - Temporary support material. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0046] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0047] In the description of this application, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0048] Furthermore, the terms "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0049] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0050] Figure 1This is a schematic diagram of a chip fine-line fan-out package structure 010 in one embodiment of this application. The chip fine-line fan-out package structure 010 includes a chip 100 and multiple winding layers. The multiple winding layers include an inter-chip fine winding layer 300 and multiple package winding layers. The chip 100 is overlapped with the inter-chip fine winding layer 300 and the multiple package winding layers. The pins of the chip 100 are electrically connected to the inter-chip fine winding layer 300 or at least one package winding layer through electrically connected interconnects. The inter-chip fine winding layer 300 or the package winding layers are all electrically connected to the chip 100 or at least one of the other package winding layers through electrically connected interconnects. The line width and line spacing of the inter-chip fine winding layer 300 and each package winding layer are different. Specifically, the line width and line spacing of the inter-chip fine winding layer 300 are smaller than the line width and line spacing of each package winding layer. The number of chips 100 included in the chip fine-line fan-out package structure 010 can be determined as needed, such as the two shown in the figure. It can also include only one chip 100, which is connected to other components through the inter-chip fine winding layer 300 or the package winding layer. Alternatively, the chip fine-line fan-out package structure 010 can include three or more chips 100. It should be understood that in the embodiments of this application, different line widths and spacings refer to different line widths of different winding layers and different line spacings. For example... Figure 1 As shown, an embodiment of this application provides a chip fine circuit fan-out package structure 010 including a chip 100, an adhesive layer 200, an inter-chip fine winding layer 300, a first insulating layer 400, a second insulating layer 500, a first package winding layer 600, a third insulating layer 700, a second package winding layer 800, a solder mask layer 900, and solder balls 910 arranged in layers. The chip 100 is encapsulated by an encapsulation material 110, and can be packaged as follows: Figure 1 As shown, the encapsulation material 110 completely covers the chip 100, but the top of the chip 100 may also be exposed. It should be understood that in this embodiment, the multiple encapsulation winding layers only include the first encapsulation winding layer 600 and the second encapsulation winding layer 800. In other optional embodiments of this application, the number of encapsulation winding layers can be two or more.

[0051] In an optional embodiment, the inter-chip fine winding layer 300 is electrically connected to the high-density inter-chip interconnect pins 101 of the chip 100 through the first interconnect hole 410. It should be understood that the interconnect holes (including the first interconnect hole 410, the second interconnect hole 510, and the third interconnect hole 710) in this embodiment are all electrically conductive hole structures. Conductive materials (such as metal or other non-metallic conductive materials) coated on the inner wall, bottom, or filled within the interconnect holes enable the interconnect holes to conduct electricity. Optionally, the first interconnect hole 410 passes through the wiring of the inter-chip fine winding layer 300 and extends to the high-density inter-chip interconnect pins 101 of the chip 100. The first interconnect hole 410 is electrically connected by copper plating, thus electrically connecting the inter-chip fine winding layer 300 to the high-density inter-chip interconnect pins 101 of the chip 100. Figure 1 In one embodiment, the electroplated copper fills the first interconnect hole 410. Of course, in other optional embodiments, the electroplated copper may only coat the inner wall of the first interconnect hole 410.

[0052] The first package winding layer 600 is electrically connected to the inter-chip fine winding layer 300 and / or the low-density chip interconnect pins of the chip 100 via an electrically configured second interconnect via 510. For example... Figure 1 As shown, there are three types of second interconnect holes 510. One type passes through the second insulating layer 500, the first insulating layer 400, then through the lines of the inter-chip fine winding layer 300, and then through the adhesive layer 200 to reach the pins of the chip 100, thus electrically connecting the first package winding layer 600, the inter-chip fine winding layer 300, and the low-density chip interconnect pins 102 of the chip 100. Another type of second interconnect hole 510 passes through the second insulating layer 500, the first insulating layer 400, passes through the inter-chip fine winding layer 300 but avoids the lines on the inter-chip fine winding layer 300, and then through the adhesive layer 200 to reach the pins of the chip 100, thus achieving an electrical connection between the first package winding layer 600 and the chip 100. The third type of second interconnect hole 510 only electrically connects the first package winding layer 600 and the inter-chip fine winding layer 300.

[0053] A third insulating layer 700 separates the second package winding layer 800 from the first package winding layer 600. The second package winding layer 800 can be connected to the inter-chip fine winding layer 300, the first package winding layer 600, and / or the pins of the chip 100 through electrically connected third interconnects 710. Figure 1 As shown, in an optional embodiment, the second package winding layer 800 and the first package winding layer 600 are electrically connected through a third interconnect hole 710.

[0054] A solder resist layer 900 is formed on the side of the second package winding layer 800 away from the chip 100. The solder resist layer 900 exposes part of the circuit of the second package winding layer 800 through gaps, and the solder ball 910 is connected to the circuit of the second package winding layer 800 through gaps.

[0055] In this embodiment, the linewidth and spacing of each winding layer of the chip fine-line fan-out package structure 010 are different. Optionally, the linewidth and spacing gradually increase in the direction away from the chip 100. Specifically... Figure 1 In this embodiment, the line width and spacing of the fine winding layer 300 between chips can be selected as 0.5-2 micrometers, the line width and spacing of the first packaging winding layer 600 can be selected as 2-5 micrometers, and the line width and spacing of the second packaging winding layer 800 can be selected as 5 micrometers or more. This provides users with a variety of options to meet their different needs.

[0056] In optional embodiments of this application, the materials of each winding layer can be titanium, copper, silver, or alloys thereof. The materials of the first insulating layer 400 and the insulating layers between each encapsulation winding layer (including the first and second insulating layers 500 and the third insulating layer 700) include at least one of polyimide, benzocyclobutene (BCB), parylene, industrial liquid crystal polymer (LCP), epoxy resin, silicon oxide, silicon nitride, ceramic, aluminum oxide, and glass. In this embodiment, the first insulating layer 400 can be a polymer (such as parylene epoxy resin), an inorganic material (such as silicon dioxide, silicon nitride, etc.), or a ceramic film (alumina, aluminum nitride, silicon carbide, etc.). The adhesive material can be an insulating DAF film or other insulating materials with adhesive functions. The material of the second insulating layer 500 can be a permanent photoresist, a photoresist dry film, or a non-photosensitive polymer, inorganic material, ceramic film, etc. The third insulating layer 700 can be a photosensitive / non-photosensitive material, such as PI, BCB, pyrene, or epoxy resin (DAF film). The conductive material filling each interconnect can be a metal such as copper, aluminum, or tungsten, or anisotropic conductive adhesive, conductive paste, or alloys such as tin-silver, tin-silver-copper, or gold-tin.

[0057] Of course, the package structure can be a BGA or a surface mount package (thus eliminating the need for solder balls 910 and the BGA ball-mounting process).

[0058] This application also provides a method for fabricating a chip fine-line fan-out package structure, which can be used to prepare the chip fine-line fan-out package structure 010 provided in the embodiments of this application. The fabrication method includes: sequentially fabricating a first insulating layer, a chip-to-chip fine winding layer, and an adhesive layer on one side surface of a temporary support material; mounting multiple chips on the side of the adhesive layer away from the chip-to-chip fine winding layer, wherein the chip pins include high-density chip-to-chip interconnect pins and low-density chip-to-chip interconnect pins, and the chip pins are precisely aligned with the chip-to-chip fine winding layer; encapsulating the multiple chips with an encapsulation material and covering the adhesive layer;

[0059] Remove the temporary support material; open a first interconnect hole on the first insulating layer, the first interconnect hole penetrates the first insulating layer, the inter-chip fine winding layer and the adhesive layer and exposes the high-density inter-chip pins of the chip; fill the first interconnect hole with conductive material so that the inter-chip fine winding layer is electrically connected to the high-density inter-chip pins of the chip.

[0060] A second insulating layer is coated on the first insulating layer, covering the first insulating layer and the first interconnect. A first packaging winding layer is formed on the second insulating layer. A second interconnect is formed, penetrating the first packaging winding layer, the second insulating layer, the first insulating layer, and the inter-chip fine winding layer, exposing low-density chip interconnect pins, and / or penetrating the first packaging winding layer, the second insulating layer, and the first insulating layer to expose the inter-chip fine winding layer. A conductive material is filled in the second interconnect, and the low-density chip interconnect pins are electrically connected to the inter-chip fine winding layer and the first packaging winding layer through the conductive material in the second interconnect.

[0061] At least one insulating layer and at least one package winding layer are alternately prepared in the direction away from the chip in the first package winding layer. Interconnect holes are formed on each insulating layer and filled with conductive material. Electrical connections are formed between each package winding layer through the conductive material in the interconnect holes.

[0062] The package winding layer furthest from the chip has pin pads, a solder mask is covered on the package winding layer furthest from the chip, at least part of the solder mask covering the pin pads is removed, and solder balls are planted on the pin pads.

[0063] Figure 2 This is a flowchart illustrating a method for fabricating a chip fine-line fan-out package structure 010 according to one embodiment of this application. Figure 2 As shown, in this embodiment, the manufacturing method includes:

[0064] Step S100: The first insulating layer, the fine winding layer between chips, and the adhesive layer are fabricated layer by layer on the temporary support material.

[0065] In step S200, the chip is mounted on the side of the adhesive layer away from the fine winding layer between the chips, and the high-density inter-chip interconnect pins are precisely aligned with the fine winding layer between the chips.

[0066] In step S300, a first interconnect hole is formed on the first insulating layer. The first interconnect hole passes through the inter-chip fine winding layer and reaches the high-density inter-chip interconnect pin of the chip. The first interconnect hole is electrically connected to the high-density inter-chip interconnect pin of the chip.

[0067] In step S400, at least one insulating layer and at least one package winding layer are alternately prepared on the first insulating layer, and each package winding layer is electrically connected to the chip pins through interconnect holes, and / or electrically connected to the previously prepared at least one package winding layer, wherein the linewidth and line spacing of each package winding layer, including the inter-chip fine winding layer, are different.

[0068] The fabrication method provided in this application provides a chip fine-line fan-out package structure 010 with multiple winding layers. The multiple winding layers include an inter-chip fine winding layer 300 and multiple package winding layers. The inter-chip fine winding layer 300 connects each chip, and its linewidth and spacing are smaller than those of the package winding layers. Because this package structure has winding layers with different linewidths and spacings, and these layers are electrically connected to each other or to the pins of the chip 100, the chip fine-line fan-out package structure 010 can meet different user needs.

[0069] Figures 3 to 14 This is a schematic diagram illustrating the fabrication process of a chip fine circuit fan-out package structure 010 in one embodiment of this application. The following describes the fabrication process... Figure 1 Taking the chip fine circuit fan-out package structure 010 of the embodiment as an example, the above steps S100 to S400 will be introduced.

[0070] Step S100: The first insulating layer, the fine winding layer between chips, and the adhesive layer are fabricated layer by layer on the temporary support material.

[0071] In an optional embodiment, step S100 may specifically include: preparing a first insulating layer 400 on the temporary support material 020; preparing an inter-chip fine winding layer 300 (e.g., ...) on the first insulating layer 400. Figure 3 As shown); an adhesive material is prepared on the fine winding layer 300 between chips to form an adhesive layer 200 (as shown). Figure 4 (As shown). Optionally, the temporary support material 020 may be made of metal, glass, silicon, or ceramic. The temporary support material 020 is removed before the first interconnect hole 410 is formed.

[0072] Optionally, a fine inter-chip wiring layer 300 may be fabricated on the first insulating layer 400. Specifically, this may include: sputtering a metal material onto the first insulating layer 400, and forming the fine inter-chip wiring layer 300 using photolithography and etching; or sputtering a seed layer onto the first insulating layer 400, and forming the fine inter-chip wiring layer 300 using photolithography and copper electroplating. The metal material and seed layer may be titanium, copper, silver, or alloys thereof. Photolithography includes forming circuit patterns with photoresist (using photolithography or other methods), and etching includes removing the metal not covered by the photoresist using dry or wet methods. After removing the photoresist, the remaining metal forms the fine inter-chip wiring layer 300.

[0073] Step S200: Mount the chip on the side of the adhesive layer away from the fine winding layer between the chips.

[0074] like Figure 5 As shown, the chip 100 with its pins is attached to the adhesive layer 200. At this point, neither the high-density inter-chip interconnect pins 101 nor the low-density chip pins 102 of the chip 100 are electrically connected to the fine inter-chip winding layer 300. Multiple chips 100 can be selected. After mounting the chips 100, they are sealed with encapsulating material, such as... Figure 6 As shown, the chip 100 can be completely encapsulated; alternatively, the upper surface of the chip 100 can be exposed. After encapsulation, the temporary support material 020 used for support is removed to facilitate subsequent processing on the first insulating layer 400, such as... Figure 7 As shown.

[0075] In step S300, a first interconnect hole is formed on the first insulating layer. The first interconnect hole passes through the inter-chip fine winding layer and reaches the high-density inter-chip interconnect pin of the chip. The first interconnect hole is electrically connected to the high-density inter-chip interconnect pin of the chip.

[0076] like Figure 8 As shown, a plurality of first interconnect holes 410 are formed on the first insulating layer 400, all extending from the side of the first insulating layer 400 away from the chip 100. Figure 8 The first interconnect hole 410 extends from the lower side of the chip 100 towards the chip 100, and extends to the high-density inter-chip interconnect pins 101 of the chip 100. Optionally, the first interconnect hole 410 is formed by laser drilling, or by photolithography and dry etching. During the formation of the first interconnect hole 410, and in subsequent steps, [the following steps can be performed]. Figure 8 The structure shown is flipped over for processing.

[0077] Then, the first interconnect hole 410 is filled with a conductive material to achieve electrical properties. Optionally, the first interconnect hole 410 is electrically connected by using a copper electroplating process to fill the first interconnect hole 410 with copper (e.g.,Figure 9 (As shown). Of course, in an alternative embodiment, covering the inner wall of the first interconnect hole 410 with copper can also achieve electrical connection between the fine inter-chip winding layer 300 and the high-density inter-chip interconnect pins 101 of the chip 100.

[0078] In step S400, at least one insulating layer and at least one package winding layer are alternately prepared on the first insulating layer, and each package winding layer is electrically connected to the low-density chip interconnect pins of the chip, and / or to the previously prepared at least one winding layer through interconnect holes.

[0079] Production Figure 1 Taking the chip fine circuit fan-out package structure 010 as an example, two insulating layers and two package winding layers are prepared on the first insulating layer 400. Step S400 specifically includes: preparing a second insulating layer 500 on the side of the first insulating layer 400 away from the chip 100; forming a second interconnect hole 510 on the second insulating layer 500, the second interconnect hole 510 being connected to the low-density chip pins and / or the inter-chip fine winding layer 300 of the chip 100; depositing metal material on the second insulating layer 500 and electrifying the second interconnect hole 510; etching the metal material on the second insulating layer 500 to form a first packaging winding layer 600; preparing a third insulating layer 700 on the first packaging winding layer 600; forming a third interconnect hole 710 on the third insulating layer 700, the third interconnect hole 710 being connected to the first packaging winding layer 600; depositing metal material on the third insulating layer 700 and electrifying the third interconnect hole 710; etching the metal material on the third insulating layer 700 to form a second packaging winding layer 800. It should be understood that in this application, the connection of the second interconnect hole 510 to the low-density chip pins of the chip 100 and / or the fine winding layer 300 between chips means that all of the second interconnect holes 510 are connected to the low-density chip pins of the chip 100, or all of them are connected to the fine winding layer 300 between chips, or some of them are connected to the low-density chip pins of the chip 100 and the other part is connected to the fine winding layer 300 between chips.

[0080] like Figure 10 As shown, a second insulating layer 500 is first prepared on the first insulating layer 400 to cover the copper filling the first interconnect hole 410.

[0081] like Figure 11 As shown, multiple second interconnect holes 510 are then formed on the second insulating layer 500, in a manner similar to that of the first interconnect holes 410, and will not be described in detail here. Figure 11As shown, the second interconnect via 510 has several forms: the first extends only to the inter-chip fine winding layer 300, exposing part of the wiring of the inter-chip fine winding layer 300; the second extends through the inter-chip fine winding layer 300 to the low-density chip pins 102 of the chip 100; the third extends through the inter-chip fine winding layer 300 but is not directly electrically connected to the inter-chip fine winding layer 300, extending to the low-density chip interconnect pins 102 of the chip 100, and therefore is not connected to the wiring of the inter-chip fine winding layer 300. These three types of second interconnect vias 510 provide three interconnection methods.

[0082] like Figure 12 As shown, after the second interconnect 510 is formed, a seed layer (titanium, copper, or an alloy of both) is magnetron sputtered onto the second insulating layer 500. Then, photoresist is applied, and photolithography is performed (exposing and developing to expose the second interconnect 510 and the circuit pattern). Copper is then plated using an electroplating process, which electrically converts the second interconnect 510 (…). Figure 12 In this process, copper is only applied to the inner wall of the second interconnect hole 510, and the circuit portion of the first package winding layer 600 is also plated with copper. Then, the photoresist is removed to expose the seed layer, which is then removed using a dry or wet method to obtain the first package winding layer 600. Figure 13 As shown.

[0083] like Figure 14 As shown, a third insulating layer 700 is prepared on the first package winding layer 600, and a portion of the material of the third insulating layer 700 fills the second interconnect hole 510. Then, a third interconnect hole 710 is formed on the third insulating layer 700, and the third interconnect hole 710 connects to the lines of the first package winding layer 600. The method of forming the third interconnect hole 710 is similar to that of the first interconnect hole 410 and will not be described again here.

[0084] like Figure 15 As shown, a metal material is deposited on the third insulating layer 700, and the third interconnect 710 is electrically connected. The metal material on the third insulating layer 700 is etched to form the second package winding layer 800. The method of fabricating the second package winding layer 800 and electrically connecting the third interconnect 710 is similar to the method of fabricating the first package winding layer 600 and electrically connecting the second interconnect 510. The difference is that when the third interconnect 710 is electrically connected using an electroplating copper process, the third interconnect 710 is completely filled with copper. The fabrication method of this application embodiment also includes preparing a solder resist layer 900 on the package winding layer furthest from the chip 100. The solder resist layer 900 forms a gap, and the solder ball 910 is connected to the package winding layer furthest from the chip 100 through the gap formed by the solder resist layer 900, finally obtaining the package winding layer 800 as shown in the figure. Figure 1 The chip shown is a fine-line fan-out package structure 010. Figure 14In this configuration, the second package winding layer 800 is the package winding layer furthest from the chip 100, and it also has the widest line width and spacing. Therefore, a solder mask layer 900 is provided on the second package winding layer 800, and solder balls 910 are connected to the lines of the second package winding layer 800 to achieve electrical connection with the second package winding layer 800.

[0085] It should be understood that, in alternative embodiments, the second package winding layer 800 may also be connected to the low-density chip pins 102 of the chip 100, or to the inter-chip fine winding layer 300.

[0086] It should be noted that in this embodiment, the process of electrifying each interconnect hole can be: preparing an interconnect hole seed layer by physical vapor deposition, chemical plating, or chemical vapor deposition, and then filling it with conductive metal by chemical plating or electroplating; or, filling the interconnect hole with conductive paste, solder paste, silver paste, etc. by stencil or screen printing.

[0087] The method for fabricating a fine-line fan-out package structure provided in this application can not only produce a fine-line fan-out package structure with multiple interconnect winding layers of different linewidths and spacings to meet various user needs, but also optimize the stress magnitude and distribution, thermal resistance characteristics, and electrical measurement characteristics of the fine-line fan-out package structure by selecting insulating materials and processing techniques, thereby improving the performance and reliability of the fine-line fan-out package structure.

[0088] Industrial applicability

[0089] The chip fine circuit fan-out packaging structure and the packaging structure obtained by the manufacturing method provided in this application allow users to select winding layers with different line widths and spacings for signal transmission, which can meet the user's needs in more scenarios.

Claims

1. A method for fabricating a chip fine circuit fan-out package structure, characterized in that, include: A first insulating layer, a fine inter-chip winding layer, and an adhesive layer are sequentially fabricated on one side of the temporary support material. Multiple chips are mounted on the side of the adhesive layer away from the fine inter-chip winding layer. The pins of the chips include high-density inter-chip interconnect pins and low-density inter-chip interconnect pins. The pins of the chips are precisely aligned with the fine inter-chip winding layer. The plurality of chips are encapsulated with encapsulating material and covered with the adhesive layer; Remove the temporary support material; A first interconnect hole is formed on the first insulating layer. The first interconnect hole penetrates the first insulating layer, the inter-chip fine winding layer and the adhesive layer and exposes the high-density inter-chip pins of the chip. The first interconnect hole is filled with conductive material so that the inter-chip fine winding layer is electrically connected to the high-density inter-chip pins of the chip. A second insulating layer is coated on the first insulating layer, the second insulating layer covering the first insulating layer and the first interconnection hole, and a first encapsulation winding layer is prepared on the second insulating layer; A second interconnect is fabricated, wherein the second interconnect penetrates the first package winding layer, the second insulating layer, the first insulating layer and the inter-chip fine winding layer and exposes the low-density chip interconnect pins, and / or penetrates the first package winding layer, the second insulating layer and the first insulating layer and exposes the inter-chip fine winding layer; a conductive material is filled in the second interconnect, and the low-density chip interconnect pins are electrically connected to the inter-chip fine winding layer and the first package winding layer through the conductive material in the second interconnect; At least one insulating layer and at least one packaging winding layer are alternately prepared in the direction away from the chip in the first packaging winding layer, and interconnect holes are formed on each insulating layer and the interconnect holes are filled with conductive material; Electrical connections are formed between each of the package winding layers through conductive material in the interconnect holes, and the line width and spacing of the fine winding layers between the chips are smaller than the line width and spacing of each of the package winding layers. The package winding layer furthest from the chip has pin pads, a solder mask is covered on the package winding layer furthest from the chip, at least part of the solder mask covering the pin pads is removed, and solder balls are planted on the pin pads.

2. The method for fabricating a chip fine circuit fan-out packaging structure according to claim 1, characterized in that, The linewidth and spacing of each winding layer, including the inter-chip fine winding layer, the first packaging winding layer, and other packaging winding layers, gradually increase in the direction away from the chip.

3. The method for fabricating a chip fine circuit fan-out packaging structure according to claim 1, characterized in that, The conductive material within the second interconnect hole electrically connects the low-density chip interconnect pins to the first package winding layer, and / or electrically connects the inter-chip fine winding layer to the first package winding layer.

4. The method for fabricating a chip fine circuit fan-out packaging structure according to claim 1, characterized in that, The sidewalls and bottom of the second interconnect hole are coated with a conductive material, and the remaining space inside the second interconnect hole is filled with the material of the third insulating layer, or the second interconnect hole is filled with a conductive material.

5. The method for fabricating a chip fine circuit fan-out package structure according to claim 1, characterized in that, Fill each of the interconnect holes with a conductive material, including: A seed layer of metal is magnetron sputtered or chemically plated on the sidewalls and bottom of the interconnect hole, and conductive material is filled into the interconnect hole using an electroplating process; or conductive material is filled into the interconnect hole by screen / stencil printing.

6. The method for fabricating a chip fine circuit fan-out packaging structure according to claim 5, characterized in that, The interconnect holes are formed by laser drilling, or by photolithography and dry etching.

7. A chip fine circuit fan-out packaging structure, characterized in that, The fine-line fan-out package structure includes multiple chips and multiple winding layers. Each chip includes a device and pins. The pins include high-density inter-chip interconnect pins and low-density inter-chip interconnect pins. The multiple winding layers include an inter-chip fine winding layer and a package winding layer. The linewidth and line spacing of the inter-chip fine winding layer are smaller than the linewidth and line spacing of the package winding layer. The inter-chip fine winding layer is connected to the chips through the high-density inter-chip pins. The fine-line fan-out package structure is manufactured by the method for manufacturing a chip fine-line fan-out package structure as described in any one of claims 1 to 6.

8. The chip fine circuit fan-out packaging structure according to claim 7, characterized in that, An adhesive layer is formed using an insulating adhesive material or anisotropic conductive material to attach one side of the chip's pins to the nearest fine winding layer between the chips, with the chip pins and the fine winding layer between the chips precisely aligned.

9. The chip fine circuit fan-out packaging structure according to claim 8, characterized in that, The first interconnect hole penetrates the first insulating layer, the inter-chip fine winding layer, and the adhesive layer to the high-density inter-chip pins of the chip, and the first interconnect hole is filled with conductive material; the inter-chip fine winding layer achieves high-density inter-chip pin electrical interconnection between different chips through the conductive material filled in the first interconnect hole.

10. The chip fine circuit fan-out packaging structure according to claim 9, characterized in that, The insulating layer includes a second insulating layer, the interconnect includes a second interconnect, the package winding layer includes a first package winding layer, the second insulating layer covers the first insulating layer and the first interconnect, and the first package winding layer is disposed on the second insulating layer; the second interconnect may penetrate the first insulating layer and the second insulating layer to the inter-chip fine winding layer, and / or penetrate the second insulating layer, the first insulating layer, the inter-chip fine winding layer and the adhesive layer to the low-density chip interconnect pin, and only the sidewalls of the second interconnect are coated with conductive material to achieve electrical interconnection between the first package winding layer and the inter-chip fine winding layer and / or the low-density chip interconnect pin.

11. The chip fine circuit fan-out packaging structure according to claim 10, characterized in that, The insulating layer further includes a third insulating layer, the interconnecting hole further includes a third interconnecting hole, the encapsulation winding layer further includes a second encapsulation winding layer, the third insulating layer covers the first encapsulation winding layer, and the material of the third insulating layer fills the second interconnecting hole; the third interconnecting hole penetrates the third insulating layer, the second encapsulation winding layer is disposed on the third insulating layer, and is electrically connected to the first encapsulation winding layer through the conductive material in the third interconnecting hole.

12. The chip fine circuit fan-out packaging structure according to claim 7, characterized in that, The linewidth and spacing of the encapsulation winding layer are greater than those of the inter-chip fine winding layer. The linewidth and spacing of the inter-chip fine winding layer are 0.5-2 micrometers, and the linewidth and spacing of the first encapsulation winding layer are 2-5 micrometers.

13. The chip fine circuit fan-out packaging structure according to claim 12, characterized in that, The linewidth and line spacing of all winding layers, including the inter-chip fine winding layer and the packaging winding layer, gradually increase in the direction away from the chip. The linewidth of the other packaging winding layers, except for the first packaging winding layer, is 5 micrometers or more.

14. The chip fine circuit fan-out packaging structure according to claim 7, characterized in that, The material of the first insulating layer and the insulating layer between each of the encapsulation winding layers includes at least one of polyimide, benzocyclobutene (BCB), parylene, industrial liquid crystal polymer (LCP), epoxy resin, silicon oxide, silicon nitride, ceramic, aluminum oxide, and glass.

15. The chip fine circuit fan-out packaging structure according to claim 11, characterized in that, The conductive material in the first interconnect hole, the second interconnect hole, and the third interconnect hole is at least one of copper, aluminum, tungsten, conductive paste, tin-silver alloy, tin-silver-copper alloy, and gold-tin alloy.

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