Semiconductor device and electronic device

Abstract

A semiconductor device capable of achieving high detection efficiency and low jitter without depending on thickening of a substrate is provided. The semiconductor device includes a plurality of pixels each of which has an avalanche photodiode element that photoelectrically converts incident light, each of the plurality of pixels being provided with: a substrate including a first semiconductor material; and a stacked portion that is stacked on a surface of the substrate on a light incident side and includes a second semiconductor material different from the first semiconductor material.

Description

Technical Field

[0001] This disclosure (the technology) relates to a semiconductor device and an electronic device having the semiconductor device. Background Technology

[0002] Avalanche photodiodes (APDs) include Geiger mode, which operates at a bias voltage above the breakdown voltage, and linear mode, which operates at a bias voltage slightly higher than the breakdown voltage. Geiger mode avalanche photodiodes are also known as single-photon avalanche photodiodes (SPADs).

[0003] SPAD is a device that can detect a photon for each pixel by multiplying the charge carriers generated by photoelectric conversion in the PN junction region provided with a high electric field for each pixel.

[0004] Incidentally, there is a need to improve the sensitivity of SPAD pixels, so a method has been proposed to improve the detection efficiency, known as photon detection efficiency (PDE), while ensuring a large area of ​​doubling region (e.g., Patent Document 1).

[0005] List of cited references

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2018-201005 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] Incidentally, in SPADs, due to the use of silicon (Si) in the substrate, the sensitivity in the infrared (IR) region is low. To improve the PDE, the Si needs to be thickened. When the Si is thickened, the time for photoelectric electrons to reach the multiplication region increases, and there are concerns about the deterioration of jitter characteristics when it is used for laser imaging detection and ranging (LIDAR).

[0010] In view of this situation, the present invention was realized, and its object is to provide a semiconductor device and electronic device that can achieve high detection efficiency and low jitter without relying on substrate thickening.

[0011] Solutions to technical problems

[0012] One aspect of this disclosure is a semiconductor device comprising a plurality of pixels, each pixel having an avalanche photodiode element for photoelectric conversion of incident light; each of the plurality of pixels having a substrate comprising a first semiconductor material; and a stack portion stacked on the light-incident side of the substrate, and comprising a second semiconductor material different from the first semiconductor material.

[0013] Another aspect of this disclosure is an electronic device including a semiconductor device comprising a plurality of pixels, each pixel having an avalanche photodiode element for photoelectric conversion of incident light; each of the plurality of pixels having a substrate comprising a first semiconductor material; and a stack portion stacked on the light-incident side of the substrate, and comprising a second semiconductor material different from the first semiconductor material. Attached Figure Description

[0014] Figure 1A This is a schematic structural diagram showing the use of SPAD as a pixel circuit in a solid-state imaging device according to a first embodiment of the present technology.

[0015] Figure 1B This diagram illustrates the operation in the first embodiment of this technology when the pixel is an active pixel.

[0016] Figure 2 This is a cross-sectional view showing an example of three pixels according to a first embodiment of the present technology.

[0017] Figure 3 This is a cross-sectional view of an example of three pixels from a comparative example.

[0018] Figure 4 This is a cross-sectional view showing a three-pixel example of a variation of the first embodiment of the present technology.

[0019] Figure 5 This is a cross-sectional view showing an example of three pixels of the second embodiment of the present technology.

[0020] Figure 6 This is a cross-sectional view showing a three-pixel example of a first variant of the second embodiment of the present technology.

[0021] Figure 7 This is a cross-sectional view showing a three-pixel example of a second variant of the second embodiment of the present technology.

[0022] Figure 8 This is a cross-sectional view showing an example of three pixels in the third embodiment of the present technology.

[0023] Figure 9 This is a cross-sectional view showing a three-pixel example of a first variant of the third embodiment of the present technology.

[0024] Figure 10 This is a cross-sectional view showing a three-pixel example of a second variant of the third embodiment of the present technology.

[0025] Figure 11This is a cross-sectional view showing an example of three pixels in the fourth embodiment of the present technology.

[0026] Figure 12 This is a cross-sectional view showing a three-pixel example of a variation of the fourth embodiment of the present technology.

[0027] Figure 13 This is a cross-sectional view showing an example of three pixels of the fifth embodiment of the present technology.

[0028] Figure 14 This is a cross-sectional view showing an example of three pixels of the sixth embodiment of the present technology.

[0029] Figure 15 This is a cross-sectional view showing a three-pixel example of a first variant of the sixth embodiment of the present technology.

[0030] Figure 16 This is a cross-sectional view showing a three-pixel example of a second variant of the sixth embodiment of the present technology.

[0031] Figure 17 This is a cross-sectional view showing an example of three pixels of the seventh embodiment of the present technology.

[0032] Figure 18 This is a cross-sectional view showing a three-pixel example of a variation of the seventh embodiment of the present technology.

[0033] Figure 19 This is a cross-sectional view showing an example of three pixels of the eighth embodiment of the present technology.

[0034] Figure 20 This is a cross-sectional view showing a three-pixel example of a first variant of the eighth embodiment of the present technology.

[0035] Figure 21 This is a cross-sectional view showing a three-pixel example of a second variant of the eighth embodiment of the present technology.

[0036] Figure 22 This is a cross-sectional view showing an example of three pixels of the ninth embodiment of the present technology.

[0037] Figure 23 This is a cross-sectional view showing a three-pixel example of a first variant of the ninth embodiment of the present technology.

[0038] Figure 24 This is a cross-sectional view showing a three-pixel example of a second variant of the ninth embodiment of the present technology.

[0039] Figure 25 This is a cross-sectional view showing an example of three pixels of the tenth embodiment of the present technology.

[0040] Figure 26 This is a cross-sectional view showing a three-pixel example of a first variant of the tenth embodiment of the present technology.

[0041] Figure 27 This is a cross-sectional view showing a three-pixel example of a second variant of the tenth embodiment of the present technology.

[0042] Figure 28 This is a cross-sectional view showing an example of three pixels of the eleventh embodiment of the present technology.

[0043] Figure 29 This is a cross-sectional view of a three-pixel example of a variation of the eleventh embodiment of the present technology.

[0044] Figure 30 This is a cross-sectional view showing an example of three pixels of the twelfth embodiment of the present technology.

[0045] Figure 31 This is a cross-sectional view of a three-pixel example of a variant of the twelfth embodiment of the present technology.

[0046] Figure 32 This is a cross-sectional view showing an example of three pixels of the thirteenth embodiment of the present technology.

[0047] Figure 33 This is a cross-sectional view showing a three-pixel example of a variation of the thirteenth embodiment of the present technology.

[0048] Figure 34 This is a cross-sectional view showing an example of three pixels of the fourteenth embodiment of the present technology.

[0049] Figure 35 This is a cross-sectional view showing a three-pixel example of a variation of the fourteenth embodiment of the present invention.

[0050] Figure 36 This is a block diagram showing a light-receiving element including pixels according to the first to fourteenth embodiments of the present technology.

[0051] Figure 37 It shows that it includes Figure 36 A block diagram illustrating an example of the construction of a ranging system using an optical receiving element.

[0052] Figure 38 It is shown as being equipped with Figure 37 A block diagram illustrating the construction example of a smartphone with an electronic device for a ranging system.

[0053] Figure 39 This is a block diagram illustrating a construction example of a camera device as an electronic device to which this technology is applied. Detailed Implementation Plan

[0054] The embodiments of this disclosure will be described below with reference to the accompanying drawings. In the figures referenced in the following description, the same or similar reference numerals denote the same or similar parts, and repeated descriptions are omitted. It should be noted that the drawings are schematic, and the relationships between thickness and planar dimensions, the thickness ratios between devices and components, etc., differ from actual dimensions. Therefore, specific thicknesses and dimensions should be determined based on the following description. Furthermore, it goes without saying that dimensional relationships and ratios differ partially between the drawings.

[0055] In this specification, "first conductivity type" refers to either p-type or n-type, and "second conductivity type" refers to either p-type or n-type that is different from "first conductivity type". Furthermore, "n" or "p" with added "+" or "-" indicates a semiconductor region with a relatively higher or lower impurity concentration than a semiconductor region without added "+" or "-". However, even in semiconductor regions with the same added "n", it does not mean that the impurity concentration of the semiconductor regions is exactly the same.

[0056] Furthermore, the definitions of directions such as up and down described below are merely for ease of explanation and do not limit the technical concept of this disclosure. For example, needless to say, if the object is viewed when rotated 90°, the up and down directions are converted to left and right directions, and if the object is viewed when rotated 180°, the up and down directions are inverted.

[0057] Note that the effects described in this instruction manual are illustrative only, and the effects are not limited to these, and other effects may also occur.

[0058] <First Implementation Plan>

[0059] <Example of the overall structure of a solid-state imaging device>

[0060] The solid-state imaging device, as a semiconductor device according to the first embodiment, can be applied to, for example, a ranging sensor that measures distance using the time-of-flight (ToF) method. For example, the solid-state imaging device has a photoelectric conversion function for light with wavelengths ranging from the visible region of about 380 nm to less than 780 nm to the infrared region of about 780 nm to less than 2400 nm.

[0061] The solid-state imaging device performs photoelectric conversion on incident light, and each of the multiple pixels, including SPADs that accumulate charge carriers such as electrons and holes, is arranged in a two-dimensional array to perform imaging.

[0062] Figure 1A The pixel circuit using SPAD is shown. The solid-state imaging device 1 is provided with pixel P. Figure 1AThe pixel P is equipped with a SPAD element 2, a constant current source 102, a transistor 103 and an inverter 104.

[0063] The cathode of SPAD element 2 is connected to the constant current source 102, and also to the input of inverter 104 and the drain of transistor 103. The anode of SPAD element 2 is connected to the power supply VSPAD.

[0064] SPAD element 2 is a photodiode (single-photon avalanche photodiode) that amplifies the generated electrons when incident light strikes it and outputs a signal of the cathode voltage VS. The power supply VSPAD to the anode of SPAD element 2 is, for example, set to a negative bias (negative potential) with the same voltage as the breakdown voltage VBD of SPAD element 2.

[0065] The constant current source 102 includes, for example, a P-type MOS transistor operating in the saturation region, and performs passive quenching by acting as a quench resistor. A supply voltage VE (VE > 0) is supplied to the constant current source 102. Note that pull-up resistors, etc., can also be used in place of the P-type MOS transistor for the constant current source 102.

[0066] In order to detect light (photons) with sufficient efficiency, a voltage greater than the breakdown voltage VBD of SPAD element 2 (hereinafter referred to as overbias voltage) is applied to SPAD element 2.

[0067] The drain of transistor 103 is connected to the cathode of SPAD element 2, the input terminal of inverter 104, and constant current source 102, and the source of transistor 103 is connected to ground (GND). A gating control signal VG is supplied from the pixel driving unit driving pixel P to the gate of transistor 103.

[0068] When pixel P is an active pixel, a low (Lo) gating control signal VG is supplied from the pixel driving unit to the gate of transistor 103. In contrast, when pixel P is an active pixel, a high (Hi) gating control signal VG is supplied from the pixel driving unit to the gate of transistor 103.

[0069] The inverter 104 outputs the Hi PFout signal when the cathode voltage VS, which is used as the input signal, is Lo, and outputs the Lo PFout signal when the cathode voltage VS is Hi.

[0070] Next, refer to Figure 1B This describes the operation when pixel P is an active pixel. Figure 1B This is a graph showing the change of the cathode voltage VS of SPAD element 2 according to the incident photon and the detection signal PFout.

[0071] First, when pixel P is an active pixel, transistor 103 is set to cut off by the Lo gating control signal VG.

[0072] exist Figure 1B Before time t0, since power supply voltage VE and power supply VSPAD are supplied to the cathode and anode of SPAD element 2 respectively, SPAD element 2 is subjected to a reverse voltage greater than the breakdown voltage VBD, causing SPAD element 2 to be set to Geiger mode. In this state, the cathode voltage VS of SPAD element 2 is the same as the power supply voltage VE.

[0073] When a photon is incident on SPAD element 2 set to Geiger mode, avalanche multiplication occurs, and current flows through SPAD element 2.

[0074] Assume that avalanche multiplication occurs at time t0 and current flows through SPAD element 2. After time t0, current flows through SPAD element 2, causing current to also flow through the P-type MOS transistor, which is a constant current source 102, and a voltage drop occurs due to the resistive component of the MOS transistor.

[0075] At time t2, when the cathode voltage VS of SPAD element 2 becomes lower than 0V, it becomes lower than the breakdown voltage VBD, thereby stopping avalanche multiplication. Here, the current generated by avalanche multiplication flows through the constant current source 102 to generate a voltage drop, and the operation that stops avalanche multiplication by causing the cathode voltage VS to become lower than the breakdown voltage VBD along with the generated voltage drop is the quenching operation.

[0076] When avalanche multiplication stops, the current flowing through constant current source 102 (P-type MOS transistor) gradually decreases, and at time t4, the cathode voltage VS returns to the initial power supply voltage VE and enters a state where it can detect the next new photon (recharge operation).

[0077] When the cathode voltage VS, which serves as the input voltage, is equal to or higher than a predetermined threshold voltage Vth (=VE / 2), the inverter 104 outputs a low (Lo) PFout signal, and when the cathode voltage VS is lower than the predetermined threshold voltage, it outputs a high (Hi) PFout signal. Figure 1B In the example, a high (Hi)PFout signal is output during the time period from time t1 to time t3.

[0078] Note that when pixel P is an active pixel, a Hi gating control signal VG is supplied from the pixel driving unit to the gate of transistor 103, and transistor 103 is turned on. Therefore, the cathode voltage VS of SPAD element 2 becomes 0V (GND), and the anode-cathode voltage of SPAD element 2 becomes equal to or lower than the breakdown voltage VBD, so that no reaction occurs even if photons enter SPAD element 2.

[0079] <Pixel Construction>

[0080] Figure 2 It is a cross-sectional view of three pixels P. Figure 2 In the example shown, a solid-state imaging device 1 is illustrated using a back-illuminated type. In the following description, the light incident surface side of each component of the solid-state imaging device 1 will be referred to as... Figure 2 The side facing upwards is called the "back side," and the side opposite to the light incident surface of each component of the solid-state imaging device 1 is called the "back side." Figure 2 The side (the bottom side) is called the "front side". Furthermore, since the three pixels P have the same structure, representative illustrations will be used. Figure 2 The pixel P on the left.

[0081] like Figure 2 As shown, in the solid-state imaging device 1, a substrate 10, a transition layer 20, a stacked material section 30 (which is a stacked structure grown by crystal growth), a p-type well region 61, and an interlayer film 62 are stacked sequentially. On the back side of the interlayer film 62, an on-chip lens 50 is stacked for each pixel P. In addition, a wiring layer 40 is stacked on the front side of the substrate 10.

[0082] For example, substrate 10 is formed by using a semiconductor substrate containing monocrystalline silicon. In substrate 10, the concentration of p-type (first conductivity type) or n-type (second conductivity type) impurities is controlled, and SPAD elements 2 are formed for each pixel P.

[0083] In the wiring layer 40, wiring is formed for supplying voltage to be applied to the SPAD element 2, wiring for extracting electrons (charge carriers) generated in the SPAD element 2 from the substrate 10, etc.

[0084] Pixel P includes SPAD element 2 and pixel isolation unit 60. Multiple pixels P are arranged along mutually perpendicular X and Y directions via pixel isolation unit 60. Pixel isolation unit 60 electrically and optically isolates pixel P from adjacent pixels P.

[0085] The pixel isolation unit 60 is provided with a trench TrA (hereinafter referred to as a full trench TrA) obtained by sandwiching a metal film 63 between two sides using an interlayer film 62 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. The pixel isolation unit 60 with the full trench TrA then extends from the front side of the substrate 10 to the back side of the stacked material portion 30. The metal film 63 is formed using a light-reflecting metal film (e.g., a tungsten (W) thin film). The interlayer film 62 is formed using an insulating film (e.g., a silicon oxide film).

[0086] SPAD element 2 includes a light-absorbing unit 3 disposed in the stacked material section 30 and the transition layer 20, and a Geiger multiplier unit 4 disposed in the substrate 10 and the transition layer 20. The light-absorbing unit 3 is a photoelectric conversion unit that absorbs light incident from the on-chip lens 50 through the interlayer film 62 and the p-type well region 61 to generate electrons (charge carriers). Then, the light-absorbing unit 3 transmits the electrons generated by photoelectric conversion to the Geiger multiplier unit 4 through an electric field.

[0087] The Geiger multiplier unit 4 performs avalanche multiplication on electrons transmitted from the light absorption unit 3. The Geiger multiplier unit 4 includes a p-type first electrode region 11 disposed on the front side of the substrate 10 and an n-type second electrode region 12 disposed at a shallower position than the p-type first electrode region 11. The n-type second electrode region 12 and the p-type first electrode region 11 form a pn junction, and an avalanche multiplication region 13 is formed at the interface of the pn junction.

[0088] In substrate 10, p-type first electrode region 11 includes a p-type semiconductor region with high impurity concentration in Geiger multiplication unit 4, and n-type second electrode region 12 includes an n-type semiconductor region with high impurity concentration in Geiger multiplication unit 4. Avalanche multiplication region 13 is a high electric field region (depletion layer) formed at the pn junction interface between p-type first electrode region 11 and n-type second electrode region 12 by applying a negative voltage higher than the breakdown voltage to n-type second electrode region 12, and multiplies electrons generated by a photon by light absorption unit 3.

[0089] A p-type well region 61 is provided along the wall surface of the pixel isolation unit 60 and the back side of the stacked material section 30. The p-type well region 61 includes a p-type semiconductor region with a higher impurity concentration than the p-type first electrode region 11, and accumulates holes as charge carriers. The p-type well region 61 is electrically connected to the anode 43 formed in the wiring layer 40 and is capable of bias adjustment. Therefore, the hole concentration of the p-type well region 61 is increased, pinning is strengthened, and for example, the generation of dark current can be suppressed.

[0090] A wiring layer 40 is formed on the front side of the substrate 10 and includes wiring 41, a cathode 42, and an anode 43. The cathode 42 includes an n-type semiconductor region with a higher impurity concentration than the n-type second electrode region 12 and is electrically connected to the n-type second electrode region 12 via wiring 41.

[0091] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the n-type second electrode region 12 can be supplied to the cathode 42 from the logic circuit (not shown). Furthermore, in pixel P, bias adjustment of the p-type well region 61 via the anode 43 can be achieved.

[0092] In the solid-state imaging device 1 with the above-described structure, light is applied, and the applied light passes through the on-chip lens 50. The transmitted light is then photoelectrically converted by the SPAD element 2 to generate electrons. The generated electrons are then output to the inverter 104 through the wiring 41 of the wiring layer 40.

[0093] <Comparative Example>

[0094] Incidentally, since silicon (Si) is typically used in the substrate, the sensitivity in the infrared (IR) region is low, and the Si needs to be thickened to improve the PDE.

[0095] Figure 3 This is a cross-sectional view showing an example of the solid-state imaging device 1, which is a comparative example. Figure 3 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0096] In the comparative example, when the substrate 10 containing Si is thickened, the time for electrons after photoelectric conversion to reach the multiplication region increases, and there is a concern that jitter characteristics may deteriorate when it is used as a laser camera for detection and ranging (LiDAR).

[0097] <Countermeasures of the First Implementation Plan>

[0098] Refer again Figure 2 In the first embodiment according to the present technology, a stacked material portion 30 comprising a semiconductor material different from the semiconductor material of the substrate 10 is stacked on the light incident side surface of the substrate 10, thereby improving the absorption efficiency of IR light and improving PDE.

[0099] The semiconductor materials included in the stacked material section 30 are silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe), cadmium sulfide (CdS), etc., which can be crystal grown relative to silicon. Since these semiconductor materials do not match the silicon lattice, a transition layer 20 needs to be inserted between the substrate 10 and the stacked material section 30.

[0100] For example, SiGe, Ge, InGaAs, etc. are narrow bandgap semiconductors with lower bandgap energies than silicon, and have light absorption sensitivity in the infrared (IR) region, which is a wavelength region longer than the visible light region.

[0101] Note that when gallium arsenide (GaAs) and indium phosphide (InP) are used in the substrate 10, similar to the case where silicon is used, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe), cadmium sulfide (CdS), etc. are also used in the stacked material section 30.

[0102] <The Role and Effects of the First Implementation Plan>

[0103] As described above, according to the first embodiment, by stacking a stacked material portion 30 comprising a semiconductor material different from the silicon used in the substrate 10 via a transition layer 20 on the light incident side of the substrate 10, the absorption efficiency of IR light can be improved and the PDE can be improved, and by making the pixel P thinner than a pixel P comprising only a silicon substrate, the jitter characteristics can be improved.

[0104] Furthermore, according to the first embodiment, by providing a full trench TrA for the pixel isolation unit 60 to insulate and isolate multiple adjacent pixels P from each other, crosstalk to adjacent pixels P can be suppressed.

[0105] <Variations on the First Implementation Plan>

[0106] Figure 4 This is a cross-sectional view illustrating an example of a solid-state imaging device 1, a variation of the first embodiment of the present technology. Figure 4 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0107] like Figure 4 As shown, in a variant example, the full trench TrA with the metal film 63 sandwiched between the two sides by the interlayer film 62 is not provided on the pixel separation unit 60A.

[0108] According to this variant of the first embodiment, the absorption efficiency of IR light can also be improved and the PDE can be enhanced, and the jitter characteristics can be improved by making the pixel P thinner than the pixel P which only contains a silicon substrate.

[0109] <Second Implementation Plan>

[0110] Figure 5 This is a cross-sectional view illustrating an example of a solid-state imaging device 1A according to a second embodiment of the present technology. Figure 5 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are listed, and their detailed descriptions are omitted.

[0111] like Figure 5As shown, in the second embodiment, the pixel separation unit 60B has a trench TrB (hereinafter referred to as the front trench TrB) only on the substrate 10 side. The front trench TrB is obtained by sandwiching a metal film 65 from both sides with an insulating film 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. Then, the front trench TrB extends from the front side of the substrate 10 to the back side of the substrate 10.

[0112] <The Role and Effects of the Second Implementation Plan>

[0113] As described above, according to the second embodiment, the solid-state imaging device 1A can be easily manufactured by processing only the substrate 10 to form the pixel isolation unit 60B.

[0114] <First Variation of the Second Implementation Plan>

[0115] Figure 6 This is a cross-sectional view illustrating an example of a solid-state imaging device 1A, a first variant of the second embodiment of the present technology. Figure 6 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0116] like Figure 6 As shown, in the first variant of the second embodiment, the pixel separation unit 60C has a trench TrC (hereinafter referred to as the back trench TrC) only on the side of the stacked material portion 30. The back trench TrC is obtained by sandwiching a metal film 66 from both sides with an interlayer film 62 in a direction perpendicular to the thickness direction (Z direction) of the stacked material portion 30. Then, the back trench TrC extends from the back side of the stacked material portion 30 to the front side of the stacked material portion 30.

[0117] <The Role and Effects of the First Variation of the Second Implementation Plan>

[0118] As described above, according to the first variant of the second embodiment, the solid-state imaging device 1A can be easily manufactured by processing only the stacked material portion 30 to form the pixel isolation unit 60C.

[0119] <Second Variation of the Second Implementation Scheme>

[0120] Figure 7 This is a cross-sectional view illustrating an example of a solid-state imaging device 1A, a second variation of the second embodiment of the present technology. Figure 7 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0121] like Figure 7 As shown, the solid-state imaging device 1A of the second variant of the second embodiment has a structure without an on-chip lens 50.

[0122] <The Role and Effects of the Second Variation of the Second Implementation Scheme>

[0123] As described above, according to the second variant of the second embodiment, as in the case of the first embodiment described above, by processing the substrate 10, the transition layer 20 and the stacked material portion 30 to form the pixel isolation unit 60, the solid-state imaging device 1A can be easily manufactured, and by providing a full trench TrA in the pixel isolation unit 60 to insulate and isolate adjacent multiple pixels P from each other, crosstalk to adjacent pixels P can be suppressed.

[0124] <Third Implementation Plan>

[0125] Figure 8 This is a cross-sectional view illustrating an example of a solid-state imaging device 1B according to a third embodiment of the present technology. Figure 8 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0126] like Figure 8 As shown, in the third embodiment, the pixel isolation unit 60D extends from the front side of the substrate 10 to the back side of the substrate 10. The pixel isolation unit 60D is provided with a front trench TrB obtained by sandwiching a metal film 65 between two sides using an insulating film 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. A p-type well region 67 is provided on the wall surface of the pixel isolation unit 60D.

[0127] In the third embodiment, the stacked material section 30 is an n-type semiconductor region.

[0128] <The Role and Effects of the Third Implementation Plan>

[0129] As described above, according to the third embodiment, similar effects and functions as those of the second embodiment can be obtained, and the area capable of absorbing light can be expanded by making the stacked material portion 30 non-p-type.

[0130] <First Variation of the Third Implementation Plan>

[0131] Figure 9 This is a cross-sectional view illustrating an example of a solid-state imaging device 1B, a first variant of the third embodiment of the present technology. Figure 9 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0132] like Figure 9As shown, in the first variant of the third embodiment, the pixel separation section 60E has a trench TrC (hereinafter referred to as the back trench TrC) only on the side of the stacked material section 30. The back trench TrC is obtained by sandwiching a metal film 66 from both sides with an interlayer film 62 in a direction perpendicular to the thickness direction (Z direction) of the stacked material section 30. Then, the back trench TrC extends from the back side of the stacked material section 30 to the front side of the stacked material section 30.

[0133] P-type well region 68 is disposed on the wall surface of pixel isolation unit 60E. P-type well region 14 electrically connected to anode 43 of wiring layer 40 is disposed on the front side of substrate 10.

[0134] <The Role and Effects of the First Variation of the Third Implementation Plan>

[0135] As described above, according to the first variant of the third embodiment, a similar effect to the first variant of the second embodiment can be obtained, and color mixing on the incident light side can be suppressed.

[0136] <Second Variation of the Third Implementation Plan>

[0137] Figure 10 This is a cross-sectional view illustrating an example of a solid-state imaging device 1B, a second variant of the third embodiment of the present technology. Figure 10 In the figures, the same reference numerals are used to denote the figures described above. Figure 8 The same parts are omitted, and their detailed descriptions are omitted.

[0138] like Figure 10 As shown, in the pixel isolation unit 60F of the second variant, no trench is provided by sandwiching the metal film 65 from both sides with the insulating film 64, and only the p-type well region 67 is provided.

[0139] According to this second variant of the third implementation scheme, the same function and effect as the third implementation scheme described above can also be obtained.

[0140] <Fourth Implementation Plan>

[0141] Figure 11 This is a cross-sectional view illustrating an example of a solid-state imaging device 1C according to a fourth embodiment of the present technology. Figure 11 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0142] like Figure 11 As shown, in the solid-state imaging device 1C of the fourth embodiment, an anti-reflective unit (RIG) 69 with a moth-eye structure is provided on the back side of the stacked material section 30. The RIG 69 prevents the reflection of incident light.

[0143] <The Role and Effects of the Fourth Implementation Plan>

[0144] As described above, according to the fourth embodiment, by setting RIG 69, quantum efficiency can be further improved and glare can be suppressed by reducing surface reflection.

[0145] <Variations of the Fourth Implementation Plan>

[0146] Figure 12 This is a cross-sectional view illustrating an example of a solid-state imaging device 1C, a variant of the fourth embodiment of the present technology. Figure 12 In the figures, the same reference numerals are used to denote the figures described above. Figure 11 The same parts are omitted, and their detailed descriptions are omitted.

[0147] like Figure 12 As shown, the solid-state imaging device 1C of the fourth embodiment has a structure that removes the on-chip lens 50 provided for each pixel P.

[0148] <The Role and Effects of the Variations in the Fourth Implementation Plan>

[0149] As described above, according to the first variant of the fourth embodiment, surface reflections can be further reduced and glare suppressed by removing the on-chip lens 50.

[0150] <Fifth Implementation Plan>

[0151] Figure 13 This is a cross-sectional view illustrating an example of a solid-state imaging device 1D according to a fifth embodiment of the present technology. Figure 13 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0152] like Figure 13 As shown, in the solid-state imaging device 1D of the fifth embodiment, a transparent electrode 44 serving as the anode is disposed between the p-type trap region 61 and the on-chip lens 50.

[0153] The p-type well region 61 is electrically connected to the transparent electrode 44 and can be biased. This allows the transmission electric field on the back side to be increased.

[0154] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the n-type second electrode region 12 can be supplied to the cathode 42 from the logic circuit (not shown). Furthermore, in pixel P, bias adjustment of the p-type well region 61 can be achieved via the transparent electrode 44.

[0155] <The Role and Effects of the Fifth Implementation Plan>

[0156] As described above, according to the fifth embodiment, by providing the transparent electrode 44, the anode on the front side becomes unnecessary, thus expanding the multiplication region and increasing the multiplication probability. Furthermore, by increasing the transmission electric field on the back side, further improvements in jitter characteristics can be expected.

[0157] <Sixth Implementation Plan>

[0158] Figure 14 This is a cross-sectional view illustrating an example of a solid-state imaging device 1E according to a sixth embodiment of the present technology. Figure 14 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0159] like Figure 14 As shown, in the solid-state imaging device 1E of the sixth embodiment, a substrate 10, a stacked material section 30, a p-type well region 61, and an interlayer film 62 are stacked sequentially. In the stacked material section 30, a semiconductor material grown by crystal growth that matches the crystal lattice of the substrate 10 is used. For example, if gallium arsenide (GaAs) is used in the substrate 10, germanium (Ge) or gallium arsenide (GaAs) is used in the stacked material section 30. Furthermore, for example, if indium phosphide (InP) is used in the substrate 10, indium gallium arsenide (InGaAs) is used in the stacked material section 30.

[0160] <The Role and Effects of the Sixth Implementation Plan>

[0161] As described above, according to the sixth embodiment, by using a semiconductor material in the stacked material section 30 that matches the lattice of the substrate 10, defects at the bonding interface between the substrate 10 and the stacked material section 30 can be prevented.

[0162] <First Variation of the Sixth Implementation Plan>

[0163] Figure 15 This is a cross-sectional view illustrating an example of a solid-state imaging device 1E, a first variant of the sixth embodiment of the present technology. Figure 15 In the figures, the same reference numerals are used to denote the figures described above. Figure 14 The same parts are omitted, and their detailed descriptions are omitted.

[0164] like Figure 15 As shown, the stacked material section 31 of the first variant of the sixth embodiment has a multi-stack (quantum well) type structure.

[0165] <The Role and Effects of the First Variation of the Sixth Implementation Plan>

[0166] According to a first variant of the sixth embodiment, by controlling the band gap with a stacked material section 31 having a quantum well structure to improve the absorption efficiency of IR light, a specific wavelength can be effectively absorbed by the subband of the quantum well structure.

[0167] <Second Variation of the Sixth Implementation Plan>

[0168] Figure 16 This is a cross-sectional view illustrating an example of a solid-state imaging device 1E, a second variation of the sixth embodiment of the present technology. Figure 16 In the figures, the same reference numerals are used to denote the figures described above. Figure 14 The same parts are omitted, and their detailed descriptions are omitted.

[0169] like Figure 16 As shown, the stacked material section 32 of the second variant of the sixth embodiment has a quantum dot structure.

[0170] <The Role and Effects of the Second Variation of the Sixth Implementation Plan>

[0171] According to a second variation of the sixth embodiment, by controlling the band gap with a stacked material portion 32 having a quantum dot structure to improve the absorption efficiency of IR light, a specific wavelength can be effectively absorbed by the subband of the quantum dot structure.

[0172] <Seventh Implementation Plan>

[0173] Figure 17 This is a cross-sectional view illustrating an example of a solid-state imaging device 1F according to a seventh embodiment of the present technology. Figure 17 In the figures, the same reference numerals are used to denote the figures described above. Figure 2 The same parts are omitted, and their detailed descriptions are omitted.

[0174] like Figure 17 As shown, in the solid-state imaging device 1F of the seventh embodiment, a substrate 10, an n-type stacked material section 33, a p-type stacked material section 34, a p-type well region 61, and an interlayer film 62 are stacked in sequence.

[0175] SPAD elements 5 are formed for each pixel P. SPAD element 5 includes linear multiplication units 6 disposed in n-type stacked material sections 33 and p-type stacked material sections 34, and Geiger multiplication units 4 disposed in the substrate 10. The linear multiplication unit 6 absorbs light incident from the on-chip lens 50 via the interlayer film 62 and the p-type well region 61 to generate electrons (charge carriers) and linearly multiplies the electrons. Then, the linear multiplication unit 6 transfers the linearly multiplied electrons to the Geiger multiplication unit 4 via an electric field.

[0176] The linear multiplication unit 6 forms a pn junction with the n-type stacked material section 33 and the p-type stacked material section 34, and a linear multiplication region is formed at the interface of the pn junction. In the linear multiplication region, an electron generated by a photon is linearly multiplied by applying a slightly higher negative voltage close to the breakdown voltage to the n-type stacked material section 33.

[0177] <The Role and Effects of the Seventh Implementation Plan>

[0178] As described above, according to the seventh embodiment, a higher PDE is achieved by employing a two-stage multiplication structure in which linear multiplication is performed by linear multiplication unit 6 without relying on Geiger multiplication performed solely by Geiger multiplication unit 4.

[0179] <Variations of the Seventh Implementation Plan>

[0180] Figure 18 This is a cross-sectional view illustrating an example of a solid-state imaging device 1E, a variant of the seventh embodiment of this technology. Figure 18 In the figures, the same reference numerals are used to denote the figures described above. Figure 17 The same parts are used, and their detailed descriptions are omitted.

[0181] like Figure 18 As shown, in a variant of the seventh embodiment, a transition layer 20 is sandwiched between the substrate 10 and the n-type stacked material portion 33.

[0182] <The Role and Effects of the Variant of the Seventh Implementation Plan>

[0183] Even in a variant of the seventh embodiment, similar effects and functions as described above can be achieved, and the substrate 10 and the n-type stacked material section 33 can be stacked by using lattice-mismatched semiconductor materials.

[0184] <Eighth Implementation Plan>

[0185] Figure 19 This is a cross-sectional view illustrating an example of a solid-state imaging device 1G according to the eighth embodiment of the present technology. Figure 19 In the figures, the same reference numerals are used to denote the figures described above. Figure 5 The same parts are omitted, and their detailed descriptions are omitted.

[0186] like Figure 19As shown, in the solid-state imaging device 1G of the eighth embodiment, a substrate 10, a stacked material section 70, a p-type well region 61, and an interlayer film 62 are stacked sequentially. In the stacked material section 70, a semiconductor material made of a nanocrystalline film that matches the crystal lattice of the substrate 10 is used. For example, palladium sulfide (PdS), CsPbI3, CuGaSe2, CuInSe2, etc., are used as semiconductor materials included in the stacked material section 70, relative to silicon. This is similar to gallium arsenide (GaAs) and indium phosphide (InP).

[0187] In the eighth embodiment, the pixel isolation unit 60B has a trench TrB (hereinafter referred to as the front trench TrB) only on the substrate 10 side. The front trench TrB is obtained by sandwiching a metal film 65 from both sides with an insulating film 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. Then, the front trench TrB extends from the front side of the substrate 10 to the back side of the substrate 10.

[0188] <The Role and Effects of the Eighth Implementation Plan>

[0189] As described above, according to the eighth embodiment, by using nanocrystals in the stacked material section 70, an absorption efficiency no less than that of ordinary crystals can be obtained. Furthermore, the solid-state imaging device 1G can be easily manufactured by processing only the substrate 10 to form the pixel isolation unit 60B.

[0190] <First Variation of the Eighth Implementation Plan>

[0191] Figure 20 This is a cross-sectional view illustrating an example of a solid-state imaging device 1G, a first variant of the eighth embodiment of the present technology. Figure 20 In the figures, the same reference numerals are used to denote the figures described above. Figure 19 The same parts are omitted, and their detailed descriptions are omitted.

[0192] like Figure 20 As shown, in the first variant of the eighth embodiment, the pixel isolation unit 60B is provided with a full trench TrA. The full trench TrA is obtained by sandwiching a metal film 63 from both sides with an insulating film 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. Then, the full trench TrA extends from the front side of the substrate 10 to the back side of the stacked material portion 70.

[0193] <The Role and Effects of the First Variation of the Eighth Implementation Plan>

[0194] As described above, according to the first variant of the eighth embodiment, light leakage to adjacent pixel P can be prevented.

[0195] <Second Variation of the Eighth Implementation Plan>

[0196] Figure 21This is a cross-sectional view illustrating an example of a solid-state imaging device 1G, a second variant of the eighth embodiment of the present technology. Figure 21 In the figures, the same reference numerals are used to denote the figures described above. Figure 19 The same parts are omitted, and their detailed descriptions are omitted.

[0197] like Figure 21 As shown, the pixel isolation unit 60F of the second variant does not have a full trench TrA.

[0198] According to this second variation of the eighth implementation plan, similar effects and functions as those of the eighth implementation plan can also be obtained.

[0199] <Ninth Implementation Plan>

[0200] Figure 22 This is a cross-sectional view illustrating an example of a solid-state imaging device 1H according to a ninth embodiment of the present technology. Figure 22 In the figures, the same reference numerals are used to denote the figures described above. Figure 19 The same parts are omitted, and their detailed descriptions are omitted.

[0201] like Figure 22 As shown, in the solid-state imaging device 1H of the ninth embodiment, a transparent electrode 44 serving as an anode is provided between the stacked material section 70 and the on-chip lens 50.

[0202] The stacked material section 70 is electrically connected to the transparent electrode 44 and is capable of bias adjustment. This allows the transmission electric field on the back side to be increased.

[0203] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the n-type second electrode region 12 can be supplied to the cathode 42 from the logic circuit (not shown). Furthermore, in pixel P, bias adjustment of the stacked material section 70 can be achieved via the transparent electrode 44.

[0204] <The Role and Effects of the Ninth Implementation Plan>

[0205] As described above, according to the ninth embodiment, by providing the transparent electrode 44, the anode on the front side becomes unnecessary, thus expanding the multiplication region and increasing the multiplication probability. Furthermore, by increasing the transmission electric field on the back side, further improvements in jitter characteristics can be expected.

[0206] <First Variation of the Ninth Implementation Plan>

[0207] Figure 23 This is a cross-sectional view illustrating an example of a solid-state imaging device 1H, a first variant of the ninth embodiment of the present technology. Figure 23 In the figures, the same reference numerals are used to denote the figures described above. Figure 22 The same parts are omitted, and their detailed descriptions are omitted.

[0208] like Figure 23 As shown, in the first variant of the ninth embodiment, the pixel isolation unit 60B is provided with a full trench TrA. The full trench TrA is obtained by sandwiching a metal film 63 from both sides with an insulating film 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. Then, the full trench TrA extends from the front side of the substrate 10 to the back side of the stacked material portion 70.

[0209] <The Role and Effects of the First Variation of the Ninth Implementation Plan>

[0210] As described above, according to the first variant of the ninth embodiment, similar effects and functions as those of the ninth embodiment can be obtained.

[0211] <Second Variation of the Ninth Implementation Plan>

[0212] Figure 24 This is a cross-sectional view illustrating an example of a solid-state imaging device 1H, a second variation of the ninth embodiment of the present technology. Figure 24 In the figures, the same reference numerals are used to denote the figures described above. Figure 22 The same parts are omitted, and their detailed descriptions are omitted.

[0213] like Figure 24 As shown, the pixel isolation unit 60F of the second variant does not have a full trench TrA.

[0214] According to this second variant of the ninth implementation scheme, similar effects and functions as those of the ninth implementation scheme can also be obtained.

[0215] <Tenth Implementation Plan>

[0216] Figure 25 This is a cross-sectional view illustrating an example of a solid-state imaging device 1I according to the tenth embodiment of the present technology. Figure 25 In the figures, the same reference numerals are used to denote the figures described above. Figure 22 The same parts are omitted, and their detailed descriptions are omitted.

[0217] like Figure 25 As shown, in the solid-state imaging device 1I of the tenth embodiment, a substrate 10, an n-type stacked material portion 71, a p-type stacked material portion 72 and a transparent electrode 44 are stacked in sequence.

[0218] SPAD elements 5 are formed for each pixel P. SPAD element 5 includes linear multiplication units 6 disposed in n-type stacked material sections 71 and p-type stacked material sections 72, and Geiger multiplication units 4 disposed in the substrate 10. The linear multiplication unit 6 absorbs light incident from the on-chip lens 50 via the transparent electrode 44 to generate electrons (charge carriers) and linearly multiplies the electrons. Then, the linear multiplication unit 6 transfers the linearly multiplied electrons to the Geiger multiplication unit 4 via an electric field.

[0219] The linear multiplication unit 6 forms a pn junction with the n-type stacked material section 71 and the p-type stacked material section 72, and a linear multiplication region is formed at the interface of the pn junction. In the linear multiplication region, electrons generated by a photon are linearly multiplied by a negative voltage that is slightly higher than the breakdown voltage applied to the n-type stacked material section 71.

[0220] <The Role and Effects of the Tenth Implementation Plan>

[0221] As described above, according to the tenth embodiment, similar effects and functions as those of the ninth embodiment can be obtained, and a higher PDE can be achieved by employing a two-stage multiplication structure in which linear multiplication is performed by linear multiplication unit 6 without relying solely on Geiger multiplication by Geiger multiplication unit 4.

[0222] <First Variation of the Tenth Implementation Plan>

[0223] Figure 26 This is a cross-sectional view illustrating an example of a solid-state imaging device 1I, a first variant of the tenth embodiment of the present technology. Figure 26 In the figures, the same reference numerals are used to denote the figures described above. Figure 25 The same parts are omitted, and their detailed descriptions are omitted.

[0224] like Figure 26 As shown, in the first variant of the tenth embodiment, the pixel isolation unit 60B is provided with a full trench TrA. The full trench TrA is obtained by sandwiching a metal film 63 from both sides with an insulating film 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. Then, the full trench TrA extends from the front side of the substrate 10 to the back side of the stacked material portion 30.

[0225] <The Role and Effects of the First Variation of the Tenth Implementation Plan>

[0226] As described above, according to the first variant of the tenth embodiment, similar effects and functions as those of the tenth embodiment can be obtained.

[0227] <Second Variation of the Tenth Implementation Plan>

[0228] Figure 27This is a cross-sectional view illustrating an example of a solid-state imaging device 1I, a second variation of the tenth embodiment of the present technology. Figure 27 In the figures, the same reference numerals are used to denote the figures described above. Figure 25 The same parts are omitted, and their detailed descriptions are omitted.

[0229] like Figure 27 As shown, the pixel isolation unit 60F of the second variant does not have a full trench TrA.

[0230] According to this second variation of the tenth implementation plan, similar effects and functions as those of the tenth implementation plan can also be obtained.

[0231] <Eleventh Implementation Plan>

[0232] In the eleventh embodiment of this technology, the copper (Cu)-copper (Cu) junctions of the readout circuits formed for each pixel become unnecessary, and manufacturing costs are reduced.

[0233] Figure 28 This is a cross-sectional view illustrating an example of a solid-state imaging device 1J according to the eleventh embodiment of the present technology. Figure 28 In the figures, the same reference numerals are used to denote the figures described above. Figure 25 The same parts are omitted, and their detailed descriptions are omitted.

[0234] like Figure 28 As shown, in the solid-state imaging device 1J of the eleventh embodiment, a p-type substrate 81, an n-type substrate 82, an n-type stacked material portion 71, a p-type stacked material portion 72, and a transparent electrode 44 are stacked in sequence.

[0235] The p-type substrate 81 and the n-type substrate 82 are equipped with electronic readout circuits. An n-type electrode region 811, an n-type well region 812, and a p-type electrode region 813 are formed in the p-type substrate 81. An n-type contact region 821 is formed in the n-type substrate 82.

[0236] The n-type contact region 821 is electrically connected to the n-type stacked material section 71 and serves as a cathode. Furthermore, the n-type contact region 821 is electrically connected to the n-type electrode region 811. The n-type electrode region 811 is connected to a logic circuit (not shown).

[0237] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the n-type stacked material portion 71 can be supplied from the logic circuit (not shown) to the n-type contact region 821, which serves as the cathode. Furthermore, in pixel P, bias adjustment of the p-type stacked material portion 72 can be achieved via the transparent electrode 44.

[0238] In the solid-state imaging device 1J with the above-described structure, light is applied, and the applied light passes through the on-chip lens 50. The transmitted light is photoelectrically converted by the n-type stacked material portion 71 and the p-type stacked material portion 72, thereby generating and multiplying electrons. Then, the multiplied electrons are read out from the n-type contact region 821, which serves as the cathode, and output as a pixel signal via the n-type electrode region 811 of the p-type substrate 81 through the vertical signal line 153 shown in FIG1.

[0239] <The Role and Effects of the Eleventh Implementation Plan>

[0240] As described above, according to the eleventh embodiment, by forming electronic readout circuits in the p-type substrate 81 and the n-type substrate 82, the cost of copper (Cu)-copper (Cu) bonding can be reduced.

[0241] <Variations on the Eleventh Implementation Plan>

[0242] Figure 29 This is a cross-sectional view illustrating an example of a solid-state imaging device 1J, a variant of the eleventh embodiment of the present technology. Figure 29 In the figures, the same reference numerals are used to denote the figures described above. Figure 28 The same parts are omitted, and their detailed descriptions are omitted.

[0243] like Figure 29 As shown, in a variant of the eleventh embodiment, back grooves TrC are provided in the n-type stacked material section 71 and the p-type stacked material section 72. The back grooves TrC are obtained by sandwiching the metal film 66 from both sides using an insulating film 64.

[0244] <The Role and Effects of Variations to the Eleventh Implementation Plan>

[0245] As described above, a variant of the eleventh embodiment can achieve similar effects and outcomes as described in the eleventh embodiment.

[0246] <Implementation Plan Twelfth>

[0247] Figure 30 This is a cross-sectional view illustrating an example of a solid-state imaging device 1K according to the twelfth embodiment of the present technology. Figure 30 In the figures, the same reference numerals are used to denote the figures described above. Figure 28 The same parts are omitted, and their detailed descriptions are omitted.

[0248] like Figure 30 As shown, in the solid-state imaging device 1K of the twelfth embodiment, a p-type substrate 81, an n-type substrate 82, a p-type stacked material portion 72, an n-type stacked material portion 71, and a transparent electrode 45 serving as a cathode are stacked in sequence.

[0249] The p-type substrate 81 and the n-type substrate 82 are equipped with hole readout circuits. A p-type contact region 822 is formed in the n-type substrate 82.

[0250] The p-type contact region 822 is electrically connected to the p-type stacked material portion 72 and serves as an anode. Furthermore, the p-type contact region 822 is electrically connected to the p-type electrode region 813 formed in the n-type well region 812. The p-type electrode region 813 is connected to a logic circuit (not shown).

[0251] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the p-type stacked material portion 72 can be supplied from a logic circuit (not shown) to the p-type contact region 822, which serves as the anode. Furthermore, in pixel P, bias adjustment of the n-type stacked material portion 71 can be achieved via the transparent electrode 45.

[0252] In the solid-state imaging device 1K with the above-described structure, light is applied, and the applied light passes through the on-chip lens 50. The transmitted light is photoelectrically converted by the n-type stacked material portion 71 and the p-type stacked material portion 72, thereby generating and multiplying holes. Then, the multiplied holes are read out from the p-type contact region 822, which serves as the anode, and output as a pixel signal via the p-type electrode region 813 of the p-type substrate 81 through the vertical signal line 153 shown in FIG1.

[0253] <The Role and Effects of the Twelfth Implementation Plan>

[0254] As described above, according to the twelfth embodiment, by forming hole readout circuits in the p-type substrate 81 and the n-type substrate 82, the cost of copper (Cu)-copper (Cu) bonding can be reduced.

[0255] <Variations of the Twelfth Implementation Plan>

[0256] Figure 31 This is a cross-sectional view illustrating an example of a solid-state imaging device 1K, a variant of the twelfth embodiment of the present technology. Figure 31 In the figures, the same reference numerals are used to denote the figures described above. Figure 30 The same parts are omitted, and their detailed descriptions are omitted.

[0257] like Figure 31 As shown, in a variant of the twelfth embodiment, back grooves TrC are provided in the n-type stacked material section 71 and the p-type stacked material section 72. The back grooves TrC are obtained by sandwiching the metal film 66 from both sides using an insulating film 64.

[0258] <The Role and Effects of the Variant of the Twelfth Implementation Plan>

[0259] As described above, a variant of the twelfth embodiment can achieve similar effects and outcomes as described in the twelfth embodiment above.

[0260] <Thirteenth Implementation Plan>

[0261] Figure 32 This is a cross-sectional view illustrating an example of a solid-state imaging device 1L according to the thirteenth embodiment of the present technology. Figure 32 In the figures, the same reference numerals are used to denote the figures described above. Figure 28 The same parts are omitted, and their detailed descriptions are omitted.

[0262] like Figure 32 As shown, in the solid-state imaging device 1L of the thirteenth embodiment, a p-type substrate 81, an n-type substrate 82, an n-type stacked material portion 91, a p-type stacked material portion 92, and a transparent electrode 44 are stacked in sequence.

[0263] In the n-type stacked material section 91 and the p-type stacked material section 92, a semiconductor material made of an organic film that matches the lattice of the substrate 10 is used. For example, in the semiconductor materials included in the n-type stacked material section 91 and the p-type stacked material section 92, F6-OC6F5 or the like is used for silicon.

[0264] The p-type substrate 81 and the n-type substrate 82 are equipped with electronic readout circuits. An n-type electrode region 811, an n-type well region 812, and a p-type electrode region 813 are formed in the p-type substrate 81. An n-type contact region 821 is formed in the n-type substrate 82.

[0265] The n-type contact region 821 is electrically connected to the n-type stacked material section 91 and serves as a cathode. Furthermore, the n-type contact region 821 is electrically connected to the n-type electrode region 811. The n-type electrode region 811 is connected to a logic circuit (not shown).

[0266] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the n-type contact region 821, which serves as the cathode, can be applied from the logic circuit (not shown). Furthermore, in pixel P, bias adjustment of the p-type stacked material section 92 can be achieved via the transparent electrode 44.

[0267] In the solid-state imaging device 1L with the above-described structure, light is applied, and the applied light passes through the on-chip lens 50. The transmitted light is photoelectrically converted by the n-type stacked material portion 91 and the p-type stacked material portion 92, thereby generating and multiplying electrons. Then, the multiplied electrons are read out from the n-type contact region 821, which serves as the cathode, and output as a pixel signal via the n-type electrode region 811 of the p-type substrate 81 through the vertical signal line 153 shown in FIG1.

[0268] <The Role and Effects of the Thirteenth Implementation Plan>

[0269] As stated above, according to the thirteenth implementation plan, similar effects and outcomes as those of the eleventh implementation plan can be achieved.

[0270] <Variations of the Thirteenth Implementation Plan>

[0271] Figure 33 This is a cross-sectional view illustrating an example of a solid-state imaging device 1L, a variant of the thirteenth embodiment of the present technology. Figure 33 In the figures, the same reference numerals are used to denote the figures described above. Figure 32 The same parts are omitted, and their detailed descriptions are omitted.

[0272] like Figure 33 As shown, in a variant of the thirteenth embodiment, back grooves TrC are provided in the n-type stacked material section 91 and the p-type stacked material section 92. The back grooves TrC are obtained by sandwiching the metal film 66 from both sides using an insulating film 64.

[0273] <The Role and Effects of the Variant of the Thirteenth Implementation Plan>

[0274] As described above, a variant of the thirteenth embodiment can achieve similar effects and outcomes as described in the thirteenth embodiment above.

[0275] <Fourteenth Implementation Plan>

[0276] Figure 34 This is a cross-sectional view illustrating an example of a solid-state imaging device 1M according to the fourteenth embodiment of the present technology. Figure 34 In the figures, the same reference numerals are used to denote the figures described above. Figure 32 The same parts are omitted, and their detailed descriptions are omitted.

[0277] like Figure 34 As shown, in the solid-state imaging device 1M of the fourteenth embodiment, a p-type substrate 81, an n-type substrate 82, a p-type stacked material portion 92, an n-type stacked material portion 91, and a transparent electrode 45 serving as a cathode are stacked sequentially.

[0278] The p-type substrate 81 and the n-type substrate 82 are equipped with hole readout circuits. A p-type contact region 822 is formed in the n-type substrate 82.

[0279] The p-type contact region 822 is electrically connected to the p-type stacked material portion 92 and serves as the anode. Furthermore, the p-type contact region 822 is electrically connected to the p-type electrode region 813 formed in the n-type well region 812. The p-type electrode region 813 is connected to a logic circuit (not shown).

[0280] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the p-type stacked material portion 92 can be supplied from the logic circuit (not shown) to the p-type contact region 822, which serves as the anode. Furthermore, in pixel P, bias adjustment of the n-type stacked material portion 91 can be achieved via the transparent electrode 45.

[0281] In the solid-state imaging device 1M having the above-described structure, light is applied, and the applied light passes through the on-chip lens 50. The transmitted light is photoelectrically converted by the n-type stacked material portion 91 and the p-type stacked material portion 92, thereby generating and multiplying holes. Then, the multiplied holes are read out from the p-type contact region 822, which serves as the anode, and output as a pixel signal via the p-type electrode region 813 of the p-type substrate 81 through the vertical signal line 153 shown in FIG1.

[0282] <The Role and Effects of the Fourteenth Implementation Plan>

[0283] As described above, according to the fourteenth embodiment, similar effects and functions can be achieved as described in the twelfth embodiment.

[0284] <Variations of the Fourteenth Implementation Plan>

[0285] Figure 35 This is a cross-sectional view illustrating an example of a solid-state imaging device 1M, a variant of the fourteenth embodiment of the present technology. Figure 35 In the figures, the same reference numerals are used to denote the figures described above. Figure 34 The same parts are omitted, and their detailed descriptions are omitted.

[0286] like Figure 35 As shown, in a variant of the fourteenth embodiment, back grooves are provided in the n-type stacked material section 91 and the p-type stacked material section 92. The back grooves are obtained by clamping the metal film 66 from both sides with an insulating film 64.

[0287] <The Role and Effects of the Variation of the Fourteenth Implementation Plan>

[0288] As described above, a variant of the fourteenth embodiment can achieve similar effects and outcomes as described in the fourteenth embodiment.

[0289] <Other Implementation Plans>

[0290] As described above, the present technology has been illustrated according to the first to fourteenth embodiments and their variations, but it should not be construed as limiting the present technology by the description and drawings that form part of this disclosure. By understanding the spirit of the technical content disclosed in the first to fourteenth embodiments above, those skilled in the art will realize that various alternative embodiments, examples, and operational techniques can be included in the present technology. Furthermore, the constructions disclosed in the first to fourteenth embodiments and their variations can be appropriately combined without contradiction. For example, constructions disclosed by multiple different embodiments can be combined, or constructions disclosed by multiple different variations of the same embodiment can be combined.

[0291] <Example of optical receiver construction>

[0292] The pixel P according to the first to fourteenth embodiments described above can be applied to, for example... Figure 36 The pixels of the light-receiving element shown.

[0293] Figure 36 It is a block diagram including the light receiving element of the aforementioned pixel P.

[0294] Figure 36 The light receiving element 5010 is provided with a pixel driving unit 5110, a pixel array 5120, a multiplexer (MUX) 5130, a time measurement unit 5140 and an input / output unit 5150.

[0295] The pixel array 5120 is constructed such that pixels 5210 are arranged in a two-dimensional matrix in both row and column directions. Each pixel 5210 detects incident photons and outputs a detection signal PFout representing the detection result as a pixel signal. Here, the row direction refers to the arrangement direction of pixels 5210 in a pixel row, i.e., the horizontal direction, and the column direction refers to the arrangement direction of pixels 5210 in a pixel column, i.e., the vertical direction. Figure 36 In the diagram, due to the limitations of the paper, a pixel array 5120 is shown with a pixel arrangement of 10 rows and 12 columns. However, the number of rows and columns of the pixel array 5120 is not limited to this and can be any number.

[0296] Pixel driving lines 5220 are horizontally routed for each pixel row relative to the matrix of pixels in pixel array 5120. Pixel driving lines 5220 transmit driving signals for driving pixels 5210. Pixel driving unit 5110 drives each pixel 5210 by supplying predetermined driving signals to each pixel 5210 via pixel driving lines 5220. Specifically, pixel driving unit 5110 performs control such that at a predetermined time corresponding to a light emission timing signal supplied externally via input / output unit 5150, some pixels 5210 of the plurality of pixels 5210 arranged in a two-dimensional matrix shape are set as active pixels, and the remaining pixels 5210 are set as passive pixels. Active pixels are pixels that detect photon incidence, and passive pixels are pixels that do not detect photon incidence. As a construction of pixel 5210, any of the first to fourteenth embodiments of pixel P described above can be adopted.

[0297] Note that in Figure 36 In the diagram, pixel driving line 5220 is illustrated as a single wiring, but it may include multiple wirings. One end of pixel driving line 5220 is connected to the output terminal corresponding to each pixel row of pixel driving unit 5110.

[0298] The MUX 5130 selects the output from the active pixel based on the switching between active and passive pixels in the pixel array 5120. Then, the MUX 5130 outputs the pixel signal input from the selected active pixel to the time measurement unit 5140.

[0299] Based on the pixel signals of the active pixels supplied from the MUX 5130 and the indicator light source ( Figure 37 The timing signal of the light emission timing of the light source (6320) is generated by the timing measurement unit 5140, which produces a count value corresponding to the time from the emission of light from the light source to the reception of light by the active pixel. The signal is transmitted via the input / output unit 5150 from an external source. Figure 37 The camera device 6220's controller 6420 supplies light-emitting timing signals.

[0300] Input / output unit 5150 outputs the count value of effective pixels supplied by time measurement unit 5140 as a pixel signal to the outside. Figure 37 (Signal processing circuit 6530). In addition, the input / output unit 5150 supplies externally supplied light emission timing signals to the pixel driving unit 5110 and the time measurement unit 5140.

[0301] <Example of a distance measuring system construction>

[0302] Figure 37 It shows including Figure 36 A block diagram illustrating the construction example of a ranging system implementation using the optical receiving element 5010.

[0303] The ranging system 6110 is, for example, a system that uses a Time-of-Flight (ToF) method to capture a distance image. Here, the distance image is an image that includes distance pixel signals based on the detected distance, where the distance is the distance from the ranging system 6110 to the subject in the depth direction detected for each pixel.

[0304] The ranging system 6110 is equipped with an illumination device 6210 and a camera device 6220.

[0305] The lighting device 6210 is equipped with a lighting controller 6310 and a light source 6320.

[0306] The lighting controller 6310 controls the light-emitting mode of the light source 6320 under the control of the controller 6420 of the camera device 6220. Specifically, the lighting controller 6310 controls the light-emitting mode of the light source 6320 according to the illumination code included in the illumination signal supplied from the controller 6420. For example, the illumination code has two values, 1 (high) and 0 (low), and when the value of the illumination code is 1, the lighting controller 6310 turns on the light source 6320, and when the value of the illumination code is 0, the light source 6320 is turned off.

[0307] The light source 6320 emits light within a predetermined wavelength range under the control of the lighting controller 6310. The light source 6320 includes, for example, an infrared laser diode. Note that the type of light source 6320 and the wavelength range of the irradiated light can be arbitrarily set according to the application of the ranging system 6110, etc.

[0308] The camera device 6220 is a device for receiving reflected light. Light (illumination light) applied from the illumination device 6210 is reflected by the subject 6120, subject 6130, etc. The camera device 6220 is provided with a camera unit 6410, a controller 6420, a display unit 6430, and a storage unit 6440.

[0309] The camera unit 6410 is equipped with a lens 6510, a light receiving element 6520, and a signal processing circuit 6530.

[0310] Lens 6510 forms an image of the incident light on the light-receiving surface of light-receiving element 6520. Note that lens 6510 can be arbitrarily constructed; for example, lens 6510 can be constructed from multiple lens groups.

[0311] The light receiving element 6520 includes, for example, a SPAD sensor for each pixel. Under the control of the controller 6420, the light receiving element 6520 receives reflected light from the subject 6120, subject 6130, etc., and supplies the resulting pixel signal to the signal processing circuit 6530. This pixel signal represents a digital count value obtained by counting the time from when the illumination device 6210 illuminates the light to when the light receiving element 6520 receives the light. A light emission timing signal indicating the moment when the light source 6320 emits light is also supplied from the controller 6420 to the light receiving element 6520. As a configuration of the light receiving element 6520, a sensor with the aforementioned pixel P is used. Figure 36 The optical receiving element 5010.

[0312] Signal processing circuit 6530 processes pixel signals supplied from light receiving element 6520 under the control of controller 6420. For example, signal processing circuit 6530 detects the distance to the subject for each pixel based on the pixel signals supplied from light receiving element 6520, and generates a distance image representing the distance to the subject for each pixel. Specifically, signal processing circuit 6530 obtains for each pixel the time (count value) from the emission of light from light source 6320 to the reception of light by each pixel of light receiving element 6520 multiple times (e.g., thousands of times). Signal processing circuit 6530 generates a histogram corresponding to the obtained time. Then, by detecting the peak value of the histogram, signal processing circuit 6530 determines the time until the light applied from light source 6320 is reflected back by subject 6120 or subject 6130, etc. Furthermore, signal processing circuit 6530 performs arithmetic operations based on the determined time and speed of light to obtain the distance to the subject. Signal processing circuit 6530 provides the generated distance image to controller 6420.

[0313] The controller 6420 includes, for example, control circuitry and a processor such as a field-programmable array (FPGA) or a digital signal processor (DSP). The controller 6420 controls the lighting controller 6310 and the light receiving element 6520. Specifically, the controller 6420 supplies an illumination signal to the lighting controller 6310 and a light emission timing signal to the light receiving element 6520. The light source 6320 emits illumination light according to the illumination signal. The light emission timing signal can be the illumination signal supplied to the lighting controller 6310. Furthermore, the controller 6420 supplies a distance image obtained from the camera unit 6410 to the display unit 6430 and causes the display unit 6430 to display the distance image. Additionally, the controller 6420 stores the distance image obtained from the camera unit 6410 in the storage unit 6440.

[0314] In addition, the controller 6420 outputs the distance image obtained from the camera unit 6410 to the outside.

[0315] The display unit 6430 includes, for example, a panel display device such as a liquid crystal display or an organic electroluminescent (EL) display.

[0316] Storage unit 6440 may include any storage device, storage medium, etc., and stores distance images, etc.

[0317] By employing the aforementioned pixel P structure in the light receiving element 5010 and ranging system 6110, a distance image achieving high photon detection efficiency (PDE) can be generated and output while preventing edge breakage.

[0318] <Example 1 of the application of electronic devices>

[0319] For example, the ranging system 6110 described above can be installed on electronic devices such as smartphones, tablets, mobile phones, personal computers, game consoles, televisions, wearable devices, digital cameras, and digital video cameras.

[0320] Figure 38 This is a block diagram showing a construction example of a smartphone as an electronic device equipped with a ranging system 6110.

[0321] like Figure 38 As shown, the smartphone 7010 is formed by connecting a ranging module 7020, a camera device 7030, a display 7040, a speaker 7050, a microphone 7060, a communication module 7070, a sensor unit 7080, a touch panel 7090, and a control unit 7100 via a bus 7110. Furthermore, the control unit 7100 executes programs via a CPU and functions as an application processing unit 7210 and an operating system processing unit 7220.

[0322] Figure 37 The ranging system 6110 is applied to the ranging module 7020. For example, the ranging module 7020 is arranged on the front of the smartphone 7010 and can measure the distance of the user of the smartphone 7010 to output the depth value of the surface shape of the user's face, hands, fingers, etc. as the ranging result.

[0323] The camera device 7030 is disposed on the front of the smartphone 7010 and captures images of the user of the smartphone 7010 as the subject. Note that, although not shown, the camera device 7030 may also be disposed on the back of the smartphone 7010.

[0324] The display 7040 displays the operation screen processed by the application processing unit 7210 and the operating system processing unit 7220, images captured by the camera device 7030, etc. For example, when speaking on the smartphone 7010, the speaker 7050 and the microphone 7060 output the other party's voice and collect the user's voice.

[0325] The communication module 7070 communicates via a communication network. The sensor unit 7080 senses speed, acceleration, proximity, etc., and the touch panel 7090 receives touch operations from the user on the operation screen displayed on the display 7040.

[0326] The application processing unit 7210 performs processing for various services provided by the smartphone 7010. For example, the application processing unit 7210 can perform the following processing: creating a face based on a depth map provided by the ranging module 7020 using computer graphics to virtually reproduce the user's facial expressions, and displaying the face on the display 7040. Furthermore, the application processing unit 7210 can perform processing, for example, creating three-dimensional shape data of an arbitrary solid subject based on a depth map provided by the ranging module 7020.

[0327] The operating system processing unit 7220 performs processing to implement the basic functions and operations of the smartphone 7010. For example, the operating system processing unit 7220 can perform processing to authenticate the user's face and unlock the smartphone 7010 based on the depth map provided by the ranging module 7020. Furthermore, based on the depth map provided by the ranging module 7020, the operating system processing unit 7220 can perform processing such as recognizing the user's gestures and inputting various operations based on those gestures.

[0328] In the smartphone 7010 constructed in this way, for example, a depth map can be generated with high precision and high speed by applying the aforementioned ranging system 6110. Therefore, the smartphone 7010 can detect ranging information more accurately.

[0329] <Application Examples of Electronic Device 2>

[0330] Figure 39 This is a block diagram illustrating a construction example of a camera device as an electronic device to which this technology is applied.

[0331] Figure 39 The imaging device 1000 is a video camera, digital camera, etc. The imaging device 1000 includes a lens group 1001, a solid-state imaging element 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, operation unit 1007, and power supply unit 1008 are interconnected via a bus 1009.

[0332] Lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of solid-state imaging element 1002. Solid-state imaging element 1002 is the solid-state imaging device of the first to fourteenth embodiments described above. Solid-state imaging element 1002 converts the amount of incident light of the image formed on the imaging surface by lens group 1001 for each pixel into an electrical signal, which is then supplied to DSP circuit 1003 as a pixel signal.

[0333] The DSP circuit 1003 performs predetermined image processing on the pixel signals supplied from the solid-state imaging element 1002, and supplies the processed image signals to the frame memory 1004 for temporary storage in each frame.

[0334] The display unit 1005 includes, for example, a panel display device such as a liquid crystal panel and an organic electroluminescent (EL) panel, and displays an image based on pixel signals for each frame temporarily stored in the frame memory 1004.

[0335] The recording unit 1006 includes a digital multifunction disc (DVD), flash memory, etc., and reads pixel signals for each frame temporarily stored in the frame memory 1004 for recording.

[0336] Under user operation, the operation unit 1007 issues operation commands for various functions of the camera device 1000. The power supply unit 1008 appropriately supplies power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007.

[0337] Electronic devices that utilize this technology are sufficient to be devices in which a solid-state camera is used as an image capturing unit (photoelectric conversion unit); in addition to the camera device 1000, there are also portable terminal devices with camera functions, copiers that use a solid-state camera as an image reading unit, etc.

[0338] <Examples of the use of solid-state imaging devices>

[0339] For example, the aforementioned solid-state camera device can be used to sense various types of light, such as visible light, infrared light, ultraviolet light, and X-rays, as described below.

[0340] - Devices that capture images for viewing, such as digital cameras and portable devices with camera functions.

[0341] - Devices for traffic purposes, such as onboard sensors for safe driving such as automatic stopping and driver status recognition, which capture images of the front, rear, surroundings, and interior of a car; monitoring cameras for monitoring moving vehicles and roads; and distance measuring sensors for measuring distances between vehicles.

[0342] - Devices used in home appliances, such as televisions, refrigerators, and air conditioners, capture the user's gestures and perform device operations based on those gestures.

[0343] - Devices used in healthcare, such as endoscopes and devices that perform angiography by receiving infrared light.

[0344] - Devices used for security, such as security surveillance cameras and personal authentication cameras.

[0345] - Devices used for beauty purposes, such as skin measurement instruments for photographing the skin and microscopes for photographing the scalp.

[0346] - Devices used for sports, such as action cameras and wearable cameras for sports purposes.

[0347] - Devices used in agriculture, such as cameras used to monitor the condition of fields and crops.

[0348] Note that the effects described in this specification are illustrative and not restrictive; other effects may also be present.

[0349] Note that this disclosure may also have the following construction. (1)

[0351] A semiconductor device comprising:

[0352] Multiple pixels, each containing an avalanche photodiode element that performs photoelectric conversion on incident light.

[0353] Each of the plurality of pixels is configured as follows:

[0354] A substrate comprising a first semiconductor material; and

[0355] The stacked portion is stacked on the light-incident side of the substrate and includes a second semiconductor material that is different from the first semiconductor material. (2)

[0357] According to the semiconductor device described in (1) above, the substrate is provided with

[0358] A multiplication unit includes a first electrode region of a first conductivity type disposed on a side of a substrate opposite to the light incident side, and a second electrode region of a second conductivity type disposed to form a pn junction with the first electrode region, wherein an avalanche multiplication region is formed at the interface of the pn junction. (3)

[0360] According to the semiconductor device described in (2) above, wherein,

[0361] The stacked portion is a light-absorbing layer, and

[0362] The multiplication unit is a Geiger multiplication unit that avalanche multiplies the charge carriers converted by the photoelectric absorption layer. (4)

[0364] According to the semiconductor device described in (2) above, wherein,

[0365] The stacked section is a linear multiplication unit that avalanche multiplication of photoelectric conversion carriers, and

[0366] The multiplication unit is a Geiger multiplication unit that performs avalanche multiplication of carriers multiplied by the linear multiplication unit. (5)

[0368] According to the semiconductor device described in (1) above, wherein,

[0369] The stacked section is a Geiger multiplier unit that avalanche multiplication of photoelectric conversion carriers, and

[0370] A readout circuit for reading the charge carriers multiplied by the Geiger multiplier unit is also formed on the substrate. (6)

[0372] According to the semiconductor device described in (3) or (4) above, the stacked portion uses a material capable of crystal growth as the second semiconductor material. (7)

[0374] According to the semiconductor device described in (6) above, the stacked portion has a stacked structure grown by crystal including a transition layer. (8)

[0376] According to the semiconductor device described in (6) above, the stacked portion has a stacked structure grown by crystal growth through lattice matching. (9)

[0378] According to the semiconductor device described in (8) above, the stacked structure grown by the lattice-matched crystal is a quantum well type or a quantum dot type stacked structure. (10)

[0380] The semiconductor device according to any one of (3) to (5) above, wherein the stacked portion uses nanocrystals as the second semiconductor material. (11)

[0382] The semiconductor device according to any one of (3) to (5) above, wherein the stacked portion uses an organic film as the second semiconductor material. (12)

[0384] The semiconductor device according to any one of (1) to (11) above further includes:

[0385] A pixel isolation unit is a unit that insulates and isolates multiple adjacent pixels from each other. (13)

[0387] According to the semiconductor device described in (12) above, the pixel isolation unit performs pixel isolation by forming a full trench from the substrate to the stacked portion. (14)

[0389] According to the semiconductor device described in (12) above, the pixel isolation unit performs pixel isolation by forming a back trench in the stacked portion. (15)

[0391] According to the semiconductor device described in (12) above, the pixel isolation unit performs pixel isolation by forming a front trench in the substrate. (16)

[0393] The semiconductor device according to any one of (11) to (15) above further includes:

[0394] An on-chip lens is disposed on the light-incident side of each of the plurality of pixels. (17)

[0396] The semiconductor device according to any one of (11) to (16) above, wherein the plurality of pixels are provided with anti-reflection units to prevent the incident light from being reflected. (18)

[0398] An electronic device comprising:

[0399] A semiconductor device, which includes:

[0400] Multiple pixels, each containing an avalanche photodiode element that performs photoelectric conversion on incident light.

[0401] Each of the plurality of pixels is configured as follows:

[0402] A substrate comprising a first semiconductor material; and

[0403] The stacked portion is stacked on the light-incident side of the substrate and includes a second semiconductor material that is different from the first semiconductor material.

[0404] List of reference numerals

[0405] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L, 1M Solid-state imaging devices

[0406] 2.5 SPAD components

[0407] 3 light absorption units

[0408] 4 Geiger multiplier units

[0409] 6 Linear multiplication units

[0410] 10, 81, 82 base plate

[0411] 11 First electrode region

[0412] 12 Second electrode region

[0413] 13 Avalanche Multiplication Zone

[0414] Tunnel regions 14, 61, 67, 68, and 812

[0415] 20 Transition Layer

[0416] 30, 31, 32, 33, 34, 70, 71, 72, 91, 92 Stacked Materials Department

[0417] 40 wiring layers

[0418] 41 Wiring

[0419] 42 Cathode

[0420] 43 Anode

[0421] 44, 45 Transparent electrodes

[0422] 50 lenses

[0423] Pixel isolation units: 60, 60A, 60B, 60C, 60D, 60E, 60F

[0424] 62-layer interlayer membrane

[0425] 63, 65, 66 metal film

[0426] 64 Insulating film

[0427] 102 Constant Current Source

[0428] 103 transistors

[0429] 104 inverter

[0430] Electrode regions 811 and 813

[0431] Contact areas 821 and 822

[0432] 1000, 6220, 7030 camera devices

[0433] 1001 Lens Group

[0434] 1002 Solid-state imaging element

[0435] 1003 DSP Circuit

[0436] 1004 Frame Memory

[0437] 1005 Display Unit

[0438] 1006 Recording Unit

[0439] 1007 Operation Unit

[0440] 1008 Power Supply Unit

[0441] 1009 bus

[0442] 5010 Optical Receiver Element

[0443] 5110 pixel driving unit

[0444] 5120 pixel array

[0445] 5140 Time Measurement Unit

[0446] 5150 Input / Output Unit

[0447] 5210, P pixels

[0448] 5220 pixel drive line

[0449] 6110 Distance Measuring System

[0450] 6120 Subject

[0451] 6130 Subject

[0452] 6210 Lighting fixtures

[0453] 6310 Lighting Controller

[0454] 6320 light source

[0455] 6410 camera unit

[0456] 6420 controller

[0457] 6430 display unit

[0458] 6440 storage units

[0459] 6510 Lens

[0460] 6520 Optical Receiver Element

[0461] 6530 Signal Processing Circuit

[0462] 7010 Smartphone

[0463] 7020 Distance Measuring Module

[0464] 7040 monitor

[0465] 7050 speaker

[0466] 7060 microphone

[0467] 7070 Communication Module

[0468] 7080 sensor unit

[0469] 7090 Touch Panel

[0470] 7100 Control Unit

[0471] 7110 bus

[0472] 7210 Application Processing Unit

[0473] 7220 Operating System Processing Unit

[0474] TrA full trench

[0475] TrB front trench

[0476] TrC back groove.

Claims

1. A semiconductor device comprising: Multiple pixels, each containing an avalanche photodiode element that performs photoelectric conversion on incident light; Each of the plurality of pixels is configured as follows: The substrate includes a first semiconductor material; and A stacked portion, which is stacked on the light-incident side of the substrate, and includes a second semiconductor material different from the first semiconductor material. The substrate is provided with: A multiplication unit includes a first electrode region of a first conductivity type disposed on a surface of the substrate opposite to the surface of the light incident side, and a second electrode region of a second conductivity type configured to form a pn junction with the first electrode region, wherein an avalanche multiplication region is formed at the interface of the pn junction. The stacked section is a linear multiplication unit that avalanche multiplication of photoelectric conversion carriers, and The multiplication unit is a Geiger multiplication unit that performs avalanche multiplication of carriers multiplied by the linear multiplication unit.

2. The semiconductor device according to claim 1, wherein, The stacked portion uses a material capable of crystal growth as the second semiconductor material.

3. The semiconductor device according to claim 2, wherein, The stacked portion has a stacked structure grown by crystals including a transition layer.

4. The semiconductor device according to claim 2, wherein, The stacked portion has a stacked structure grown by crystal growth through lattice matching.

5. The semiconductor device according to claim 4, wherein, The stacked structure grown by lattice matching is a quantum well type or a quantum dot type stacked structure.

6. The semiconductor device according to claim 1, wherein, The stacked portion uses nanocrystals as the second semiconductor material.

7. The semiconductor device according to claim 1, wherein, The stacked portion uses an organic film as the second semiconductor material.

8. The semiconductor device according to any one of claims 1 to 7, comprising: A pixel isolation unit that insulates and isolates adjacent pixels from each other.

9. The semiconductor device according to claim 8, wherein, The pixel isolation unit performs pixel isolation through a full trench formed from the substrate to the stacked portion.

10. The semiconductor device according to claim 8, wherein, The pixel isolation unit performs pixel isolation by forming a back trench in the stack.

11. The semiconductor device according to claim 8, wherein, The pixel isolation unit performs pixel isolation by forming a front trench in the substrate.

12. The semiconductor device according to any one of claims 9 to 11, comprising: An on-chip lens is disposed on the light-incident side of each of the plurality of pixels.

13. The semiconductor device according to any one of claims 9 to 11, wherein, The plurality of pixels are provided with anti-reflection units to prevent the incident light from being reflected.

14. An electronic device comprising a semiconductor device according to any one of claims 1 to 13.

Images