Display substrate and manufacturing method thereof, and display device

Abstract

The embodiments of the present disclosure disclose a display substrate and a manufacturing method thereof, and a display device, comprising: a substrate having a routing area; a first routing layer located on the substrate, the first routing layer including a plurality of first routing lines arranged at intervals in the routing area, and a distance between adjacent first routing lines being less than 2 um; an insulating layer located on a side of the first routing layer away from the substrate, the insulating layer having a plurality of first via holes corresponding to each first routing line; a first flat layer located on a side of the insulating layer away from the substrate, the first flat layer having second via holes corresponding to each first via hole, and the second via holes at least partially overlap with the first via holes.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the rapid development of smartphones, not only are smartphones required to have beautiful appearance, but they are also required to provide users with a better visual experience. Major manufacturers have begun to increase the screen-to-body ratio on smartphones, making full-screen a new competitive point for smartphones. With the development of full-screen phones, the demand for improved performance and functions is also increasing day by day. Under-screen cameras can bring a sense of visual and user experience impact to a certain extent without affecting the high screen-to-body ratio. Summary of the invention

[0003] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0004] A substrate having a routing area;

[0005] A first routing layer, located on the substrate, wherein the first routing layer comprises a plurality of first routing lines arranged at intervals in the routing area, and a distance between adjacent first routing lines is less than 2 um;

[0006] An insulating layer, located on a side of the first wiring layer away from the substrate, the insulating layer having a plurality of first via holes corresponding to each of the first wirings;

[0007] The first flat layer is located on a side of the insulating layer away from the substrate, and the first flat layer has second via holes corresponding to the first via holes, and the second via holes at least partially overlap with the first via holes.

[0008] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, the insulating layer includes a plurality of independent sub-insulating layers corresponding to each of the first wirings, the sub-insulating layers have the first via holes, and the line width of the first wiring is less than or equal to 2 um.

[0009] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, the distance between adjacent first wirings is 0.8um-1.8um, and the line width of the first wiring is 1.0um-1.8um.

[0010] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, the distance between adjacent first wirings is 1.2-1.6 um, and the line width of the first wiring is 1.2 um-1.6 um.

[0011] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it includes a display area and a frame area, the display area includes a first display area and a second display area, and the transmittance of the first display area is greater than the transmittance of the second display area;

[0012] The first display area includes a plurality of sub-pixels distributed in an array, the sub-pixels include a light-emitting device and a pixel circuit, the pixel circuit is located in the border area adjacent to the first display area, or the second display area has a transition area adjacent to the first display area, the pixel circuit is located in the transition area;

[0013] The wiring area is at least partially located in the first display area, and the first wiring layer is located between the light emitting device and the pixel circuit;

[0014] The first wiring is electrically connected to the anode of the light emitting device through the corresponding first via hole and the second via hole.

[0015] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, it further includes a second flat layer located between the pixel circuit and the first wiring layer, and the second flat layer has a plurality of fourth via holes corresponding to the first wiring;

[0016] The first wiring is electrically connected to the pixel circuit through the corresponding fourth via hole.

[0017] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the material of the first wiring includes at least one of ITO, a-Si, IZO, and IGZO.

[0018] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it includes a display area and a frame area, the display area includes a plurality of signal lines, and the frame area includes the routing area;

[0019] The first wiring is used to electrically connect the corresponding signal line.

[0020] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it includes a gate metal layer and a source-drain metal layer sequentially formed on the substrate, and the first wiring layer is located in the gate metal layer or the source-drain metal layer.

[0021] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, it further includes a second wiring layer located between the insulating layer and the first flat layer, and the second wiring layer includes a plurality of second wirings arranged at intervals in the wiring area;

[0022] The insulating layer is arranged to form a groove between adjacent first wirings, and the second wiring is at least located in the groove.

[0023] Optionally, in the above-mentioned display substrate provided by an embodiment of the present disclosure, a width of an orthographic projection of the second wiring on the substrate is smaller than a width of an orthographic projection of the insulating layer between adjacent first via holes on the substrate.

[0024] Optionally, in the above-mentioned display substrate provided by an embodiment of the present disclosure, an orthographic projection of the second wiring on the substrate substantially overlaps with an orthographic projection of a gap between adjacent first wirings on the substrate.

[0025] Optionally, in the above display substrate provided by the embodiment of the present disclosure, the width of the first wiring is greater than or equal to 1.5um, and the width of the first wiring is less than 2um; the maximum width of the first via hole is greater than or equal to 1.1um, and the maximum width of the first via hole is less than 1.6um;

[0026] The orthographic projection of the first trace on the substrate has a first annular side, the orthographic projection of the first via on the substrate has a second annular side, and the distance between the first annular side and the second annular side is greater than or equal to 0.2 um.

[0027] Optionally, in the above-mentioned display substrate provided by an embodiment of the present disclosure, the first planar layer has third via holes corresponding to each of the second wirings.

[0028] Optionally, in the above-mentioned display substrate provided by an embodiment of the present disclosure, the sum of the thickness of the second wiring and the thickness of the insulating layer is substantially the same as the thickness of the first wiring.

[0029] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it includes a display area and a frame area, the display area includes a first display area and a second display area, and the transmittance of the first display area is greater than the transmittance of the second display area;

[0030] The first display area includes a plurality of sub-pixels distributed in an array, the sub-pixels include a light-emitting device and a pixel circuit, the pixel circuit is located in the border area adjacent to the first display area, or the second display area has a transition area adjacent to the first display area, the pixel circuit is located in the transition area;

[0031] The wiring area is at least partially located in the first display area, and the first wiring layer and the second wiring layer are located between the anode of the light-emitting device and the pixel circuit;

[0032] The first wiring is electrically connected to the anode of the light-emitting device through the corresponding first via hole and the second via hole, and the second wiring is electrically connected to the anode of the light-emitting device through the third via hole.

[0033] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, it further includes a second flat layer located between the pixel circuit and the first wiring layer, the second flat layer has a plurality of fourth via holes corresponding to the first wiring and the second wiring; the insulating layer has a fifth via hole corresponding to each of the second wirings;

[0034] The first wiring is electrically connected to the pixel circuit through the corresponding fourth via hole, and the second wiring is electrically connected to the pixel circuit through the corresponding fourth via hole and the fifth via hole.

[0035] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the material of the first wiring and the material of the second wiring both include at least one of ITO, a-Si, IZO, and IGZO.

[0036] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it includes a display area and a frame area, the display area includes a plurality of signal lines, and the frame area includes the routing area;

[0037] The first wiring is used to electrically connect the corresponding signal line, and the second wiring is used to electrically connect the corresponding signal line.

[0038] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it includes a gate metal layer and a source-drain metal layer sequentially formed on the substrate, and the first wiring layer is located in the gate metal layer or the source-drain metal layer.

[0039] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the thickness of the insulating layer is 100 angstroms to 1200 angstroms.

[0040] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the thickness of the insulating layer is 500 angstroms to 1000 angstroms.

[0041] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the thickness of the insulating layer is 700 angstroms to 800 angstroms.

[0042] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the material of the insulating layer includes one or a combination of SiNx and SiOx.

[0043] On the other hand, an embodiment of the present disclosure further provides a method for manufacturing any of the above display substrates, comprising:

[0044] Providing a substrate; the substrate having a wiring area;

[0045] A first routing layer and an insulating layer are formed on the substrate; the first routing layer includes a plurality of independently arranged first routing lines in the routing area, the insulating layer is located on a side of the first routing layer away from the substrate, and the insulating layer has a plurality of first vias corresponding to each of the first routing lines;

[0046] A first flat layer is formed on a side of the insulating layer facing away from the substrate; the first flat layer has second via holes corresponding to the first via holes, and the second via holes at least partially overlap with the first via holes.

[0047] Optionally, in the above manufacturing method provided in the embodiment of the present disclosure, forming a first wiring layer and an insulating layer on the substrate specifically includes:

[0048] Depositing a first conductive layer in a routing region of the substrate;

[0049] Depositing an insulating layer on a side of the first conductive layer away from the substrate, and patterning the insulating layer to form a patterned insulating layer;

[0050] Using the patterned insulating layer as a mask, etching the first conductive layer to form a plurality of independently arranged first wirings;

[0051] Depositing a first flat layer on a side of the patterned insulating layer away from the substrate, and patterning the first flat layer to form second via holes corresponding to the first wirings;

[0052] The patterned insulating layer is etched using the first planar layer having the second via hole as a mask to form a first via hole corresponding to the second via hole.

[0053] Optionally, in the above manufacturing method provided in the embodiment of the present disclosure, forming a first wiring layer and an insulating layer on the substrate specifically includes:

[0054] Depositing a first conductive layer in a routing region of the substrate;

[0055] Patterning the first conductive layer to form a plurality of independently arranged first wirings;

[0056] Depositing an insulating layer on a side of the first conductive layer on which the plurality of first wirings are formed, away from the substrate; the insulating layer is arranged to form a groove between adjacent first wirings;

[0057] Depositing a second conductive layer on a side of the insulating layer away from the substrate, and patterning the second conductive layer to form a plurality of second wirings at least located in the corresponding grooves; wherein the thickness of the second conductive layer before patterning is greater than the thickness of the first conductive layer before patterning;

[0058] Depositing a first flat layer on a side of the second conductive layer on which the plurality of second wirings are formed, which is away from the substrate, and patterning the first flat layer to form second via holes corresponding to the first wirings and third via holes corresponding to the second wirings;

[0059] The insulating layer is etched using the first planar layer having the second via hole and the third via hole as a mask to form a first via hole corresponding to the second via hole.

[0060] Optionally, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, the thickness of the second conductive layer before composition is approximately 200 angstroms greater than the thickness of the first conductive layer before composition, and the sum of the thickness of the second routing line and the thickness of the insulating layer is approximately the same as the thickness of the first routing line.

[0061] Optionally, the above manufacturing method provided in the embodiment of the present disclosure further includes:

[0062] A plurality of anodes are formed on a side of the first flat layer where the second via hole is formed, which is away from the substrate. Each of the anodes is electrically connected to the first wiring through the corresponding second via hole and the first via hole.

[0063] On the other hand, an embodiment of the present disclosure further provides a display device, comprising any of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A schematic diagram of a top view structure of a display substrate provided in an embodiment of the present disclosure;

[0065] Figure 2 A schematic diagram of the line width and line spacing of a routing layer produced by a photoresist process in the related art;

[0066] Figure 3 A schematic diagram of the structure of a display substrate provided in the related art;

[0067] Figure 4 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0068] Figure 5 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0069] Figure 6 A schematic diagram of the line width and line spacing of a routing layer manufactured by an insulating layer process according to an embodiment of the present disclosure;

[0070] Figure 7 A schematic diagram of a top view structure of another display substrate provided in an embodiment of the present disclosure;

[0071] Figure 8A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0072] Fig. 9 A schematic diagram of a top view structure of another display substrate provided in an embodiment of the present disclosure;

[0073] Fig.10 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0074] Fig.11 for Fig.10 A top view of the first and second routing lines;

[0075] Fig.12 A schematic diagram of a top view structure of another display substrate provided in an embodiment of the present disclosure;

[0076] Fig.13 A schematic flow chart of a method for manufacturing a display substrate provided in an embodiment of the present disclosure;

[0077] Figures 14A-14H For production Figure 4 The schematic cross-sectional view of the display substrate after each step is performed;

[0078] Figure 15A-15I For production Figure 5 The schematic cross-sectional view of the display substrate after each step is performed is shown. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0080] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "Include" or "comprising" and other similar words used in the present disclosure mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0081] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0082] In related technologies, such as Figure 1 As shown, the under-screen camera technology generally sets a first display area AA1 and a second display area AA2 in the display area AA, wherein the second display area AA2 occupies most of the display area, and the first display area AA1 occupies a smaller part of the display area, and the first display area AA1 is where the under-screen camera is placed. The under-screen camera means that the front camera is located below the screen but does not affect the screen display function. When the front camera is not in use, the screen above the camera can still display the image normally. So from the appearance, the under-screen camera will not have any camera holes, and the full-screen display effect is truly achieved. However, in the current under-screen camera design, the pixel circuit of the first display area AA1 is set in the border area BB above the first display area AA1 or in the second display area AA2 adjacent to the first display area AA1. Taking the pixel circuit set in the border area BB above the first display area AA1 as an example, the pixel circuit is connected to the light-emitting device in the first display area AA1 through the ITO trace 100, so as to transmit the surrounding pixel signals to the under-screen camera area. As shown Figure 2 As shown, Figure 2 This is a schematic diagram of the ITO wiring on the same layer. The ITO wiring is formed by photoresist exposure, development and etching process. Due to the minimum exposure distance and minimum exposure line width requirements of photoresist, the same layer of ITO has a minimum line width (Width) and line spacing (space). At present, the general limits in the factory are Width (about 2um and above) and space (about 2um and above). Therefore, the number of wiring on the same layer of ITO is limited. When there are many light-emitting devices in the first display area AA1 (camera area under the screen), multi-layer ITO wiring is required, such as Figure 3 As shown, Figure 3Taking the use of 4-layer ITO wiring to connect the pixel circuit and the light-emitting device as an example, the 4-layer ITO wiring is indicated as 10, 20, 30, and 40 respectively. Each layer of ITO needs to be covered with an organic layer (flat layer), that is, four flat layers (50, 60, 70, and 80) are required. The four flat layers (50, 60, 70, and 80) need to be composed separately to form vias corresponding to the anode 90 of the light-emitting device. In this way, the number of masks for composition is large, resulting in a long process time and high cost, and it is very difficult to apply it to actual mass production.

[0083] In order to solve the problem in the prior art that the number of wirings in the same layer of ITO is limited, and multi-layer ITO wiring is required, resulting in a large number of masks and high costs, the present disclosure provides a display substrate, such as Figure 4 and Figure 5 As shown, including:

[0084] Substrate 1, with a routing area, Figure 1 Only the routing area is indicated;

[0085] A first routing layer 2 is located on the substrate 1, and the first routing layer 2 includes a plurality of first routing lines 21 arranged at intervals in a routing area, and a distance S between adjacent first routing lines 21 is less than 2 um;

[0086] The insulating layer 3 is located on a side of the first wiring layer 2 away from the substrate 1, and the insulating layer 3 has a plurality of first via holes 31 corresponding to the first wirings 21;

[0087] The first flat layer 4 is located on the side of the insulating layer 3 facing away from the substrate 1 . The first flat layer 4 has second via holes 41 corresponding to the first via holes 31 . The second via holes 41 at least partially overlap with the first via holes 31 .

[0088] The above-mentioned display substrate provided by the embodiment of the present disclosure, by setting an insulating layer 3 between the first routing layer 2 and the first flat layer 4, can change the method of using the photoresist process in the prior art to produce routing, and produce a distance between adjacent first routing lines 21 less than 2um, so that more lines can be laid in the same wiring space, so that for the same number of routing lines, the present disclosure can reduce the number of routing layers, and the flat layer above the routing layer can be reduced, thereby reducing the number of composition masks and reducing the production cost.

[0089] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 4As shown, the insulating layer 3 includes a plurality of independent sub-insulating layers 32 corresponding to each first wiring 21, and the sub-insulating layer 32 has a first via 31; thus, when making the first wiring 21, the embodiment of the present disclosure can deposit a layer of insulating layer 3 after depositing the material for making the first wiring 21 on the substrate 1. Compared with the photoresist material in the prior art, the material of the insulating layer 3 has a higher exposure resolution and can produce a smaller line width / line spacing ratio, which can be SiNx or SiOx. At present, due to the minimum line width and minimum line spacing requirements for making wiring using the photoresist process, the wiring on the same layer has a minimum line width and line spacing. The current in-factory production limits are: minimum line width (about 2um and above) and minimum line spacing (about 2um and above), so the number of wiring on the same layer is limited. The present disclosure uses an insulating layer 3 to replace the photoresist in the prior art, and uses the insulating layer 3 as a mask to etch the first wiring layer 2, so that the first wiring layer 2 can produce multiple first wirings 21 with a smaller line width / line spacing ratio, that is, the distance S between adjacent first wirings 21 is less than 2um, and the line width W of the first wiring 21 is less than or equal to 2um. In this way, more wirings can be arranged on the same wiring layer, thereby reducing the number of masks, reducing costs, and shortening investment time.

[0090] It should be noted that Figure 4 The distance S between adjacent first wiring lines 21 and the line width W of the first wiring lines 21 are only schematic illustrations and do not represent actual dimensions.

[0091] Furthermore, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 4 As shown, using the insulating layer 3 as a mask, the distance S between adjacent first traces 21 can be 0.8um-1.8um, further can be 1um, 1.2um, 1.5um, 1.7um. The line width W of the first trace 21 can be 1.0um-1.8um, further can be 1.2um, 1.5um, 1.7um.

[0092] Furthermore, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 6 As shown, Figure 6 for Figure 4 Schematic diagram of the first wiring layer 2 and the insulating layer 3, the distance S between adjacent first wirings 21 is set to be equal to the line width of the first wiring 21, preferably 1.2um-1.6um; Figure 6For example, the distance S between adjacent first routing lines 21 and the line width of the first routing lines 21 are both 1.5um. For example, in the wiring space of 200um, the photoresist process in the prior art can only arrange 50 routing lines in one layer, while the solution of the embodiment of the present disclosure can reduce the line width / line spacing to 1.5um / 1.5um, so that 67 routing lines can be arranged in the wiring space of 200um, thereby reducing the number of routing layers, saving the number of masks of the flat layer, and reducing costs.

[0093] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 1 and Figure 7 As shown, it includes a display area AA and a frame area BB, the display area AA includes a first display area AA1 and a second display area AA2, and the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2;

[0094] The first display area AA1 includes a plurality of sub-pixels (not shown) distributed in an array, and the sub-pixels include light-emitting devices and pixel circuits (not shown). Figure 1 As shown, the pixel circuit may be located in the border area BB adjacent to the first display area AA1, or, as shown in FIG. Figure 7 As shown, the second display area AA2 has a transition area CC adjacent to the first display area AA1, and the pixel circuit is located in the transition area CC;

[0095] like Figure 1 and Figure 7 As shown, Figure 4 The wiring area shown is at least partially located in the first display area AA1; Figure 8 As shown, the first wiring layer 2 is located between the anode 5 of the light-emitting device and the pixel circuit 6; the pixel circuit 6 may be, but is not limited to, a 7T1C structure including 7 transistors and a capacitor, the pixel circuit 6 includes a source-drain electrode layer, and the first wiring layer 2 is electrically connected to the source-drain electrode layer of the pixel circuit;

[0096] like Figure 8 As shown, the first trace 21 passes through the corresponding first via 31 and second via 41 (refer to Figure 4 ) is electrically connected to the anode 5 of the light-emitting device.

[0097] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 8 As shown, it also includes a second flat layer 7 located between the pixel circuit 6 and the first wiring layer 2, and the second flat layer 7 has a plurality of fourth via holes 71 corresponding to the first wiring 21;

[0098] The first wiring 21 is electrically connected to the pixel circuit 6 through the corresponding fourth via 71 .

[0099] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 4 and Figure 8 As shown, the material of the first wiring 21 may include but is not limited to at least one of ITO, a-Si, IZO, and IGZO.

[0100] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, Figure 4 and Figure 8 The wiring area shown is not only applicable to the under-screen camera area, but also to the fan-shaped area (the fan-shaped area is used to connect the signal lines of the display area AA, such as the data line, to the external driver chip to realize signal transmission). Fig. 9 As shown, the display substrate includes a display area AA and a frame area BB, the display area AA includes a plurality of signal lines (such as data lines S1, S2, S3...), and the frame area BB includes Figure 4 The routing area shown (the routing area is the fan-shaped area DD);

[0101] The first wiring 21 is used to electrically connect corresponding signal lines (eg, data lines S1, S2, S3, . . . ).

[0102] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Fig. 9 As shown, it includes a gate metal layer and a source-drain metal layer formed on a substrate in sequence, and the first wiring layer 2 can be located in the gate metal layer or the source-drain metal layer. In this way, it is only necessary to change the original patterning pattern when forming the gate metal layer or the source-drain metal layer, and the pattern of the first wiring layer 2 and the gate metal layer or the source-drain metal layer can be formed through a single patterning process, without adding a process for preparing the first wiring layer 2 separately, which can simplify the preparation process flow, save production costs, and improve production efficiency.

[0103] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 As shown, it also includes a second wiring layer 8 located between the insulating layer 3 and the first flat layer 4, and the second wiring layer 8 includes a plurality of second wirings 81 arranged at intervals in the wiring area;

[0104] The insulating layer 3 is provided to form a groove 32 between adjacent first wirings 21, and the second wiring 81 is at least located in the groove 32. In this way, when manufacturing the insulating layer 3, a thinner insulating layer 3 can be manufactured so that the upper surface of the second wiring 81 is substantially flush with the upper surface of the first wiring 21. Since the first wiring layer 2 and the second wiring layer 8 are insulated by the insulating layer 3, this is equivalent to wiring the first wiring layer 2 and the second wiring layer 8 on the same layer, so that more wirings can be arranged in the same wiring space, the number of wiring layers can be reduced, and the number of masks in the subsequent manufacturing process can be reduced, thereby reducing the cost.

[0105] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 As shown, the orthographic projection width of the second wiring 81 on the substrate 1 is smaller than the orthographic projection width of the insulating layer 3 between adjacent first vias 31 on the substrate 1. In this way, the second wiring 81 will not cover the position of the first via 31, and the second wiring 81 does not need to be etched again to expose the area corresponding to the first via 31.

[0106] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Fig.10 As shown, the orthographic projection of the second wiring 81 on the substrate 1 and the orthographic projection of the gap between adjacent first wirings 21 on the substrate 1 are substantially overlapped. Fig.11 As shown, Fig.11 for Fig.10 In the top view of the second routing line 81 and the first routing line 21 on the substrate 1, the second routing line 81 and the first routing line 21 can be wired with zero spacing. Since the insulating layer 3 can be set very thin, in the thickness direction, the upper surfaces of the first routing line 21 and the second routing line 81 can be set to be basically flat. Fig.10 This is only a schematic illustration. In actual manufacturing, the thickness of the insulating layer 3 is very thin. For example, taking a 200um space as an example, the same wiring layer made by the photoresist process in the prior art can only arrange 50 wirings, while Fig.10 In the structure shown, the second routing line 81 and the first routing line 21 are equivalent to the same-layer routing. In this way, the wiring space is not limited by the line width and line spacing. The two layers of routing lines can be wired with zero spacing, and 100 routing lines can be arranged in a space of 200um, which can reduce the number of routing layers by half, thereby saving half the number of flat layer masks.

[0107] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 and Fig.10 As shown, the width of the first wiring 21 is greater than or equal to 1.5um, and the width of the first wiring 21 is less than 2um; since the first via hole 31 is obtained by etching, due to factors such as the etching rate, the cross-sectional shape of the first via hole 31 is generally a trapezoid. In order to ensure that the insulating layer 3 covers the surroundings of the first wiring 21, the maximum width of the first via hole 31 is greater than or equal to 1.1um, and the maximum width of the first via hole 31 is less than 1.6um;

[0108] The orthographic projection of the first routing line 21 on the substrate 1 has a first annular side 211, and the orthographic projection of the first via hole 31 on the substrate 1 has a second annular side 311. The distance d between the first annular side 211 and the second annular side 311 is greater than or equal to 0.2 um, thereby ensuring that the first routing line 21 and the second routing line 81 are insulated by the insulating layer 3.

[0109] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 and Fig.10 As shown, the first planar layer 4 has third via holes 42 corresponding to the second wirings 81 , so that the second wirings 81 are electrically connected to the subsequently manufactured anodes through the third via holes 42 .

[0110] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 and Fig.10 As shown, since the insulating layer 3 can be made thinner, when making the second wiring 81, the sum of the thickness of the second wiring 81 and the thickness of the insulating layer 3 can be made substantially the same as the thickness of the first wiring 21. That is, the upper surface of the second wiring 81 is substantially flush with the upper surface of the first wiring 21, which is equivalent to wiring the first wiring layer 2 and the second wiring layer 8 on the same layer, so that more wirings can be arranged in the same wiring space, the number of wiring layers can be reduced, and the number of masks in the subsequent manufacturing process can be reduced, thereby reducing costs.

[0111] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 1 and Figure 7 As shown, it includes a display area AA and a frame area BB, the display area AA includes a first display area AA1 and a second display area AA2, and the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2;

[0112] The first display area AA1 includes a plurality of sub-pixels (not shown) distributed in an array, and the sub-pixels include light-emitting devices and pixel circuits (not shown). Figure 1 As shown, the pixel circuit may be located in the border area BB adjacent to the first display area AA1, or, as shown in FIG. Figure 7 As shown, the second display area AA2 has a transition area CC adjacent to the first display area AA1, and the pixel circuit is located in the transition area CC;

[0113] like Figure 1 and Figure 7 As shown, Figure 5 and Fig.10 The wiring area shown is at least partially located in the first display area AA1; Fig.12 As shown, the first wiring layer 2 and the second wiring layer 8 are located between the anode 5 of the light-emitting device and the pixel circuit 6; the pixel circuit 6 may be, but is not limited to, a 7T1C structure including 7 transistors and a capacitor, the pixel circuit 6 includes a source-drain electrode layer, and the first wiring layer 2 and the second wiring layer 8 are electrically connected to the source-drain electrode layers corresponding to the pixel circuit respectively;

[0114] like Fig.12 As shown, the first trace 21 passes through the corresponding first via 31 and second via 41 (refer to Figure 5) is electrically connected to the anode 5 of the light-emitting device, and the second wiring 81 is electrically connected to the anode 5 of the light-emitting device through the third via 42.

[0115] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Fig.12 As shown, it also includes a second flat layer 7 located between the pixel circuit 6 and the first wiring layer 2, the second flat layer 7 has a plurality of fourth vias 71 corresponding to the first wiring 21 and the second wiring 81; the insulating layer 3 has a fifth via 33 corresponding to each second wiring 81;

[0116] The first wiring 21 is electrically connected to the pixel circuit 6 through the corresponding fourth via hole 71 , and the second wiring 81 is electrically connected to the pixel circuit 6 through the corresponding fourth via hole 71 and the fifth via hole 33 .

[0117] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 and Fig.12 As shown, the materials of the first wiring 21 and the second wiring 81 may include but are not limited to at least one of ITO, a-Si, IZO, and IGZO.

[0118] In a specific implementation, the materials used for the first wiring 21 and the second wiring 81 can be the same material or different materials. When the first wiring 21 and the second wiring 81 use the same material, they are preferably ITO (indium tin oxide).

[0119] In the specific implementation, since the second routing line 81 is not blocked when etching the insulating layer 3 to form the first via 31 corresponding to the first routing line 21, the etching material will etch the surface of the second routing line 81 to a certain extent, so the surface morphology of the second routing line 81 is rougher than the surface morphology of the first routing line 21.

[0120] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, Figure 5 and Fig.12 The wiring area shown is not only applicable to the under-screen camera area, but also to the fan-shaped area (the fan-shaped area is used to connect the signal lines of the display area AA, such as the data line, to the external driver chip to realize signal transmission). Fig. 9 As shown, the display substrate includes a display area AA and a frame area BB, the display area AA includes a plurality of signal lines (such as data lines S1, S2, S3...), and the frame area BB includes Figure 5 The routing area shown (the routing area is the fan-shaped area DD);

[0121] The first wiring 21 is used to electrically connect corresponding signal lines (eg, data lines S1, S2, S3, . . . ), and the second wiring 81 is used to electrically connect corresponding signal lines (eg, data lines S1, S2, S3, . . . ).

[0122] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Fig. 9 As shown, it includes a gate metal layer and a source-drain metal layer formed on a substrate in sequence, and the first wiring layer 2 is located in the gate metal layer or the source-drain metal layer. In this way, it is only necessary to change the original composition pattern when forming the gate metal layer or the source-drain metal layer, and the pattern of the first wiring layer 2 and the gate metal layer or the source-drain metal layer can be formed through a single composition process, without adding a process for preparing the first wiring layer 2 separately, which can simplify the preparation process flow, save production costs, and improve production efficiency. For example, if the first wiring layer 2 is located in the gate metal layer, the second wiring layer 8 can be located in the source-drain metal layer; if the first wiring layer 2 is located in the source-drain metal layer, the second wiring layer 8 can be located between the source-drain metal layer and the anode.

[0123] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 4 , Figure 8 , Figure 5 and Fig.12 As shown, the thickness of the insulating layer 3 may be 100 angstroms to 1200 angstroms.

[0124] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 4 , Figure 8 , Figure 5 and Fig.12 As shown, the thickness of the insulating layer 3 is preferably 500 angstroms to 1000 angstroms.

[0125] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 4 , Figure 8 , Figure 5 and Fig.12 As shown, the thickness of the insulating layer 3 is more preferably 700 angstroms to 800 angstroms.

[0126] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 4 , Figure 8 , Figure 5 and Fig.12 As shown, the material of the insulating layer 3 may include but is not limited to SiNx, SiOx or a combination thereof.

[0127] Based on the same inventive concept, the embodiment of the present disclosure also provides a method for manufacturing any of the above display substrates, such as Fig.13 As shown, including:

[0128] S1301, providing a substrate; the substrate having a wiring area;

[0129] S1302, forming a first routing layer and an insulating layer on the substrate; the first routing layer includes a plurality of independently arranged first routing lines in the routing area, the insulating layer is located on a side of the first routing layer away from the substrate, and the insulating layer has a plurality of first vias corresponding to each first routing line;

[0130] S1303, forming a first flat layer on a side of the insulating layer away from the substrate; the first flat layer has second via holes corresponding to the first via holes, and the second via holes at least partially overlap with the first via holes.

[0131] Below Figure 4 The manufacturing method of the display substrate shown in the figure is described in detail, which may specifically include the following steps:

[0132] (1) Depositing a first conductive layer 2' on the wiring area of ​​the substrate 1, such as Fig.14A As shown; when Figure 4 When the wiring area shown is located in the camera area under the screen, the material of the first conductive layer 2' is a transparent conductive material, such as ITO; Figure 4 When the wiring area shown is located in the fan-shaped area of ​​the frame area, the material of the first conductive layer 2 ′ is a metal material, such as Ag, Al, etc.

[0133] (2) Fig. 14B As shown, an insulating layer 3 is deposited on the side of the first conductive layer 2' away from the substrate 1, and the material of the insulating layer 3 includes but is not limited to SiNx, SiOx, or a combination thereof; Fig. 14C As shown, the insulating layer 3 is patterned to form a patterned insulating layer 3 (including a plurality of independently arranged sub-insulating layers 32).

[0134] (3) Fig. 14C The patterned insulating layer 3 shown is used as a mask to etch the first conductive layer 2' to form a plurality of independently arranged first wirings 21, such as Fig.14DAs shown, a plurality of first routing lines 21 constitute the first routing layer 2. Compared with the prior art in which the conductive layer is etched using a photoresist material as a mask, the exposure resolution of the insulating layer 3 is higher, and a smaller line width / line spacing ratio can be produced. At present, due to the minimum line width and minimum line spacing requirements for routing using the photoresist process, the routing lines on the same layer have a minimum line width and line spacing. The current in-factory production limits are: minimum line width (2um) and minimum line spacing (2um), so the number of wiring lines on the same layer is limited. The present disclosure uses an insulating layer 3 to replace the photoresist in the prior art, and uses the insulating layer 3 as a mask to etch the first routing layer 2, so that the first routing layer 2 can produce a plurality of first routing lines 21 with a smaller line width / line spacing ratio, that is, the distance S between adjacent first routing lines 21 is less than 2um, and the line width W of the first routing line 21 is less than 2um. In this way, more routing lines can be arranged on the same routing layer, thereby reducing the number of masks, reducing costs, and shortening investment time. In the embodiment of the present disclosure, the line width of the first wiring 21 is preferably 1.5 um, and the spacing between adjacent first wirings 21 is 2 um.

[0135] (4) depositing a first planar layer 4 on the side of the patterned insulating layer 3 facing away from the substrate 1, such as Fig.14E The first flat layer 4 is patterned to form a second via 41 corresponding to each first trace 21, as shown in FIG. Fig.14F shown.

[0136] (5) Using the first flat layer 4 having the second via hole 41 as a mask, the patterned insulating layer 3 is etched to form a first via hole 31 corresponding to the second via hole 41 on the insulating layer 3, as shown in FIG. Figure 14G shown.

[0137] (6) When Figure 5 When the wiring area shown is located in the under-screen camera area, a plurality of anodes 5 are formed on the side of the first flat layer 4 with the second via hole 41 facing away from the substrate 1, and each anode 5 is electrically connected to the first wiring 21 through the corresponding second via hole 41 and the first via hole 31, as shown in FIG. Fig.14H shown.

[0138] Below Figure 5 The manufacturing method of the display substrate shown in the figure is described in detail, which may specifically include the following steps:

[0139] (1) Depositing a first conductive layer 2' on the wiring area of ​​the substrate 1, such as Fig.15A As shown; when Figure 5 When the wiring area shown is located in the camera area under the screen, the material of the first conductive layer 2' is a transparent conductive material, such as ITO; Figure 5 When the wiring area shown is located in the fan-shaped area of ​​the frame area, the material of the first conductive layer 2 ′ is a metal material, such as Ag, Al, etc.

[0140] (2) The first conductive layer 2' is patterned to form a plurality of independently arranged first wirings 21, such as Fig. 15B As shown, a plurality of first wiring lines 21 constitute a first wiring layer 2 .

[0141] (3) An insulating layer 3 is deposited on the side of the first conductive layer 2' on which a plurality of first wirings 21 are formed, facing away from the substrate 1; the insulating layer 3 is arranged between adjacent first wirings 21 to form a groove 32, such as Fig. 15C shown.

[0142] (4) Depositing a second conductive layer 8' on the side of the insulating layer 3 facing away from the substrate 1, such as Fig.15D The second conductive layer 8' is patterned to form a plurality of second wirings 81 at least located in the corresponding grooves 32, as shown in FIG. Fig.15E As shown. The thickness of the second conductive layer 8' before patterning is greater than the thickness of the first conductive layer 2' before patterning. In this way, the second routing 81 and the first routing 21 are equivalent to the same layer wiring, and the wiring space is not limited by the line width and line spacing. The two layers of routing can be wired with zero spacing, so 100 routing lines can be arranged in a space of 200um, which can reduce the number of routing layers by half, thereby saving half the number of flat layer masks.

[0143] (5) A first planar layer 4 is deposited on the side of the second conductive layer 8' on which a plurality of second traces 81 are formed, away from the substrate 1. Fig.15F The first planar layer 4 is patterned to form second via holes 41 corresponding to the first wirings 21 and third via holes 42 corresponding to the second wirings 81, as shown in FIG. Figure 15G shown.

[0144] (6) Using the first flat layer 4 having the second via hole 41 and the third via hole 42 as a mask, the insulating layer 3 is etched to form a first via hole 31 corresponding to the second via hole 41, as shown in FIG. Fig.15H shown.

[0145] (7) When Figure 5 When the wiring area shown is located in the under-screen camera area, a plurality of anodes 5 are formed on the side of the first flat layer 4 with the second via hole 41 and the third via hole 42 facing away from the substrate 1, and some of the anodes 5 are electrically connected to the first wiring 21 through the corresponding second via hole 41 and the first via hole 31, and some of the anodes 5 are electrically connected to the second wiring 81 through the corresponding third via hole 42, as shown in FIG. Fig.15I shown.

[0146] In the specific implementation, due to Fig.15H When the insulating layer 3 is etched using the first flat layer 4 as a mask, part of the second wiring 81 will be etched. In order to make the surfaces of the first wiring 21 and the second wiring 81 substantially flush, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, Fig.15Aand Fig.15D As shown, the thickness of the second conductive layer 8' before patterning is approximately 200 angstroms greater than the thickness of the first conductive layer 2' before patterning. For example, the thickness of the first wiring 21 can be 600 angstroms, and the thickness of the second wiring 81 can be 800 angstroms. In this way, the thickness of the second wiring 81 remaining after dry etching can be close to that of the first wiring 21, so that the sum of the thickness of the second wiring 81 and the thickness of the insulating layer 3 is approximately the same as the thickness of the first wiring 21.

[0147] It should be noted that in the present disclosure, the shape of the first display area AA1 can be Figure 1 and Figure 7 The circle shown in the figure may also be a rectangle, an ellipse, a polygon or other shapes, which can be designed according to actual needs and are not limited here. The second display area AA2 may be as shown in FIG. Figure 1 and Figure 7 It surrounds the periphery of the first display area AA1; it may also surround part of the first display area AA1, for example, surround the left side, bottom side and right side of the first display area AA1, and the upper side boundary of the first display area AA1 coincides with the upper side boundary of the second display area AA2.

[0148] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 1 and Figure 7 As shown, the first display area AA1 is configured to install a photosensitive device, such as a camera module. Since there are only light-emitting devices in the first display area AA1 in the present disclosure, a larger light-transmitting area can be provided, which helps to adapt to a larger camera module.

[0149] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display substrate.

[0150] In a specific implementation, the display device further includes a photosensitive device (eg, a camera module), and the photosensitive device is disposed in the first display area of ​​the display substrate. Optionally, the photosensitive device may be a camera module.

[0151] The display device can be: a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as limitations on the present invention. In addition, since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the display device can refer to the embodiment of the above-mentioned display substrate, and the repeated parts will not be described in detail.

[0152] The embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device. An insulating layer is set between a first wiring layer and a first flat layer. This can change the method of manufacturing wiring using a photoresist process in the prior art, so that more wires can be laid in the same wiring space. Therefore, for the same number of wirings, the present disclosure can reduce the number of wiring layers, and the flat layer above the wiring layer can be reduced, thereby reducing the number of composition masks and reducing the manufacturing cost.

[0153] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0154] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display substrate, wherein: include: A substrate having a routing area; A first routing layer, located on the substrate, wherein the first routing layer comprises a plurality of first routing lines arranged at intervals in the routing area, wherein the line width of the first routing lines is less than or equal to 2 um, and the distance between adjacent first routing lines is less than 2 um; an insulating layer, located on a side of the first wiring layer away from the substrate, the insulating layer comprising a plurality of independent sub-insulating layers corresponding to each of the first wirings, each of the sub-insulating layers having a first via hole corresponding to the first wiring; The first flat layer is located on a side of the insulating layer away from the substrate, and the first flat layer has second via holes corresponding to the first via holes, and the second via holes at least partially overlap with the first via holes.

2. The display substrate according to claim 1, wherein: The distance between adjacent first routing lines is 0.8um-1.8um, and the line width of the first routing lines is 1.0um-1.8um.

3. The display substrate according to claim 2, wherein: The distance between adjacent first routing lines is 1.2-1.6 um, and the line width of the first routing lines is 1.2 um-1.6 um.

4. The display substrate according to any one of claims 1 to 3, wherein: It includes a display area and a frame area, the display area includes a first display area and a second display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; The first display area includes a plurality of sub-pixels distributed in an array, the sub-pixels include a light-emitting device and a pixel circuit, the pixel circuit is located in the border area adjacent to the first display area, or the second display area has a transition area adjacent to the first display area, the pixel circuit is located in the transition area; The wiring area is at least partially located in the first display area, and the first wiring layer is located between the anode of the light-emitting device and the pixel circuit; The first wiring is electrically connected to the anode of the light emitting device through the corresponding first via hole and the second via hole.

5. The display substrate according to claim 4, wherein: Also included is a second flat layer located between the pixel circuit and the first wiring layer, the second flat layer having a plurality of fourth via holes corresponding to the first wiring; The first wiring is electrically connected to the pixel circuit through the corresponding fourth via hole.

6. The display substrate according to claim 4, wherein: The material of the first wiring includes at least one of ITO, a-Si, IZO, and IGZO.

7. The display substrate according to any one of claims 1 to 3, wherein: It includes a display area and a frame area, wherein the display area includes a plurality of signal lines, and the frame area includes the routing area; The first wiring is used to electrically connect the corresponding signal line.

8. The display substrate according to claim 7, wherein: It comprises a gate metal layer and a source-drain metal layer which are sequentially formed on the substrate, and the first wiring layer is located on the gate metal layer or the source-drain metal layer.

9. The display substrate according to claim 1, wherein: It also includes a second routing layer located between the insulating layer and the first flat layer, wherein the second routing layer includes a plurality of second routing lines spaced apart in the routing area; The insulating layer is arranged to form a groove between adjacent first wirings, and the second wiring is at least located in the groove.

10. The display substrate according to claim 9, wherein: The orthographic projection width of the second trace on the substrate is smaller than the orthographic projection width of the insulating layer between adjacent first via holes on the substrate.

11. The display substrate according to claim 10, wherein: An orthographic projection of the second routing line on the substrate substantially overlaps with an orthographic projection of a gap between adjacent first routing lines on the substrate.

12. The display substrate according to claim 10, wherein: The width of the first routing line is greater than or equal to 1.5um, and the width of the first routing line is less than 2um; the maximum width of the first via hole is greater than or equal to 1.1um, and the maximum width of the first via hole is less than 1.6um; The orthographic projection of the first trace on the substrate has a first annular side, the orthographic projection of the first via on the substrate has a second annular side, and the distance between the first annular side and the second annular side is greater than or equal to 0.2 um.

13. The display substrate according to claim 9, wherein: The sum of the thickness of the second wiring and the thickness of the insulating layer is substantially the same as the thickness of the first wiring.

14. The display substrate according to any one of claims 9 to 13, wherein: It includes a display area and a frame area, the display area includes a first display area and a second display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; The first display area includes a plurality of sub-pixels distributed in an array, the sub-pixels include a light-emitting device and a pixel circuit, the pixel circuit is located in the border area adjacent to the first display area, or the second display area has a transition area adjacent to the first display area, the pixel circuit is located in the transition area; The wiring area is at least partially located in the first display area, and the first wiring layer and the second wiring layer are located between the light emitting device and the pixel circuit; The first planar layer has third via holes corresponding to the second wirings; The first wiring is electrically connected to the anode of the light-emitting device through the corresponding first via hole and the second via hole, and the second wiring is electrically connected to the anode of the light-emitting device through the third via hole.

15. The display substrate according to claim 14, wherein: It also includes a second flat layer located between the pixel circuit and the first wiring layer, the second flat layer having a plurality of fourth via holes corresponding to the first wiring and the second wiring; the insulating layer having a fifth via hole corresponding to each of the second wirings; The first wiring is electrically connected to the pixel circuit through the corresponding fourth via hole, and the second wiring is electrically connected to the pixel circuit through the corresponding fourth via hole and the fifth via hole.

16. The display substrate according to claim 14, wherein: The material of the first wiring and the material of the second wiring both include at least one of ITO, a-Si, IZO, and IGZO.

17. The display substrate according to any one of claims 9 to 13, wherein: It includes a display area and a frame area, wherein the display area includes a plurality of signal lines, and the frame area includes the routing area; The first wiring is used to electrically connect the corresponding signal line, and the second wiring is used to electrically connect the corresponding signal line.

18. The display substrate according to claim 17, wherein: It comprises a gate metal layer and a source-drain metal layer which are sequentially formed on the substrate, and the first wiring layer is located on the gate metal layer or the source-drain metal layer.

19. The display substrate according to claim 1, wherein: The thickness of the insulating layer is 100 angstroms to 1200 angstroms.

20. The display substrate according to claim 19, wherein: The thickness of the insulating layer is 500 angstroms to 1000 angstroms.

21. The display substrate according to claim 20, wherein: The thickness of the insulating layer is 700 angstroms to 800 angstroms.

22. The display substrate according to claim 1, wherein: The material of the insulating layer includes SiNx, SiOx or a combination thereof.

23. A method for manufacturing a display substrate according to any one of claims 1 to 22, wherein: include: providing a substrate; The substrate has a wiring area; forming a first wiring layer and an insulating layer on the substrate; The first routing layer includes a plurality of independently arranged first routing lines in the routing area, the insulating layer is located on a side of the first routing layer away from the substrate, and the insulating layer has a plurality of first vias corresponding to each of the first routing lines; forming a first flat layer on a side of the insulating layer facing away from the substrate; The first planar layer has second via holes corresponding to the first via holes, and the second via holes at least partially overlap with the first via holes.

24. The method of claim 23, wherein: Forming a first wiring layer and an insulating layer on the substrate specifically includes: Depositing a first conductive layer in a routing region of the substrate; Depositing an insulating layer on a side of the first conductive layer away from the substrate, and patterning the insulating layer to form a patterned insulating layer; Using the patterned insulating layer as a mask, etching the first conductive layer to form a plurality of independently arranged first wirings; Depositing a first flat layer on a side of the patterned insulating layer away from the substrate, and patterning the first flat layer to form second via holes corresponding to the first wirings; The patterned insulating layer is etched using the first planar layer having the second via hole as a mask to form a first via hole corresponding to the second via hole.

25. The method of claim 23, wherein: Forming a first wiring layer and an insulating layer on the substrate specifically includes: Depositing a first conductive layer in a routing region of the substrate; Patterning the first conductive layer to form a plurality of independently arranged first wirings; Depositing an insulating layer on a side of the first conductive layer on which the plurality of first wirings are formed, away from the substrate; the insulating layer is arranged to form a groove between adjacent first wirings; Depositing a second conductive layer on a side of the insulating layer away from the substrate, and patterning the second conductive layer to form a plurality of second wirings at least located in the corresponding grooves; wherein the thickness of the second conductive layer before patterning is greater than the thickness of the first conductive layer before patterning; Depositing a first flat layer on a side of the second conductive layer on which the plurality of second wirings are formed, which is away from the substrate, and patterning the first flat layer to form second via holes corresponding to the first wirings and third via holes corresponding to the second wirings; The insulating layer is etched using the first planar layer having the second via hole and the third via hole as a mask to form a first via hole corresponding to the second via hole.

26. The method of claim 25, wherein: The thickness of the second conductive layer before patterning is approximately 200 angstroms greater than the thickness of the first conductive layer before patterning, and the sum of the thickness of the second wiring and the thickness of the insulating layer is approximately the same as the thickness of the first wiring.

27. The method according to claim 24 or 25, wherein: Also includes: A plurality of anodes are formed on a side of the first flat layer where the second via hole is formed, which is away from the substrate. Each of the anodes is electrically connected to the first wiring through the corresponding second via hole and the first via hole.

28. A display device, wherein: Comprising the display substrate as described in any one of claims 1-22.

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