Marking method, verification method, device, storage medium and electronic equipment

Abstract

This disclosure provides a marking method, verification method, apparatus, storage medium, and electronic device, relating to the field of electronic circuit technology. The marking method includes: acquiring simulation data for a circuit under test; wherein the simulation data includes at least the actual voltage range of each node to be marked in the circuit under test; determining a preset voltage range for each node to be marked based on preset voltage changes of marked nodes and at least some of the nodes to be marked; wherein the preset voltage changes are related to the circuit structure between the node to be marked and the marked nodes; traversing the simulation data, and marking the nodes whose actual voltage range falls within the preset voltage range as the node type corresponding to the preset voltage range. This solves the current technical problem of low marking efficiency and achieves the technical effect of improving marking efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a marking method, a verification method, a device, a storage medium, and an electronic device. Background Technology

[0002] In related technologies, ERC (Electrical Rule Check) refers to testing the circuit schematic or hierarchical schematic after the initial design is completed, in order to avoid carrying over design errors into subsequent designs or pilot production. Before testing, it is generally necessary to mark some nodes in the circuit under test to facilitate subsequent testing according to nodes.

[0003] Currently, marking is generally done manually, which is inefficient. Summary of the Invention

[0004] This disclosure provides a marking method, a verification method, an apparatus, a storage medium, and an electronic device, thereby improving marking efficiency.

[0005] In a first aspect, one embodiment of this disclosure provides a marking method, including:

[0006] Obtain simulation data for the circuit under test; wherein the simulation data includes at least the actual voltage range of each node to be marked in the circuit under test;

[0007] The preset voltage range of each node to be marked is determined based on the preset voltage change of the marked nodes and at least some of the nodes to be marked in the circuit under test; wherein the preset voltage change is related to the circuit structure between the nodes to be marked and the marked nodes.

[0008] The simulation data is traversed, and nodes whose actual voltage range is within the preset voltage range are marked as nodes corresponding to the preset voltage range.

[0009] In an optional embodiment of this disclosure, there are multiple preset voltage ranges, and each preset voltage range corresponds to a different node type. The simulation data is then traversed, and nodes in the simulation data whose actual voltage range falls within a preset voltage range are marked as node types corresponding to the preset voltage range. This includes:

[0010] Based on each preset voltage range, the simulation data is traversed, and the nodes in the simulation data whose actual voltage range is within the current preset voltage range are marked as the current node type corresponding to the current preset voltage range.

[0011] In one optional embodiment of this disclosure, the traversal order of different types of nodes to be marked is determined based on the number of components between nodes to be marked and marked nodes of different types, and the components between nodes to be marked and their corresponding marked nodes of the same type are the same.

[0012] In an optional embodiment of this disclosure, before traversing the simulation data based on each preset voltage range, the method further includes:

[0013] Each node to be labeled is categorized; the category label is used to characterize whether the component corresponding to the node to be labeled is a standard part or a non-standard part; correspondingly,

[0014] The simulation data is iterated through for each preset voltage range, including:

[0015] Traverse the nodes in the simulation data that are categorized as standard parts;

[0016] The nodes to be labeled in the simulation data that are classified as non-standard parts are traversed.

[0017] In an optional embodiment of this disclosure, class labeling of each node to be labeled includes:

[0018] Determine the device type of the standard component corresponding to each node to be marked; among them, the preset voltage ranges are different for different device types.

[0019] In an optional embodiment of this disclosure, if the same node contains multiple operating states, simulation data for the circuit under test is acquired, including:

[0020] Simulations were performed on the circuit under test based on different driving parameters to obtain simulation data for each sub-simulation of the circuit under test under different operating states; correspondingly,

[0021] The simulation data is traversed, and nodes whose actual voltage range falls within a preset voltage range are marked as nodes corresponding to the preset voltage range, including:

[0022] The simulation data of each sub-simulation is traversed sequentially, and the nodes to be marked in the sub-simulation data whose actual voltage range is within the preset voltage range are marked as the node type corresponding to the preset voltage range.

[0023] In one optional embodiment of this disclosure, the driving parameters include at least: a control signal and a driving voltage.

[0024] In one optional embodiment of this disclosure, the marked node includes at least one of the power supply voltage terminal and the ground terminal of the circuit under test.

[0025] Secondly, one embodiment of this disclosure provides a verification method, including:

[0026] Obtain the node type of each node in the circuit under test; where node type refers to the node type determined according to any of the marking methods mentioned above.

[0027] According to the node type of each node, the circuit under test is verified sequentially based on the preset verification parameters of each node.

[0028] In one optional embodiment of this disclosure, the circuit under test is verified sequentially based on the preset verification parameters of each node according to the node type of each node, including:

[0029] Determine the number of nodes in each node type;

[0030] The circuit under test is verified sequentially based on the preset verification parameters of each node, in descending order of the number of nodes.

[0031] In an optional embodiment of this disclosure, before verifying the circuit under test sequentially based on the preset verification parameters of each node according to the node type of each node, the method further includes:

[0032] Each node in the circuit under test is categorized; the category label indicates whether the component corresponding to each node is a standard part or a non-standard part; correspondingly,

[0033] According to the node type of each node, the circuit under test is verified sequentially based on the preset verification parameters of each node, including:

[0034] For the same node type, nodes in the circuit under test that are categorized as standard parts are verified based on preset verification parameters.

[0035] Verify nodes in the circuit under test that are categorized as non-standard parts based on preset verification parameters.

[0036] Thirdly, one embodiment of this disclosure provides a marking apparatus, the apparatus comprising:

[0037] The first acquisition module is used to acquire simulation data for the circuit under test; wherein the simulation data includes at least the actual voltage range of each node to be marked in the circuit under test.

[0038] The determination module is used to determine the preset voltage range of each node to be marked based on the preset voltage change of the marked nodes and at least some of the nodes to be marked in the circuit under test; wherein the preset voltage change is related to the circuit structure between the nodes to be marked and the marked nodes.

[0039] The marking module is used to traverse the simulation data and mark the nodes in the simulation data whose actual voltage range is within the preset voltage range as the node type corresponding to the preset voltage range.

[0040] Fourthly, one embodiment of this disclosure provides a verification device, the device comprising:

[0041] The second acquisition module is used to acquire the node type of each node in the circuit under test; wherein, the node type refers to the node type determined according to any of the above marking methods;

[0042] The verification module is used to verify the circuit under test according to the node type of each node and based on the preset verification parameters of each node.

[0043] Fifthly, one embodiment of this disclosure provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method described above.

[0044] In a sixth aspect, one embodiment of this disclosure provides an electronic device, including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described method by executing the executable instructions.

[0045] The technical solution disclosed herein has the following beneficial effects:

[0046] The above marking method first acquires simulation data for the circuit under test, then determines the preset voltage range of each node to be marked based on the preset voltage changes of the marked nodes and at least some of the nodes to be marked in the circuit under test. Finally, it iterates through the simulation data and marks the nodes whose actual voltage range falls within the preset voltage range as the node type corresponding to the preset voltage range. Firstly, the entire process can be automated using terminal devices, requiring minimal human intervention, thus solving the technical problem of low efficiency caused by manual marking and improving marking efficiency. Secondly, automated marking avoids errors caused by differences in human skill or experience, further improving the accuracy and reliability of the marking.

[0047] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0049] Figure 1 This diagram illustrates the structure of the circuit under test in this exemplary embodiment.

[0050] Figure 2 This diagram illustrates a marking method according to an exemplary embodiment.

[0051] Figure 3 This diagram illustrates a marking method according to an exemplary embodiment.

[0052] Figure 4 This diagram illustrates the structure of the circuit under test in this exemplary embodiment.

[0053] Figure 5 This diagram illustrates a verification method according to an exemplary embodiment.

[0054] Figure 6 This diagram illustrates a verification method according to an exemplary embodiment.

[0055] Figure 7 This diagram illustrates a verification method according to an exemplary embodiment.

[0056] Figure 8 This diagram illustrates the structure of a marking device according to this exemplary embodiment.

[0057] Figure 9 This diagram illustrates the structure of a verification device in this exemplary embodiment.

[0058] Figure 10 A schematic diagram of the structure of an electronic device in this exemplary embodiment is shown. Detailed Implementation

[0059] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0060] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0061] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0062] In related technologies, ERC (Electrical Rule Check) refers to testing the completed circuit schematic or hierarchical schematic to prevent design errors from being carried over to subsequent designs or pilot production. Before testing, it is generally necessary to mark some nodes in the circuit under test to facilitate subsequent node-based testing. Currently, marking is usually done manually, which is inefficient.

[0063] In view of the above problems, this disclosure provides a marking method to improve marking efficiency. The following is a brief description of the application environment of the marking method provided in this disclosure:

[0064] Please see Figure 1 The marking method provided in this disclosure is applied to the circuit under test to mark the type of each node in the circuit under test. For example... Figure 1The circuit under test (DUT) consists of four MOSFETs (Metal-Oxide-Semiconductors). The power supply terminal, ground terminal, and the point between any two MOSFETs are each considered a node. The marking method provided in this embodiment marks all or some of the nodes in the DUT. The marking content is to label each node with its type, such as input voltage VHV, output high-level voltage VOH, and bias voltage VBN. This is merely an example; the specific marking type and content can be set according to actual conditions, and this embodiment does not impose any limitations. This marking method can be applied to any terminal device, such as a server, computer, laptop, production control equipment, or any electronic device with control functions.

[0065] The following example uses the aforementioned terminal device as the execution subject, illustrating how this marking method is applied to mark various nodes in the circuit under test on the terminal device. Please refer to [link / reference]. Figure 2 The marking method provided in this embodiment includes the following steps 201-203:

[0066] Step 201: Obtain simulation data for the circuit under test.

[0067] The simulation data must include at least the actual voltage range of each node to be marked in the circuit under test (DUT). Simulation data refers to the voltage values ​​or voltage ranges measured at each node after the DUT is run in the simulation environment, provided the necessary operating conditions are input to the simulation software, such as drive voltage and control signals. The nodes to be marked are pre-defined or selected based on the structure of the DUT. These nodes are relative to already marked nodes. For example, the voltages of power supply terminals and ground terminals are generally stable and do not require ERC testing. Therefore, these nodes can be marked in advance, eliminating the need for further marking during the actual marking process, thus saving marking and testing time.

[0068] Step 202: Determine the preset voltage range of each node to be marked based on the preset voltage changes of the marked nodes and at least some of the nodes to be marked in the circuit under test.

[0069] Each node to be marked corresponds to at least one preset voltage change. The preset voltage change for different nodes to be marked may be the same or different. This preset voltage change can be specifically set according to the specific circuit, and is not limited here. However, it should be noted that the preset voltage change in this embodiment is related to the circuit structure between the node to be marked and the marked node, such as the type and quantity of components between the two nodes, and is independent of the influence of environmental factors such as temperature and pressure. For example, for a node to be marked connected between the power supply terminal and the ground terminal of a marked node, the node to be marked may have two preset voltage ranges. One is determined based on the components between the node to be marked and the power supply terminal and the input voltage of the power supply terminal, and the other is determined based on the components between the node to be marked and the ground terminal and the input voltage of the ground terminal. Other nodes to be marked follow the same principle. Of course, this is only an example, and the determination of the preset voltage range includes, but is not limited to, the above calculation method.

[0070] Step 203: Traverse the simulation data and mark the nodes in the simulation data whose actual voltage range is within the preset voltage range as the node type corresponding to the preset voltage range.

[0071] The simulation data can be stored in the form of a data list, etc. Different nodes have corresponding actual voltage ranges, and different preset voltage ranges correspond to different node types. The terminal device determines the node type in the following ways, including but not limited to: First, traversing the simulation data according to preset voltage ranges. For example, traversing one or more preset voltage ranges each time, extracting the actual voltage ranges within the preset voltage range, determining the node to be marked where the extracted actual voltage ranges are located, and then determining the node to be marked as the node type corresponding to the preset voltage range; Second, traversing the simulation data according to nodes. For example, if the actual voltage range of the first node to be marked is within the second preset voltage range, then the first node to be marked is determined as the node type corresponding to the second preset voltage range.

[0072] It should be noted that "marking the node to be marked" in this disclosure refers to marking the coordinates corresponding to the node to be marked, which can be obtained through circuit design software.

[0073] The marking method provided in this disclosure first acquires simulation data for the circuit under test, then determines the preset voltage range of each node to be marked based on the preset voltage changes of the marked nodes and at least some of the nodes to be marked in the circuit under test, and finally iterates through the simulation data to mark the nodes whose actual voltage range falls within the preset voltage range as the node type corresponding to the preset voltage range. Firstly, the entire process can be automatically marked using terminal devices, requiring minimal human intervention, thus solving the technical problem of low efficiency caused by manual marking and achieving improved marking efficiency. Secondly, automatic marking avoids marking errors due to differences in human skill or experience, further improving the accuracy and reliability of the marking.

[0074] In one optional embodiment of this disclosure, the number of preset voltage ranges is multiple, and the node type corresponding to each preset voltage range is different. Therefore, step 203, which involves traversing the simulation data and marking the nodes whose actual voltage range falls within the preset voltage range as the node type corresponding to the preset voltage range, includes the following step A:

[0075] Step A: Based on each preset voltage range, traverse the simulation data and mark the nodes in the simulation data whose actual voltage range is within the current preset voltage range as the current node type corresponding to the current preset voltage range.

[0076] This embodiment of the present disclosure traverses the simulation data based on the first method in step 203 above. By comparing the actual voltage range in the simulation data with each preset voltage range in this way, the node type of each node can be determined without waiting for all data to be traversed before determining the node type, which is more efficient.

[0077] In one optional embodiment of this disclosure, the traversal order of different types of nodes to be marked is determined based on the number of components between nodes to be marked and marked nodes of different types, and the components between nodes to be marked and their corresponding marked nodes of the same type are the same.

[0078] Once the circuit under test is determined, the connection relationships between nodes are relatively fixed, and the components between each marked node and the node to be marked are also relatively fixed, although the number of components between adjacent nodes may vary. This embodiment of the disclosure traverses and marks the nodes to be marked based on a preset voltage change between marked and unmarked nodes. Therefore, this embodiment can first determine the number of components between each unmarked node and marked node, and then, during each traversal based on a preset voltage range, traverse in descending order of the number of components. For example, if the first unmarked node has 10 components between it and the marked node, and the second unmarked node has 5 components between it and the marked node, then during data traversal based on the preset voltage range, the first unmarked node is traversed first to determine its node type, and then the second unmarked node is traversed. This method can obtain more node types in a shorter time, resulting in higher efficiency. It is understood that in other embodiments, traversal can also be performed in ascending order of the number of components.

[0079] In an optional embodiment of this disclosure, before step A above, which involves traversing the simulation data based on each preset voltage range, the marking method further includes the following step B:

[0080] Step B: Label each node to be labeled with a category.

[0081] Category labels are used to characterize whether the components corresponding to the node to be labeled (or the components between the node to be labeled and the neighboring labeled nodes) are standard or non-standard. Standard components refer to components that conform to international standards, national standards or industry standards. Non-standard components are the opposite of standard components, such as components that have been redesigned or improved according to actual needs.

[0082] Correspondingly, please see Figure 3 Step A above involves iterating through the simulation data for each preset voltage range, including the following steps 301-302:

[0083] Step 301: Traverse the nodes to be labeled in the simulation data that are categorized as standard parts.

[0084] Step 302: Traverse the nodes to be labeled in the simulation data that are classified as non-standard parts.

[0085] Standard parts belonging to the same component type have the same marking type and verification parameters. In this embodiment of the present disclosure, when traversing simulation data for a preset voltage range, standard parts and non-standard parts are traversed separately. During the traversal process, standard parts and non-standard parts can be separated, so that the obtained node types are relatively concentrated, which can improve the efficiency of subsequent marking and further improve the efficiency of verification based on the marked node types.

[0086] In one optional embodiment of this disclosure, the nodes to be marked in the simulation data that are categorized as standard parts can be traversed first, and then the nodes to be marked in the simulation data that are categorized as non-standard parts can be traversed. When traversing standard parts, it is not necessary to frequently compare parameters, that is, it is not necessary to frequently change the preset voltage in the preset voltage range mentioned above during the comparison process. More comparison results can be obtained in a shorter time, thereby marking more nodes to be marked by node type, which is more efficient.

[0087] In an optional embodiment of this disclosure, step B, classifying each node to be labeled, includes the following steps:

[0088] Determine the device type of the standard component corresponding to each node to be marked.

[0089] Different device types correspond to different preset voltage ranges. Device type refers to the category of a component, including a single transistor, a single element, and a combined structure consisting of multiple elements and / or transistors. By marking the device type of standard components in the node to be marked, the actual voltage of standard components of the same type is generally the same as the preset voltage or falls within a narrow threshold range. Therefore, in this embodiment, the device type of the standard components corresponding to the node to be marked is first determined. In the subsequent marking process, standard components of the same device type can be marked uniformly, and then other non-standard components can be marked one by one in the same way, which is more efficient.

[0090] In one optional embodiment of this disclosure, if the same node contains multiple operating states, for example, please refer to [link to relevant documentation]. Figure 4 If the same output terminal 'out' has two output paths, Q1 and Q2, then the corresponding output terminal 'out' has two operating states, meaning that the node corresponds to two preset voltage ranges, or in other words, two node types. Correspondingly, step 201 above, obtaining simulation data for the circuit under test, includes the following steps:

[0091] Simulations were performed on the circuit under test using different driving parameters to obtain simulation data for each sub-simulation of the circuit under test under different operating states. It is understandable that when the circuit is in different operating states, the output path or connection relationship of at least one node changes.

[0092] For example Figure 4 In this embodiment, when the driving parameter is the first driving parameter, Q1 is on and Q2 is off, thereby obtaining the first sub-simulation data of each circuit node, including the output terminal 'out', under this operating state. When the driving parameter is the second driving parameter, Q1 is off and Q2 is on, thereby obtaining the second sub-simulation data of each circuit node, including the output terminal 'out', under another operating state. By fusing the sub-simulation data under different driving parameters in this embodiment, the simulation data of the circuit under test in the above embodiment can be obtained.

[0093] Correspondingly, step 203 above, which involves traversing the simulation data and marking the nodes in the simulation data whose actual voltage range falls within a preset voltage range as the node type corresponding to the preset voltage range, includes the following steps:

[0094] The simulation data of each sub-simulation is traversed sequentially, and the nodes to be marked in the sub-simulation data whose actual voltage range is within the preset voltage range are marked as the node type corresponding to the preset voltage range.

[0095] For example, first, the first sub-simulation data under the first driving parameter is traversed. During this traversal, this first sub-simulation data can be used as the simulation data in step 203 above. The node type determined by the terminal device in step 203 is used to traverse this first sub-simulation data. After traversal, the second sub-simulation data under the second driving parameter is used as the simulation data in step 203 above. The node type determined by the terminal device in step 203 is used to traverse this second sub-simulation data, and so on, traversing all other sub-simulation data one by one to obtain the node type corresponding to each node to be marked. Simultaneously, if a node to be marked has different actual voltage ranges under different driving parameters, after traversing each sub-simulation data, this node to be marked will have multiple node types.

[0096] This embodiment simulates the circuit under test based on different driving parameters to obtain sub-simulation data of the circuit under test under different operating states. Then, iterates through each sub-simulation data and marks the nodes whose actual voltage range is within a preset voltage range as the node type corresponding to the preset voltage range. This method avoids missing some nodes under different driving conditions and operating states during the marking process, making it more comprehensive and reliable.

[0097] In one optional embodiment of this disclosure, the above-mentioned driving parameters include at least: control signals and driving voltages.

[0098] The circuit under test is driven by a driving voltage and controlled by a control signal to operate under different states. By simply adjusting the control signal and the driving voltage, the actual operation of the circuit under test can be simulated to the greatest extent in the simulation environment. The simulation data obtained is more reliable, which further improves the reliability of the marking method of this embodiment.

[0099] In one optional embodiment of this disclosure, the marked node includes at least one of the power supply voltage terminal and the ground terminal of the circuit under test.

[0100] The voltages at the power supply and ground terminals are generally fixed, and their actual voltage range in the simulation data is also relatively fixed. Therefore, it is more efficient to identify the power supply and ground terminals as marked nodes in the circuit under test and then mark the nodes to be marked based on these marked nodes.

[0101] Please see Figure 5 In one embodiment of this disclosure, a verification method is provided, including the following steps 501-502:

[0102] Step 501: Obtain the node type of each node in the circuit under test.

[0103] The node type refers to the node type determined according to any of the marking methods mentioned above. The specific process for obtaining the node type of each node in the circuit under test and the corresponding beneficial effects have been described in detail in the above embodiments, and will not be repeated here.

[0104] Step 502: According to the node type of each node, verify the circuit under test in sequence based on the preset verification parameters of each node.

[0105] Verification refers to the process of testing and correcting the voltage and other parameters of each node in the circuit under test. In the embodiments of this disclosure, each node is first marked with a node type, such as input voltage VHV, output high-level voltage VOH, and bias voltage VBN. Then, based on the preset verification parameters corresponding to each node type, such as the corresponding verification voltage range, the nodes corresponding to each node type are verified in sequence. This method is more efficient than the traditional method of verifying each node one by one.

[0106] Please see Figure 6 In an optional embodiment of this disclosure, step 502, which involves sequentially verifying the circuit under test based on the preset verification parameters of each node according to the node type, includes the following steps 601-602:

[0107] Step 601: Determine the number of nodes in each node type.

[0108] For example, the number of nodes in the node type input voltage VHV is 10, the number of nodes in the node type output high-level voltage VOH is 7, and the number of nodes in the node type bias voltage VBN is 5.

[0109] Step 602: According to the order of the number of nodes from most to least, verify the circuit under test in turn based on the preset verification parameters of each node.

[0110] Continuing with the example in step 601 above, the nodes in each node type are checked sequentially according to the order of input voltage VHV, output high-level voltage VOH, and bias voltage VBN. The preset check parameters for the same node type are relatively consistent, which can complete the check of more nodes in a shorter time, resulting in relatively high efficiency.

[0111] In an optional embodiment of this disclosure, before step 502, which verifies the circuit under test sequentially based on the preset verification parameters of each node according to the node type of each node, the verification method further includes the following steps:

[0112] Each node in the circuit under test is categorized.

[0113] The category label is used to indicate whether the component corresponding to each node is a standard part or a non-standard part. The method for categorizing each node can be the same as in step B above, and will not be repeated here.

[0114] For the corresponding information, please refer to [link / reference]. Figure 7 Step 502 above, according to the node type of each node, sequentially verifies the circuit under test based on the preset verification parameters of each node, including the following steps 701-702:

[0115] Step 701: For the same node type, verify the nodes in the circuit under test that are marked as standard parts based on the preset verification parameters.

[0116] Step 702: Verify the nodes in the circuit under test that are marked as non-standard parts based on the preset verification parameters.

[0117] The preset verification parameters for standard parts are relatively fixed, while the preset verification parameters for non-standard parts also change or are adjusted gradually according to certain rules. In this embodiment of the present disclosure, when verifying each node, standard parts and non-standard parts are verified separately for the same type of node. This can avoid frequent changes or adjustments to the verification parameters and can greatly improve the verification efficiency to a certain extent.

[0118] In one optional embodiment of this disclosure, for the same node type, the nodes in the circuit under test marked as standard parts can be verified first based on preset verification parameters, and then the nodes in the circuit under test marked as non-standard parts can be verified based on preset verification parameters. The preset verification parameters of standard parts are relatively fixed and do not need to be frequently changed or adjusted. More nodes can be verified in a shorter time, and the verification efficiency is higher.

[0119] To implement the above marking method, one embodiment of this disclosure provides a marking device 800. Figure 8 A schematic architectural diagram of a marking device 800 is shown. The marking device 800 includes: a first acquisition module 810, a determination module 820, and a marking module 830, wherein:

[0120] The first acquisition module 810 is used to acquire simulation data for the circuit under test; wherein the simulation data includes at least the actual voltage range of each node to be marked in the circuit under test;

[0121] The determination module 820 is used to determine the preset voltage range of each node to be marked based on the preset voltage change of the marked nodes and at least some of the nodes to be marked in the circuit under test; wherein the preset voltage change is related to the circuit structure between the nodes to be marked and the marked nodes.

[0122] The marking module 830 is used to traverse the simulation data and mark the nodes to be marked in the simulation data whose actual voltage range is within the preset voltage range as the node type corresponding to the preset voltage range.

[0123] In an optional embodiment, there are multiple preset voltage ranges, and each preset voltage range corresponds to a different node type. The marking module 830 is specifically used to traverse the simulation data based on each preset voltage range and mark the nodes in the simulation data whose actual voltage range is within the current preset voltage range as the current node type corresponding to the current preset voltage range.

[0124] In an optional embodiment, the marking module 830 is further configured to determine the traversal order of different types of nodes to be marked based on the number of components between nodes to be marked and marked nodes of different types, wherein the components between nodes to be marked and their corresponding marked nodes of the same type are the same.

[0125] In an optional embodiment, the marking module 830 is further configured to: classify each node to be marked; wherein the class marking is used to characterize whether the component corresponding to the node to be marked is a standard part or a non-standard part; traverse the nodes to be marked in the simulation data that are classified as standard parts; and traverse the nodes to be marked in the simulation data that are classified as non-standard parts.

[0126] In an optional embodiment, the marking module 830 is specifically used to determine the device type of the standard component corresponding to each node to be marked; wherein different device types correspond to different preset voltage ranges.

[0127] In an optional embodiment, if the same node contains multiple operating states, the first acquisition module 810 is specifically used to perform simulation of the circuit under test based on different driving parameters to obtain sub-simulation simulation data of the circuit under test in different operating states; correspondingly, the marking module 830 is specifically used to traverse each sub-simulation simulation data in sequence and mark the nodes to be marked in the sub-simulation simulation data whose actual voltage range is within a preset voltage range as the node type corresponding to the preset voltage range.

[0128] In an optional embodiment, the driving parameters include at least: control signals and driving voltage.

[0129] In an optional embodiment, the marked node includes at least one of the power supply voltage terminal and the ground terminal of the circuit under test.

[0130] To implement the above verification method, one embodiment of this disclosure provides a verification device 900. Figure 9 A schematic diagram of a verification device 900 is shown. The verification device 900 includes: a second acquisition module 910 and a verification module 920, wherein:

[0131] The second acquisition module 910 is used to acquire the node type of each node in the circuit under test; wherein, the node type refers to the node type determined according to any of the above marking methods;

[0132] The verification module 920 is used to verify the circuit under test according to the node type of each node and based on the preset verification parameters of each node.

[0133] In an optional embodiment, the verification module 920 is specifically used to determine the number of nodes in each node type; and to verify the circuit under test sequentially based on the preset verification parameters of each node, in descending order of the number of nodes.

[0134] In an optional embodiment, the verification module 920 is further configured to classify each node in the circuit under test; wherein the classification is used to characterize whether the component corresponding to each node is a standard part or a non-standard part; for the same node type, the nodes in the circuit under test that are classified as standard parts are verified based on preset verification parameters; and the nodes in the circuit under test that are classified as non-standard parts are verified based on preset verification parameters.

[0135] Exemplary embodiments of this disclosure also provide a computer-readable storage medium that can be implemented as a program product including program code, which, when run on an electronic device, causes the electronic device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. In one embodiment, the program product can be implemented as a portable compact disc read-only memory (CD-ROM) and include program code, and can run on an electronic device, such as a personal computer. However, the program product of this disclosure is not limited thereto. In this document, the readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0136] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0137] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0138] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0139] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider). In embodiments of this disclosure, the program code stored in a computer-readable storage medium, when executed, can implement any step of the above-described marking and verification methods.

[0140] Please see Figure 10 The exemplary embodiments of this disclosure also provide an electronic device 1000, which can be a backend server of an information platform. Reference is made below. Figure 10 This electronic device 1000 will be described. It should be understood that... Figure 10 The electronic device 1000 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0141] like Figure 10 As shown, the electronic device 1000 is presented in the form of a general-purpose computing device. The components of the electronic device 1000 may include, but are not limited to: at least one processing unit 1010, at least one storage unit 1020, and a bus 1030 connecting different system components (including storage unit 1020 and processing unit 1010).

[0142] The storage unit stores program code, which can be executed by the processing unit 1010 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 1010 can perform the method steps shown in the figure above.

[0143] Storage unit 1020 may include volatile storage units, such as random access memory (RAM) 1021 and / or cache memory 1022, and may further include read-only memory (ROM) 1023.

[0144] Storage unit 1020 may also include a program / utility 1024 having a set (at least one) program module 1025, such program module 1025 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0145] Bus 1030 may include a data bus, an address bus, and a control bus.

[0146] Electronic device 1000 can also communicate with one or more external devices 2000 (e.g., keyboards, pointing devices, Bluetooth devices, etc.) via input / output (I / O) interface 1040. Electronic device 1000 can also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via network adapter 1050. As shown, network adapter 1050 communicates with other modules of electronic device 1000 via bus 1030. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0147] In this embodiment of the disclosure, when the program code stored in the electronic device is executed, it can implement any step of the above-mentioned marking method and verification method.

[0148] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to exemplary embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0149] Those skilled in the art will understand that various aspects of this disclosure can be implemented as systems, methods, or program products. Therefore, various aspects of this disclosure can be embodied in entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.” Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0150] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A method of marking, characterized in that, include: Acquire simulation data for the circuit under test; wherein the simulation data includes at least the actual voltage range of each node to be marked in the circuit under test; A preset voltage range for each node to be marked is determined based on a preset voltage change in the marked nodes and at least some of the nodes to be marked in the circuit under test; wherein the preset voltage change is related to the circuit structure between the nodes to be marked and the marked nodes; The simulation data is traversed, and the nodes to be marked in the simulation data whose actual voltage range is within the preset voltage range are marked as the node type corresponding to the preset voltage range.

2. The marking method according to claim 1, characterized in that, The number of preset voltage ranges is multiple, and each preset voltage range corresponds to a different node type. Therefore, the step of traversing the simulation data and marking the nodes in the simulation data whose actual voltage range falls within the preset voltage range as the node type corresponding to the preset voltage range includes: Based on each preset voltage range, the simulation data is traversed, and the nodes to be marked in the simulation data whose actual voltage range is within the current preset voltage range are marked as the current node type corresponding to the current preset voltage range.

3. The method of marking according to claim 2, wherein, The traversal order of the nodes to be marked for different types is determined based on the number of components between the nodes to be marked and the marked nodes for different types. The nodes to be marked for the same type have the same components as the corresponding marked nodes.

4. The method of marking of claim 2, wherein, Before traversing the simulation data based on each of the preset voltage ranges, the method further includes: Each node to be labeled is categorized; wherein, the category label is used to characterize whether the component corresponding to the node to be labeled is a standard part or a non-standard part; correspondingly, The step of traversing the simulation data based on each of the preset voltage ranges includes: The nodes to be labeled in the simulation data that are classified as standard parts are traversed. The nodes to be labeled in the simulation data that are classified as non-standard parts are traversed.

5. The method of marking according to claim 4, wherein, The process of classifying each of the nodes to be labeled includes: Determine the device type of the standard component corresponding to each of the nodes to be marked; wherein, the preset voltage range is different for different device types.

6. The method of marking of claim 1, wherein, If the same node contains multiple operating states, then acquiring the simulation data for the circuit under test includes: Simulations were performed on the circuit under test based on different driving parameters to obtain simulation data for each sub-simulation of the circuit under test under different operating states; correspondingly, The step of traversing the simulation data and marking the nodes to be marked in the simulation data whose actual voltage range falls within the preset voltage range as the node type corresponding to the preset voltage range includes: The sub-simulation data is traversed sequentially, and the nodes to be marked in the sub-simulation data whose actual voltage range is within the preset voltage range are marked as the node type corresponding to the preset voltage range.

7. The method of marking according to claim 6, wherein, The driving parameters include at least: control signals and driving voltage.

8. The method of marking of claim 1, wherein, The marked node includes at least one of the power supply voltage terminal and the ground terminal of the circuit under test.

9. A verification method, characterized in that, include: Obtain the node type of each node in the circuit under test; wherein, the node type refers to the node type determined by the marking method according to any one of claims 1-8; According to the node type of each node, the circuit under test is verified sequentially based on the preset verification parameters of each node.

10. The verification method according to claim 9, characterized in that, The step of verifying the circuit under test according to the node type of each node, based on the preset verification parameters of each node, includes: Determine the number of nodes in each of the node types; The circuit under test is verified sequentially based on the preset verification parameters of each node, in descending order of the number of nodes.

11. The method of claim 9, wherein, Before verifying the circuit under test sequentially based on the preset verification parameters of each node according to the node type, the method further includes: Each node in the circuit under test is categorized; wherein, the category label is used to characterize whether the component corresponding to each node is a standard part or a non-standard part; correspondingly, The step of verifying the circuit under test according to the node type of each node, based on the preset verification parameters of each node, includes: For the same node type, the nodes in the circuit under test that are categorized as standard parts are verified based on the preset verification parameters. The nodes in the circuit under test that are marked as non-standard parts are verified based on the preset verification parameters.

12. A marking device characterized by The device includes: The first acquisition module is used to acquire simulation data for the circuit under test; wherein the simulation data includes at least the actual voltage range of each node to be marked in the circuit under test. The determining module is used to determine a preset voltage range for each of the nodes to be marked based on a preset voltage change of the marked nodes and at least some of the nodes to be marked in the circuit under test; wherein the preset voltage change is related to the circuit structure between the nodes to be marked and the marked nodes; The marking module is used to traverse the simulation data and mark the nodes to be marked in the simulation data whose actual voltage range is within the preset voltage range as the node type corresponding to the preset voltage range.

13. A verification device, characterized in that, The device includes: The second acquisition module is used to acquire the node type of each node in the circuit under test; wherein, the node type refers to the node type determined by the marking method according to any one of claims 1-8; The verification module is used to verify the circuit under test sequentially based on the preset verification parameters of each node according to the node type of each node.

14. A computer readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the method according to any one of claims 1 to 9.

15. An electronic device, comprising: include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1 to 9 by executing the executable instructions.

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