Light-emitting control circuit and display panel

Abstract

The present invention discloses a light-emitting control circuit and a display panel. The light-emitting control circuit includes a shift register and a first output module. The shift register includes a start signal input terminal for inputting a start signal. The first output module is connected to an internal node of the shift register and receives a first potential signal and a second potential signal. The first output module is used to control the transmission of the first potential signal or the second potential signal to the output terminal of the light-emitting control circuit according to the potential of the internal node. Within a displayed frame, the width of a single pulse of the signal output by the output terminal of the light-emitting control circuit is associated with the number and period of pulses in the start signal. By associating the first output module with the internal node, the pulse width of the signal output by the output terminal of the light-emitting control circuit can be adjusted by adjusting the number of pulses of the start signal without changing the width of a single pulse of the start signal, thereby reducing the requirements for the clock control circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a light-emitting control circuit and a display panel. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) panels have experienced rapid development in recent years, driven by the rapid growth of the small and medium-sized smart mobile device market. They offer excellent mobility and high reliability. AMOLED panels consist of subpixels and corresponding pixel circuits. The pixel circuits generate and output drive currents to drive the subpixels to emit light, thereby achieving normal display on the panel. AMOLED panels also include light control circuits, which output light control signals to the corresponding pixel circuits to control whether the pixel circuits transmit the generated drive currents to the corresponding subpixels.

[0003] With the continuous development of organic light emitting diode (OLED) technology, the emission control signals output by traditional emission control circuits need to be adapted to the requirements of AMOLEDs. This requires increasing the duration of the emission control signals' inactive potential (the inactive potential refers to the potential signal when the pixel circuit controls the sub-pixel to be in a non-emitting state). This places higher demands on the clock control circuit and makes implementation more difficult. The clock control circuit is the circuit that controls the driver chip to generate the start signal. The driver chip outputs high and low level signals under the control of the clock control circuit. Summary of the Invention

[0004] The present invention provides a light emitting control circuit and a display panel, which can reduce the requirements on a clock control circuit and improve the feasibility of the circuit when realizing the adjustable pulse width of a light emitting control signal.

[0005] According to one aspect of the present invention, a light emitting control circuit is provided, comprising: a shift register, wherein the shift register comprises a start signal input terminal for inputting a start signal,

[0006] a first output module, the first output module being connected to an internal node of the shift register and receiving a first potential signal and a second potential signal, the potential of the internal node being controlled by the start signal, the first output module being configured to control the first potential signal or the second potential signal to be transmitted to an output end of the light-emitting control circuit according to the potential of the internal node;

[0007] Wherein, within a displayed frame, the width of a single pulse of the signal outputted from the output terminal of the light emitting control circuit is associated with the number and period of pulses in the start signal.

[0008] Optionally, the first output module includes a first output unit and a second output unit;

[0009] The control end of the first output unit is connected to the internal node, and the first output unit is used to be turned on or off according to the potential of its own control end, and to control the second potential signal to be transmitted to the output end of the light emitting control circuit when turned on;

[0010] The control end of the second output unit is connected to the internal node. The second output unit is used to be turned on or off according to the potential of its own control end, and to control the first potential signal to be transmitted to the output end of the light emitting control circuit when turned on.

[0011] Optionally, the first output unit includes a first transistor, a first electrode of the first transistor is connected to the second potential signal, a second electrode of the first transistor is connected to the output end of the light emitting control circuit, and a gate of the first transistor is connected to the internal node;

[0012] The second output unit includes a second transistor, a first electrode of the second transistor is connected to the first potential signal, a second electrode of the second transistor is connected to the output end of the light emitting control circuit, and a gate of the second transistor is connected to the internal node.

[0013] Optionally, the shift register includes a second output module, a third output module and an output control module, and the control end of the first output module is connected to the control end of the third output module;

[0014] The output control module is used to control the potential of the control end of the second output module and the control end of the third output module according to the start signal, the first clock signal, and the first potential signal;

[0015] The second output module is configured to be turned on or off according to the potential of its own control terminal, and to control the second potential signal to be transmitted to the output terminal of the shift register when turned on;

[0016] The control end of the third output module serves as the internal node and is connected to the first output module. The third output module is used to turn on or off according to the potential of its own control end, and when turned on, controls the second clock signal to be transmitted to the output end of the shift register.

[0017] Optionally, the output control module includes a first output control unit and a second output control unit, the first output control unit includes a first control end, a second control end, a first end, a second end, and a third end, the first control end of the first output control unit is connected to the first clock signal, the second control end of the first output control unit is connected to the control end of the third output module, the first end of the first output control unit is connected to the first potential signal, the second end of the first output control unit is connected to the first clock signal, and the third end of the first output control unit is connected to the control end of the second output module, and the first output control unit is configured to control the transmission of the first clock signal and the first potential signal to the control end of the second output module according to the first clock signal and the potential of the control end of the third output module;

[0018] The second output control unit includes a first control end, a second control end, a third control end, a first end, a second end, and a third end. The first control end of the second output control unit is connected to the first clock signal, the second control end of the second output control unit is connected to the control end of the second output module, the third control end of the second output control unit is connected to the second clock signal, the first end of the second output control unit is connected to the start signal, the second end of the second output control unit is connected to the second potential signal, and the third end of the second output control unit is connected to the control end of the third output module. The second output control unit is used to control the transmission of the start signal and the second potential signal to the control end of the third output module according to the first clock signal, the potential of the control end of the second output module, and the second clock signal.

[0019] Optionally, the first output control unit includes a third transistor and a fourth transistor, a first electrode of the third transistor is connected to the first potential signal, a second electrode of the third transistor is connected to the control terminal of the second output module, a gate of the third transistor is connected to the first clock signal, a first electrode of the fourth transistor is connected to the first clock signal, a second electrode of the fourth transistor is connected to the control terminal of the second output module, and a gate of the fourth transistor is connected to the control terminal of the third output module;

[0020] The second output control unit includes a fifth transistor, a sixth transistor, and a seventh transistor, wherein a first electrode of the fifth transistor is connected to the start signal, a second electrode of the fifth transistor is connected to the control terminal of the third output module, and a gate of the fifth transistor is connected to the first clock signal. A first electrode of the sixth transistor is connected to the control terminal of the third output module, a second electrode of the sixth transistor is connected to the second electrode of the seventh transistor, and a gate of the sixth transistor is connected to the second clock signal. A first electrode of the seventh transistor is connected to the second potential signal, and a gate of the seventh transistor is connected to the control terminal of the second output module.

[0021] Optionally, the third output module also includes an eighth transistor, the first electrode of the eighth transistor is connected to the second electrode of the fifth transistor, the first electrode of the eighth transistor is connected to the first electrode of the sixth transistor, the first electrode of the eighth transistor is also connected to the gate of the fourth transistor, the second electrode of the eighth transistor is connected to the control end of the third output module, and the gate of the eighth transistor is connected to the first potential signal.

[0022] Optionally, during the stage when the start signal and the first clock signal output the second potential signal at the output end of the light-emitting control circuit, the pulse widths, pulse periods, and pulse start times of the signals are the same.

[0023] Optionally, within a displayed frame, the pulse width of the signal outputted from the output end of the light emitting control circuit is equal to the product of the number of pulses of the start signal and the pulse period of the start signal.

[0024] Optionally, the second output module includes a ninth transistor and a first capacitor, the first electrode of the ninth transistor is connected to the second potential signal, the second electrode of the ninth transistor is connected to the output end of the shift register, the gate of the ninth transistor serves as the control end of the second output module, the first end of the first capacitor is connected to the first electrode of the ninth transistor, and the second end of the first capacitor is connected to the gate of the ninth transistor;

[0025] The third output module includes a tenth transistor and a second capacitor, the first electrode of the tenth transistor is connected to the second clock signal, the second electrode of the tenth transistor is connected to the output end of the shift register, the gate of the tenth transistor serves as the control end of the third output module, the first end of the second capacitor is connected to the second electrode of the tenth transistor, and the second end of the second capacitor is connected to the gate of the tenth transistor.

[0026] According to another aspect of the present invention, a display panel is provided, comprising a plurality of rows of pixel circuits and a light-emitting control circuit as described above, wherein the output end of the light-emitting control circuit is connected to the pixel circuit of the corresponding row for outputting a light-emitting control signal to the pixel circuit; the light-emitting control circuit comprises at least two continuously cascaded shift registers, wherein the output end of the shift register of the previous stage is connected to the start signal output end of the shift register of the next stage.

[0027] An embodiment of the present invention provides a light-emitting control circuit, comprising a shift register and a first output module. The shift register includes a start signal input terminal for inputting a start signal. The first output module is configured to control the transmission of a first potential signal or a second potential signal to an output terminal of the light-emitting control circuit based on the potential of an internal node of the shift register. The potential of the internal node of the shift register is controlled by the start signal. Within a displayed frame, the width of a single pulse of a signal output by the output terminal of the light-emitting control circuit is associated with the number and period of pulses in the start signal. By associating the first output module with the internal node, the light-emitting control signal output by the first output module is controlled by the internal node. The potential of the internal node is related to the start signal input by the shift register, thereby causing the width of a single pulse of the signal output by the output terminal of the light-emitting control circuit to be associated with the number and period of pulses of the start signal. As an optional approach, increasing the number of pulses of the start signal can increase the width of a single pulse of the signal output by the light-emitting control circuit. Specifically, at the end of the pulse period of the original start signal, multiple pulses having the same pulse width as the original start signal are added, so as to achieve an increase in the number of pulses without changing the width of a single pulse of the start signal. Without changing the width of a single pulse of the start signal SIN, the width of a single pulse of the signal output from the output end of the light-emitting control circuit can be adjusted by adjusting the number of pulses of the start signal, thereby reducing the high requirements on the clock control circuit and making the circuit highly feasible.

[0028] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 It is a structural diagram of a light-emitting control circuit;

[0031] Figure 2 1 is a timing diagram of a signal output from an output terminal OUT of a light emitting control circuit after the frequency of a start signal is increased;

[0032] Figure 3 This is a structural diagram of a light-emitting control circuit provided by an embodiment of the present invention;

[0033] Figure 4 is a structural diagram of another light-emitting control circuit provided by an embodiment of the invention;

[0034] Figure 5 This is a driving timing diagram of a light emitting control circuit provided by an embodiment of the present invention;

[0035] Figure 6 is a structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0036] Figure 7 is a structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0037] Figure 8 This is a driving timing diagram of another light emitting control circuit provided by an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the working state transition of a light emitting control circuit provided by an embodiment of the present invention;

[0039] Figure 10 It is a structural schematic diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] As described in the background art, in order to increase the time of the ineffective potential in the light-emitting control signal, the requirements for the clock control circuit are relatively high. The inventors have found that the reason for the above problem is that the light-emitting control signal is a signal after the start signal is shifted. Therefore, in order to adjust the time of the ineffective potential of the light-emitting control signal within the set time (within a displayed frame), it is necessary to adjust the number of pulses of the start signal within the set time. Because within the set time, the pulses of the start signal are uniformly set, that is, the interval time between the ineffective potentials of any two adjacent pulses is equal. Therefore, within the set time, in order to change the time of the ineffective potential of the light-emitting control signal, it is necessary to change the number of pulses of the start signal, which in turn causes the pulse width to change accordingly. Specifically, the specific structure of a light-emitting control circuit in the prior art is used for illustration. Figure 1 : This is a structural diagram of a light-emitting control circuit. The light-emitting control circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The light-emitting control circuit is also connected to a first clock signal CK1, a second clock signal CK2, a first potential signal VGL, a second potential signal VGH, and a start signal SIN. For specific circuit connection relationships, see Figure 1 . Figure 1 The output terminal OUT of the light emitting control circuit shown in FIG is used to shift and output the start signal SIN. Figure 2 The timing diagram of the signal output from the output terminal OUT of the light emitting control circuit after adjusting the number of pulses in the start signal SIN is based on Figure 1 The light control circuit shown in FIG. 1 is set to have a pulse of the light control signal EM outputted from the output terminal OUT of the light control circuit within the set period T before the start signal SIN is adjusted, and the pulse width is E1 (in terms of Figure 2For example, the pulse refers to the high level part, and accordingly, the pulse width refers to the high level duration. The meaning of the pulse width is the same as this below and will not be repeated). The non-effective potential of the light emitting control signal EM (for Figure 2 , the time of the non-effective potential is a high level) is E1. In order to increase the high level time of the light-emitting control signal EM, after increasing the number of pulses in the start signal SIN within the set period T, illustratively, four pulses are evenly set within the set time T, and the width of a single pulse is E2. Since the light-emitting control signal EM is a signal after the start signal SIN is shifted, the time of the non-effective potential in the light-emitting control signal EM is equal to 4*E2. Six pulses can also be evenly set within the set period T, and the width of a single pulse is E3, and E3 is less than E2. From the above analysis, it can be seen that in order to adjust the time of the non-effective potential of the light-emitting control signal, it is necessary to change the number of pulses of the start signal SIN within the set period T. Since the pulses are evenly set within the set period T, the width of a single pulse of the start signal SIN will also change accordingly. The prior art changes the time of the non-effective potential of the light-emitting control signal EM within a set period T (that is, the sum of the widths of all pulses within a period T). The start signal SIN is generated by the driver chip and output to the light-emitting control circuit. Under the control of the clock control circuit, the driver chip outputs a high level or a low level. Because the pulses of the light-emitting control signal are evenly set within the set period T, the clock control circuit needs to strictly control the driver chip to output a high level at the set time point and a low level at the set time point, and also needs to strictly time the rising edge to ensure the width of a single pulse. Therefore, after changing the number of pulses of the start signal SIN, the width of a single pulse of the start signal SIN changes, and the requirements for the clock control circuit that controls the driver chip to output the start signal SIN are relatively high. In response to the above technical problems, an embodiment of the present invention provides a new light-emitting control circuit. Figure 3 A schematic diagram of a light emitting control circuit according to an embodiment of the present invention is provided. Figure 3 , the light emitting control circuit includes: a shift register 1, the shift register 1 includes a start signal input terminal for inputting a start signal SIN,

[0043] a first output module 11 connected to an internal node of the shift register 1 and receiving a first potential signal VGL and a second potential signal VGH. The potential of the internal node is controlled by a start signal. The first output module 11 is used to control the first potential signal VGL or the second potential signal VGH to be transmitted to an output terminal OUT1 of the light emitting control circuit according to the potential of the internal node;

[0044] In one frame of display, the width of a single pulse of the signal outputted from the output terminal of the light emitting control circuit is associated with the number and period of pulses in the start signal SIN.

[0045] Exemplarily, the potentials of the first potential signal VGL and the second potential signal VGH are high and low levels relative to each other. For example, the first potential signal VGL is low and the second potential signal VGH is high; or the first potential signal VGL is high and the second potential signal VGH is low. The first output module 11 is configured to control the first potential signal VGL or the second potential signal VGH to be transmitted to the output terminal OUT1 of the light-emitting control circuit based on the potential of the internal node. A specific implementation method may be that the first output module 11 controls the second potential signal VGH to be transmitted to the output terminal OUT1 of the light-emitting control circuit in response to a low level of the internal node; and controls the first potential signal VGL to be transmitted to the output terminal OUT1 of the light-emitting control circuit in response to a high level of the internal node. Simultaneously, the potential of the internal node is controlled by the start signal SIN, that is, the potential of the internal node is related to the start signal SIN input to the shift register 1, thereby causing the width of a single pulse of the signal outputted from the output terminal OUT1 of the light-emitting control circuit to be associated with the number and period of pulses of the start signal SIN. As an optional association method, within a displayed frame, without changing the width of a single pulse in the start signal SIN, the number of pulses of the start signal SIN is increased. Exemplarily, in the prior art, within a frame, the start signal SIN is generally one pulse (when the pulse width of the signal output by the light-emitting control circuit is not adjusted), and the pulse width is set to F. In this embodiment, the number of pulses of the start signal SIN is increased by sequentially adding multiple pulses with a pulse width of F at the end of an original pulse cycle, so as to increase the number of pulses of the start signal SIN without changing the width of a single pulse in the start signal SIN, and the greater the number of pulses in the start signal SIN, the greater the single pulse width of the signal output by the light-emitting control circuit. In the prior art, within a displayed frame, changing the number of pulses in the start signal SIN causes the width of a single pulse to change, thereby placing higher requirements on the clock control circuit. When changing the number of pulses in the start signal SIN, this embodiment simply adds multiple pulses with the same pulse width as the original start signal SIN at the end of the pulse cycle of the original start signal SIN. This achieves the goal of increasing the number of pulses without changing the width of a single pulse of the start signal, thereby reducing the high requirements placed on the clock control circuit and avoiding increasing the difficulty of implementing the solution. It is worth noting that the signal output by the output terminal OUT1 of the light-emitting control circuit is the light-emitting control signal, which is used to control whether the light-emitting module in the pixel circuit emits light.

[0046] By associating the first output module with the internal node of the shift register, the signal output from the output end of the light-emitting control circuit is controlled by the internal node of the shift register. The potential of the internal node is related to the start signal input by the shift register, thereby making the width of a single pulse of the signal output by the light-emitting control circuit associated with the number of pulses and the period of the start signal input by the shift register. As an optional method, increasing the number of pulses of the start signal can increase the width of a single pulse of the signal output by the light-emitting control circuit. Specifically, multiple pulses with the same pulse width as the original start signal are added at the end of the pulse period of the original start signal to achieve the goal of not changing the width of a single pulse of the start signal and increasing the number of pulses. Without changing the width of a single pulse of the start signal SIN, by adjusting the number of pulses of the start signal, the pulse width of the signal output by the light-emitting control circuit is adjusted, reducing the high requirements placed on the clock control circuit, and the circuit is highly feasible.

[0047] Figure 4 A schematic diagram of another display panel structure provided by an embodiment of the present invention, referring to Figure 4 Optionally, the shift register 1 includes: a second output module 12, a third output module 13 and an output control module 14, and the control end of the first output module 11 is connected to the control end N2 of the third output module 13;

[0048] The output control module 14 is used to control the potential of the control terminal N1 of the second output module 12 and the control terminal N2 of the third output module 13 according to the start signal SIN, the first clock signal CK1 and the first potential signal VGL;

[0049] The second output module 12 is used to be turned on or off according to the potential of its own control terminal N1, and when turned on, controls the second potential signal VGH to be transmitted to the output terminal OUT2 of the shift register;

[0050] The control terminal N2 of the third output module 13 is connected to the first output module 11 as an internal node. The third output module 13 is used to turn on or off according to the potential of its own control terminal N2, and control the second clock signal CK2 to be transmitted to the output terminal OUT2 of the shift register when turned on.

[0051] The control terminal N2 of the third output module 13 is an internal node connected to the first output module 11. The first output module 11 is used to control the transmission of the first potential signal VGL or the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit based on the potential of the control terminal N2 of the third output module 13. Turning on the second output module 12 means connecting the second potential signal VGH to the output terminal OUT2 of the shift register. Turning off the second output module 12 means severing the connection between the second potential signal VGH and the output terminal OUT2 of the shift register. The turning on and off of other modules is similar in principle and will not be further described here. Optionally, the output control module 14 also receives the second potential signal VGH and the second clock signal CK2.

[0052] Figure 5 A driving timing diagram of a light emitting control circuit provided by an embodiment of the present invention, Figure 5 The timing diagram shown applies to Figure 4 The light control circuit shown in the figure is Figure 4 and Figure 5 The operation process of the light-emitting control circuit includes a first phase ta, a second phase tb, and a third phase tc. The second phase tb includes n state phases t2, and each state phase t2 includes a first sub-phase t21, a second sub-phase t22, a third sub-phase t23, and a fourth sub-phase t24. The first potential signal VGL is at a low level, and the second potential signal VGH is at a high level. Where n ≥ 2, n is equal to the number of low levels in the start signal SIN.

[0053] During the first phase ta, when the start signal SIN is at a high level and the first clock signal CK1 is at a low level, the first clock signal CK1 controls the output control module 14 to transmit the start signal SIN to the control terminal N2 of the third output module 13, thereby shutting down the third output module 13. It also controls the output control module 14 to transmit the first potential signal VGL to the control terminal N1 of the second output module 12, thereby turning on the second output module 12. The turned-on second output module 12 controls the second potential signal VGH to be transmitted to the output terminal OUT2 of the shift register. Furthermore, because the control terminal N2 of the third output module 13 is at a high level, the potential of the control terminal N2 of the third output module 13 controls the first output module 11 to transmit the first potential signal VGL to the output terminal OUT1 of the light-emitting control circuit. In subsequent phases of the first phase ta, after the first clock signal CK1 transitions to a high level and the second clock signal CK2 transitions to a low level, the potentials of the control terminals N1 of the second output module 12 and N2 of the third output module 13 remain unchanged, causing the potentials of the output terminals OUT2 of the shift register and OUT1 of the light-emitting control circuit to remain unchanged.

[0054] In the first sub-phase t21, the output control module 14, in response to the low level of the first clock signal CK1, controls the transmission of the first potential signal VGL to the control terminal N1 of the second output module 12 and controls the transmission of the start signal SIN to the control terminal N2 of the third output module 13. In response to the low level of its own control terminal N1, the second output module 12 is turned on to transmit the second potential signal VGH to the output terminal OUT2 of the shift register. In response to the low level of its own control terminal N2, the third output module 13 is turned on to transmit the second clock signal CK2 to the output terminal OUT2 of the shift register. Because the second clock signal CK2 is at a high level, the potential of the output terminal OUT2 of the shift register is at a high level. In response to the low level of the control terminal N2 of the third output module 13, the first output module 11 transmits the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit.

[0055] In the second sub-phase t22, the first clock signal CK1, the second clock signal CK2, and the start signal SIN are all at a high level. In response to the high level of the first clock signal CK1, the output control module 11 blocks the start signal SIN from being transmitted to the control terminal N2 of the third output module 13. The control terminal N2 of the third output module 13 maintains the voltage level from the previous phase, i.e., the first sub-phase t21. Simultaneously, in response to the low level of the control terminal N2 of the third output module 13, the output control module 14 transmits the first clock signal CK1 to the control terminal N1 of the second output module 12. In response to the high level of its control terminal N1, the second output module 12 is turned off. In response to the low level of its control terminal N2, the third output module 13 is turned on, thereby transmitting the second clock signal CK2 to the output terminal OUT2 of the shift register. In response to the voltage level of the control terminal N2 of the third output module 13, the first output module 11 controls the second voltage signal VGH to be transmitted to the output terminal OUT1 of the light-emitting control circuit.

[0056] In the third sub-phase t23, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the start signal SIN is at a high level. In response to the high level of the first clock signal CK1, the output control module 14 blocks the start signal SIN from being transmitted to the control terminal N2 of the third output module 13. The control terminal N2 of the third output module 13 maintains the voltage level from the previous phase, i.e., the second sub-phase t22. Simultaneously, in response to the low level of the control terminal N2 of the third output module 13, the output control module 14 transmits the first clock signal CK1 to the control terminal N1 of the second output module 12. In response to the high level of its control terminal N1, the second output module 12 is turned off. In response to the low level of its control terminal N2, the third output module 13 is turned on, thereby transmitting the second clock signal CK2 to the output terminal OUT2 of the shift register. In response to the voltage level of the control terminal N2 of the third output module 13, the first output module 11 controls the second voltage signal VGH to be transmitted to the output terminal OUT1 of the light-emitting control circuit.

[0057] In the fourth sub-phase t24, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, and the start signal SIN is at a high level. In response to the high level of the first clock signal CK1, the output control module 14 blocks the start signal SIN from being transmitted to the control terminal N2 of the third output module 13. The control terminal N2 of the third output module 13 maintains the voltage level from the previous phase, i.e., the third sub-phase t23. Simultaneously, in response to the low level of the control terminal N2 of the third output module 13, the output control module 14 transmits the first clock signal CK1 to the control terminal N1 of the second output module 12. In response to the high level of its control terminal N1, the second output module 12 is turned off. In response to the low level of its control terminal N2, the third output module 13 is turned on, thereby transmitting the second clock signal CK2 to the output terminal OUT2 of the shift register. In response to the voltage level of the control terminal N2 of the third output module 13, the first output module 11 controls the second voltage signal VGH to be transmitted to the output terminal OUT1 of the light-emitting control circuit.

[0058] In the second phase tb, each state phase t2 is continuously executed until the second phase tb ends. In the second phase tb, the start signal SIN includes three low levels, and within each low-level period, the signal output by the output terminal OUT1 of the light-emitting control circuit is a high level. By increasing the number of low levels in the start signal SIN, the duration of the high level of the signal output by the output terminal OUT1 of the light-emitting control circuit can be extended. The first pulse of the start signal SIN can be regarded as the original pulse. In this embodiment, at the end of the pulse period of the original start signal SIN (i.e., the end of the first state phase t2), multiple pulses with the same pulse width as the original start signal SIN are added to achieve the goal of increasing the number of pulses while maintaining the width of a single pulse of the start signal SIN.

[0059] During the third phase tc, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal SIN is at a high level. In response to the low level of the first clock signal CK1, the output control module 14 transmits the start signal SIN to the control terminal N2 of the third output module 13. The third output module 13 is turned off in response to the high level of its own control terminal N2. In response to the low level of the first clock signal CK1, the output control module 14 transmits the first potential signal VGL to the control terminal N1 of the second output module 12, thereby turning on the second output module 12. The output control module 14 then transmits the second potential signal VGH to the output terminal OUT2 of the shift register. Simultaneously, in response to the high level of the control terminal N2 of the third output module 13, the first output module 11 transmits the first potential signal VGL to the output terminal OUT1 of the light-emitting control circuit. At a subsequent moment in the third stage tc, after the first clock signal CK1 jumps to a high level and the second clock signal CK2 jumps to a low level, the potential of the control terminal N1 of the second output module 12 and the control terminal N2 of the third output module 13 remain unchanged, so that the potential of the output terminal OUT2 of the shift register and the output terminal OUT1 of the light-emitting control circuit remain unchanged.

[0060] Based on the above embodiments, Figure 6 This is a schematic diagram of another light emitting control circuit provided by an embodiment of the present invention, referring to Figure 6 , Optionally, the first output module 11 includes a first output unit 111 and a second output unit 112;

[0061] The control terminal of the first output unit 111 is connected to the internal node. The first output unit 111 is used to be turned on or off according to the potential of its own control terminal, and when turned on, controls the second potential signal VGH to be transmitted to the output terminal OUT1 of the light emitting control circuit;

[0062] The control terminal of the second output unit 112 is connected to the internal node. The second output unit 112 is configured to be turned on or off according to the potential of its own control terminal, and to control the first potential signal VGL to be transmitted to the output terminal OUT1 of the light emitting control circuit when turned on.

[0063] Exemplarily, when the shift register 1 includes a second output module 12, a third output module 13, and an output control module 14, the control terminal of the first output unit 111 is connected to an internal node, that is, the control terminal of the first output unit 111 is connected to the control terminal N2 of the third output module 13. The control terminal of the second output unit 112 is connected to an internal node, that is, the control terminal of the second output unit 112 is connected to the control terminal N2 of the third output module 13. When the potential of the control terminal N2 of the third output module 13 is low, the first output unit 111 is turned on in response to the low level of the control terminal N2 of the third output module 13, and transmits the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit. The second output unit 112 is turned off in response to the low level of the control terminal N2 of the third output module 13. When the potential of the control terminal N2 of the third output module 13 is at a high level, the second output unit 112 is turned on in response to the high level of the control terminal N2 of the third output module 13 and transmits the first potential signal VGL to the output terminal OUT1 of the light-emitting control circuit. The first output unit 111 is turned off in response to the high level of the control terminal N2 of the third output module 13. That is, at the same time, only one of the first output unit 111 and the second output unit 112 is turned on.

[0064] Continue to refer Figure 6 Optionally, the output control module 14 includes a first output control unit 141 and a second output control unit 142. The first output control unit 141 includes a first control terminal A1, a second control terminal A2, a first terminal, a second terminal, and a third terminal. The first control terminal A1 of the first output control unit 141 is connected to the first clock signal CK1, and the second control terminal A2 of the first output control unit 141 is connected to the control terminal N2 of the third output module 13. The first terminal of the first output control unit 141 is connected to the first potential signal VGL, the second terminal of the first output control unit 141 is connected to the first clock signal CK1, and the third terminal of the first output control unit 141 is connected to the control terminal N1 of the second output module 12. The first output control unit 141 is configured to control the first clock signal CK1 and the first potential signal VGL to be transmitted to the control terminal N1 of the second output module 12 according to the first clock signal CK1 and the potential of the control terminal N2 of the third output module 13;

[0065] The second output control unit 142 includes a first control end, a second control end, a third control end, a first end, a second end and a third end. The first control end of the second output control unit 142 is connected to the first clock signal CK1, the second control end of the second output control unit 142 is connected to the control end N1 of the second output module 12, the third control end of the second output control unit 142 is connected to the second clock signal CK2, the first end of the second output control unit 142 is connected to the start signal SIN, the second end of the second output control unit 142 is connected to the second potential signal VGH, and the third end of the second output control unit 142 is connected to the control end N2 of the third output module 13. The second output control unit 142 is used to control the transmission of the start signal SIN and the second potential signal VGH to the control end N2 of the third output module 13 according to the first clock signal CK1, the potential of the control end N1 of the second output module 12 and the second clock signal CK2.

[0066] The first output control unit 141 is configured to control the transmission of the first clock signal CK1 and the first potential signal VGL to the control terminal N1 of the second output module 12 based on the first clock signal CK1 and the potential of the control terminal N2 of the third output module 13. The first output control unit 141 controls whether to transmit the first potential signal VGL to the control terminal N1 of the second output module 12 in response to the potential of the first clock signal CK1 at its first control terminal A1. The first output control unit 141 also controls whether to transmit the first clock signal CK1 to the control terminal N1 of the second output module 12 in response to the potential of the control terminal N2 of the third output module 13. For example, when the first clock signal CK1 is at a low level, the first output control unit 141 is controlled to transmit the first potential signal VGL to the control terminal N1 of the second output module 12. When the control terminal N2 of the third output module 13 is at a low level, the first output control unit 141 is controlled to transmit the first clock signal CK1 to the control terminal N1 of the second output module 12.

[0067] The second output control unit 142 is configured to control the transmission of the start signal SIN and the second potential signal VGH to the control terminal N2 of the third output module 13 based on the first clock signal CK1, the potential of the control terminal N1 of the second output module 12, and the second clock signal CK2. The second output control unit 142 controls whether to transmit the start signal SIN to the control terminal N2 of the third output module 13 in response to the potential of the first clock signal CK1. The second output control unit 142 also controls whether to transmit the second potential signal VGH to the control terminal N2 of the third output module 13 in response to the second clock signal CK2 and the potential of the control terminal N1 of the second output module 12. For example, when the first clock signal CK1 is at a low level, the first clock signal CK1 controls the second output control unit 142 to transmit the start signal SIN to the control terminal N2 of the third output module 13. When the second clock signal CK2 is at a low level and the control terminal N1 of the second output module 12 is at a low level, the second clock signal CK2 and the potential of the control terminal N1 of the second output module 12 control the second output control unit 142 to transmit the second potential signal VGH to the control terminal N2 of the third output module 13.

[0068] Continue to refer Figure 6 Optionally, the start signal SIN and the first clock signal CK1 have the same pulse width, pulse period, and pulse start time during the stage when the output terminal OUT1 of the light emitting control circuit outputs the second potential signal VGH.

[0069] During the stage where the output terminal OUT1 of the light-emitting control circuit outputs the second potential signal VGH, if the start signal SIN is different from the signal of the first clock signal CK1, illustratively, when the start signal SIN is at a low level, the first clock signal CK1 is at a high level, the second output control unit 142 transmits the start signal SIN to the control terminal N2 of the third output module 13 in response to the low level of the first clock signal CK1, the potential of the control terminal N2 of the third output module 13 is at a high level, and the first output module 11 transmits the first potential signal VGL to the output terminal OUT1 of the light-emitting control circuit in response to the high level of the control terminal N2 of the third output module 13, then the signal output by the output terminal OUT1 of the light-emitting control circuit is the first potential signal VGL. Therefore, only when the start signal SIN is the same as the first clock signal CK1, the start signal SIN is at a low level and the first clock signal CK1 is at a low level, the second output control unit 142 transmits the low level of the start signal SIN to the control terminal N2 of the third output module 13, and the first output module 11 responds to the low level of the control terminal N2 of the third output module 13 and transmits the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit, can it be ensured that the output terminal OUT1 of the light-emitting control circuit outputs the second potential signal VGH.

[0070] Figure 7 A schematic structural diagram of another light emitting control circuit provided by an embodiment of the present invention is shown. Figure 7 Corresponds to Figure 6 A specific circuit structure, refer to Figure 6 and Figure 7 Optionally, the first output unit 111 includes a first transistor T1, a first electrode of the first transistor T1 is connected to the second potential signal VGH, a second electrode of the first transistor T1 is connected to the output terminal OUT1 of the light emitting control circuit, and a gate of the first transistor T1 is connected to the internal node;

[0071] The second output unit 112 includes a second transistor T2 , a first electrode of the second transistor T2 is connected to the first potential signal VGL, a second electrode of the second transistor T2 is connected to the output terminal OUT1 of the light emitting control circuit, and a gate of the second transistor T2 is connected to the internal node.

[0072] The gate of the first transistor T1 is connected to an internal node, that is, the gate of the first transistor T1 is connected to the control terminal N2 of the third output module 13. The gate of the second transistor T2 is connected to an internal node, that is, the gate of the second transistor T2 is connected to the control terminal N2 of the third output module 13. The channel types of the first transistor T1 and the second transistor T2 are opposite, so that at the same time, only one of the first transistor T1 and the second transistor T2 is turned on. The first transistor T1 is turned on or off according to the potential of the control terminal N2 of the third output module 13, and when turned on, transmits the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit. The second transistor T2 is turned on or off according to the potential of the control terminal N2 of the third output module 13, and when turned on, transmits the first potential signal VGL to the output terminal OUT1 of the light-emitting control circuit. The first output unit 111 includes only one transistor T1, and the second output unit 112 includes only one transistor, resulting in a simple structure and easy implementation.

[0073] Continue to refer Figure 6 and Figure 7 Optionally, the first output control unit 141 includes a third transistor T3 and a fourth transistor T4, a first electrode of the third transistor T3 is connected to the first potential signal VGL, a second electrode of the third transistor T3 is connected to the control terminal N1 of the second output module 12, a gate of the third transistor T3 is connected to the first clock signal CK1, a first electrode of the fourth transistor T4 is connected to the first clock signal CK1, a second electrode of the fourth transistor T4 is connected to the control terminal N1 of the second output module 12, and a gate of the fourth transistor T4 is connected to the control terminal N2 of the third output module 13;

[0074] The second output control unit 142 includes a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. The first electrode of the fifth transistor T5 is connected to the start signal SIN, the second electrode of the fifth transistor T5 is connected to the control terminal N2 of the third output module 13, and the gate of the fifth transistor T5 is connected to the first clock signal CK1. The first electrode of the sixth transistor T6 is connected to the control terminal N2 of the third output module 13, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, and the gate of the sixth transistor T6 is connected to the second clock signal CK2. The first electrode of the seventh transistor T7 is connected to the second potential signal VGH, and the gate of the seventh transistor T7 is connected to the control terminal N1 of the second output module 12.

[0075] The fifth transistor T5, the sixth transistor T6, and the fourth transistor T4 may be directly or indirectly connected to the control terminal N2 of the third output module 13. In this embodiment, they are indirectly connected to the control terminal N2 of the third output module 13 via a normally-on eighth transistor T8. Optionally, the third output module 13 further includes an eighth transistor T8, wherein a first electrode of the eighth transistor T8 is connected to the second electrode of the fifth transistor T5, a first electrode of the eighth transistor T8 is connected to the first electrode of the sixth transistor T6, a first electrode of the eighth transistor T8 is also connected to the gate of the fourth transistor T4, a second electrode of the eighth transistor T8 is connected to the control terminal N2 of the third output module 13, and the gate of the eighth transistor T8 is connected to the first potential signal VGL.

[0076] The third transistor T3 is turned on or off according to the first clock signal CK1, and when turned on, transmits the first potential signal VGL to the control terminal N1 of the second output module 12. The fourth transistor T4 is turned on or off according to the potential of the control terminal N2 of the third output module 13, and when turned on, transmits the first clock signal CK1 to the control terminal N1 of the second output module 12. The fifth transistor T5 is turned on or off according to the first clock signal CK1, and when turned on, transmits the start signal SIN to the control terminal N2 of the third output module 13. The sixth transistor T6 is turned on or off according to the second clock signal CK2, and the seventh transistor T7 is turned on or off according to the potential of the control terminal N1 of the second output module 12. When the sixth and seventh transistors T6 and T7 are turned on simultaneously, the second potential signal VGH is transmitted to the control terminal N2 of the third output module 13 via the turned-on sixth and seventh transistors T6 and T7.

[0077] Continue to refer Figure 6 and Figure 7Optionally, the second output module 12 includes a ninth transistor T9 and a first capacitor C1, the first electrode of the ninth transistor T9 is connected to the second potential signal VGH, the second electrode of the ninth transistor T9 is connected to the output terminal OUT2 of the shift register, the gate of the ninth transistor T9 serves as the control terminal N1 of the second output module 12, the first end of the first capacitor C1 is connected to the first electrode of the ninth transistor T9, and the second end of the first capacitor C1 is connected to the gate of the ninth transistor T9;

[0078] The third output module 13 includes a tenth transistor T10 and a second capacitor C2. The first electrode of the tenth transistor T10 is connected to the second clock signal CK2, the second electrode of the tenth transistor T10 is connected to the output end OUT2 of the shift register, the gate of the tenth transistor T10 serves as the control end N2 of the third output module 13, the first end of the second capacitor C2 is connected to the second electrode of the tenth transistor T10, and the second end of the second capacitor C2 is connected to the gate of the tenth transistor T10.

[0079] The ninth transistor T9 is turned on or off according to the potential of its own control terminal, and transmits the second potential signal VGH to the output terminal OUT2 of the shift register when it is turned on. The tenth transistor T10 is turned on or off according to the potential of its own control terminal, and transmits the second clock signal CK2 to the output terminal OUT2 of the shift register when it is turned on. The first capacitor C1 is used to maintain the potential of the gate of the ninth transistor T9. The second capacitor C2 is used to maintain the potential of the gate of the tenth transistor T10. At the same time, the tenth transistor T10 and the second capacitor C2 form a bootstrap circuit, so that when the signal output from the output terminal OUT2 of the shift register jumps from a high level to a low level, the gate of the tenth transistor T10 can reach an ultra-low potential, thereby preventing the second clock signal CK2 output from the output terminal OUT2 of the shift register from being affected by the threshold voltage of the tenth transistor T10 and unable to be reduced to the target value. The eighth transistor T8 is provided between the control terminal N2 of the third output module 13 and the gate of the fourth transistor T4, which can suppress the ultra-low potential of the gate of the tenth transistor T10 brought about by the bootstrap effect of the second capacitor C2 from being transmitted to the gate of the fourth transistor T4, thereby reducing the probability of the gate insulation layer of the fourth transistor T4 being broken down and improving the stability of the shift register.

[0080] Figure 8 A driving timing diagram of another light emitting control circuit provided in an embodiment of the present invention is shown. Figure 8 The drive timing shown is applicable to Figure 7 The pixel circuit shown, Figure 7 In the pixel circuit shown, except for the second transistor T2 which is an N-type transistor, the remaining transistors are all P-type transistors. Figure 7 and Figure 8The operation process of the light emitting control circuit includes a first phase ta, a second phase tb, and a third phase tc. The second phase tb includes n state phases t2, and each state phase t2 includes a first sub-phase t21, a second sub-phase t22, a third sub-phase t23, and a fourth sub-phase t24. The first potential signal VGL is at a low level, and the second potential signal VGH is at a high level.

[0081] During the first phase ta, when the start signal SIN is high and the first clock signal CK1 is low, the first clock signal CK1 turns on the fifth transistor T5. The turned-on fifth transistor T5 transmits the start signal SIN to the gate of the tenth transistor T10, turning off the tenth transistor T10. The high gate level of the tenth transistor T10 turns off the fourth transistor T4. The first clock signal CK1 also turns on the third transistor T3. The turned-on third transistor T3 transmits the first potential signal VGL to the gate of the ninth transistor T9, turning on the ninth transistor T9. The gate of the ninth transistor T9 is low, turning on the seventh transistor T7. The second clock signal CK2 is high, turning off the sixth transistor T6. The turned-on ninth transistor T9 transmits the second potential signal VGH to the output terminal OUT2 of the shift register. The gate of the tenth transistor T10 is high, turning on the second transistor T2 and turning off the first transistor T1. The turned-on second transistor T2 transmits the first potential signal VGL to the output terminal OUT1 of the light-emitting control circuit. In the subsequent stage of the first phase ta, after the first clock signal CK1 jumps to a high level, the first clock signal CK1 controls the third transistor T3 and the fifth transistor T5 to be turned off. The ninth transistor T9 remains at a low level, and the tenth transistor T10 remains at a high level, thereby causing the output terminal OUT1 of the light emitting control circuit to continue to output a low level, and the output terminal OUT2 of the shift register to continue to output a high level.

[0082] In the first sub-phase t21, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal SIN is at a low level. The first clock signal CK1 controls the conduction of the fifth transistor T5 and the third transistor T3. The conductive fifth transistor T5 transmits the start signal SIN to the gate of the tenth transistor T10, and the conductive third transistor T3 transmits the first potential signal VGL to the gate of the ninth transistor T9. The gate of the tenth transistor T10 is at a low level, which controls the conduction of the fourth transistor T4. After the fourth transistor T4 is turned on, it transmits the first clock signal CK1 to the gate of the ninth transistor T9, and the gate of the ninth transistor T9 is at a low level. In response to the low level of the gate of the ninth transistor T9, the seventh transistor T7 is turned on. The second clock signal CK2 controls the turn-off of the sixth transistor T6. The second potential signal VGH cannot be transmitted to the gate of the tenth transistor T10 through the seventh transistor T7 and the sixth transistor T6, thereby preventing the low level of the gate of the tenth transistor T10 from being affected. The ninth transistor T9 is turned on in response to the low level at its own gate, transmitting the second potential signal VGH to the output terminal OUT2 of the shift register. The tenth transistor T10 is turned on in response to the low level at its own gate, transmitting the second clock signal CK2 to the output terminal OUT2 of the shift register. The output terminal OUT2 of the shift register outputs a high level in the first sub-phase t21. The second transistor T2 is turned off in response to the low level at the gate of the tenth transistor T10. The first transistor T1 is turned on in response to the low level at the gate of the tenth transistor T10. The turned-on first transistor T1 transmits the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit. The output terminal OUT1 of the light-emitting control circuit outputs a high level in the first sub-phase t21.

[0083] In the second sub-phase t22, the first clock signal CK1, the second clock signal CK2, and the start signal SIN are all at a high level. The first clock signal CK1 controls the fifth transistor T5 and the third transistor T3 to be turned off, and the second clock signal CK2 controls the sixth transistor T6 to be turned off. The second potential signal VGH cannot be transmitted to the gate of the tenth transistor T10 through the seventh transistor T7 and the sixth transistor T6. Therefore, the gate of the tenth transistor T10 maintains the low level of the first sub-phase t21. The gate of the tenth transistor T10 is at a low level, which controls the fourth transistor T4 to be turned on. The turned-on fourth transistor T4 transmits the first clock signal CK1 to the gate of the ninth transistor T9. The ninth transistor T9 is turned off in response to the high level of its own gate. The tenth transistor T10 is turned on in response to the low level of its own gate. The turned-on tenth transistor T10 transmits the second clock signal CK2 to the output terminal OUT2 of the shift register. The output terminal OUT2 of the shift register outputs a high level in the second sub-phase t22. In response to the low level at the gate of the tenth transistor T10, the second transistor T2 is turned off, and in response to the low level at the gate of the tenth transistor T10, the first transistor T1 is turned on. The turned-on first transistor T1 transmits the second potential signal VGH to the output terminal OUT1 of the light emitting control circuit. The output terminal OUT1 of the light emitting control circuit outputs a high level in the second sub-phase t22.

[0084] In the third sub-phase t23, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the start signal SIN is at a high level. The first clock signal CK1 turns off the fifth transistor T5 and the third transistor T3, while the second clock signal CK2 turns on the sixth transistor T6. The high level at the gate of the ninth transistor T9 turns off the seventh transistor T7. The second potential signal VGH cannot be transmitted to the gate of the tenth transistor T10 via the seventh and sixth transistors T7 and T6. Therefore, the gate of the tenth transistor T10 maintains the low level of the second sub-phase t22. In response to the low level at the gate of the tenth transistor T10, the fourth transistor T4 turns on. The turned-on fourth transistor T4 transmits the first clock signal CK1 to the gate of the ninth transistor T9. The ninth transistor T9 turns off in response to the high level at its own gate. The tenth transistor T10 turns on in response to the low level at its own gate. The turned-on tenth transistor T10 transmits the second clock signal CK2 to the output terminal OUT2 of the shift register. The output terminal OUT2 of the shift register outputs a low level in the third sub-phase t23. In the third sub-phase t23, the output terminal OUT2 of the shift register transitions from a high level to a low level. Due to the bootstrap effect of the second capacitor C2, the potential of the gate of the tenth transistor T10 is coupled to a lower potential than that in the second sub-phase t23. In response to the low level at the gate of the tenth transistor T10, the second transistor T2 is turned off. In response to the low level at the gate of the tenth transistor T10, the first transistor T1 is turned on. The turned-on first transistor T1 transmits the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit. The output terminal OUT1 of the light-emitting control circuit outputs a high level in the third sub-phase t23.

[0085] In the fourth sub-phase t24, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, and the start signal SIN is at a high level. The first clock signal CK1 controls the fifth transistor T5 and the third transistor T3 to turn off. The second clock signal CK2 controls the sixth transistor T6 to turn off. The second potential signal VGH cannot be transmitted to the gate of the tenth transistor T10 via the seventh transistor T7 and the sixth transistor T6. Therefore, the gate of the tenth transistor T10 maintains the low level of the third sub-phase t23. In response to the low level of the gate of the tenth transistor T10, the fourth transistor T4 turns on. The turned-on fourth transistor T4 transmits the first clock signal CK1 to the gate of the ninth transistor T9. The ninth transistor T9 turns off in response to the high level of its own gate. The tenth transistor T10 turns on in response to the low level of its own gate. The turned-on tenth transistor T10 transmits the second clock signal CK2 to the output terminal OUT2 of the shift register. The output terminal OUT2 of the shift register outputs a high level in the fourth sub-phase t24. In the fourth sub-stage t24, the potential of the output terminal OUT2 of the shift register jumps from a low level to a high level. Due to the coupling effect of the second capacitor C2, the potential of the gate of the tenth transistor T10 is raised to the same potential as that in the second sub-stage t22. Even though the potential of the gate of the tenth transistor T10 is raised, the potential of the gate of the tenth transistor T10 remains at a low level. In response to the low level of the gate of the tenth transistor T10, the second transistor T2 is turned off. In response to the low level of the gate of the tenth transistor T10, the first transistor T1 is turned on. The turned-on first transistor T1 transmits the second potential signal VGH to the output terminal OUT1 of the light-emitting control circuit. The output terminal OUT1 of the light-emitting control circuit outputs a high level in the fourth sub-stage t24.

[0086] In the second phase tb, each state phase t2 is continuously executed until the second phase tb ends. In the second phase tb, the start signal SIN includes three low levels, and within each low-level period, the signal output by the output terminal OUT1 of the light-emitting control circuit is a high level. By increasing the number of low levels in the start signal SIN, the duration of the high level of the light-emitting control signal output by the output terminal OUT1 of the light-emitting control circuit can be extended. In this embodiment, multiple pulses with the same pulse width as the original start signal SIN are added at the end of the pulse cycle of the original start signal SIN (i.e., the end of the first state phase t2), thereby increasing the number of pulses without changing the width of a single pulse of the start signal SIN.

[0087] In the third phase tc, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal SIN is at a high level. The first clock signal CK1 controls the conduction of the fifth transistor T5 and the third transistor T3. The conducted fifth transistor T5 transmits the start signal SIN to the gate of the tenth transistor T10. The conducted third transistor T3 transmits the first potential signal VGL to the gate of the ninth transistor T9. The second clock signal CK2 controls the turn-off of the sixth transistor T6. The second potential signal VGH cannot be transmitted to the gate of the tenth transistor T10 via the seventh transistor T7 and the sixth transistor T6. The gate potential of the tenth transistor T10 is the start signal SIN, i.e., a high level. The fourth transistor T4 is turned off in response to the high level of the tenth transistor T10. The ninth transistor T9 is turned on in response to the low level of its own gate. After being turned on, the ninth transistor T9 transmits the second potential signal VGH to the output terminal OUT2 of the shift register. The tenth transistor T10 is turned off in response to the high level on its gate, the first transistor T1 is turned off in response to the high level on its gate, and the second transistor T2 is turned on in response to the high level on its gate. The turned-on second transistor T2 transmits the first potential signal VGL to the output terminal OUT1 of the light-emission control circuit. At a subsequent moment in the third phase tc, after the first clock signal CK1 transitions to a high level and the second clock signal CK2 transitions to a low level, the potentials at the gates of the ninth transistor T9 and the tenth transistor T10 remain unchanged, so that the potentials at the output terminal OUT2 of the shift register and the output terminal OUT1 of the light-emission control circuit remain unchanged.

[0088] Figure 9 A schematic diagram of a working state transition of a light emitting control circuit provided by an embodiment of the present invention, with reference to Figure 7-Figure 9 Combined with the above operating process, it can be seen that during the first sub-stage t21, the second sub-stage t22, the third sub-stage t23, and the fourth sub-stage t24, the potential of the internal node connecting the shift register to the first output module, namely the control terminal N2 of the third output module, is at a low level, so that the output terminal OUT1 of the light-emitting control circuit continuously outputs a high level throughout the second sub-stage tb. During the third sub-stage t3, the first clock signal CK1 is at a low level, but after the start signal SIN is at a high level, the signal output by the output terminal OUT1 of the light-emitting control circuit jumps from a high level to a low level, and the second sub-stage tb ends. The first clock signal CK1 is the same as the start signal SIN during the second sub-stage tb. Therefore, within a displayed frame, the pulse width of the signal output by the output terminal OUT1 of the light-emitting control circuit is equal to the product of the number of pulses of the start signal SIN and the pulse period of the start signal, that is, equal to the product of the number of pulses of the start signal SIN and the pulse period T1 of the first clock signal CK1.

[0089] An embodiment of the present invention further provides a display panel, Figure 10A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, referring to Figure 10 The display panel includes multiple rows of pixel circuits 02 and the light-emitting control circuit 01 described in any one of the above items. The output terminal OUT1 of the light-emitting control circuit is connected to the pixel circuit 02 of the corresponding row, and is used to output a light-emitting control signal to the pixel circuit 02; the light-emitting control circuit 01 includes at least two continuously cascaded shift registers 1, and the output terminal OUT2 of the previous stage shift register 1 is connected to the start signal input terminal ASIN of the next stage shift register 1.

[0090] The internal node B1 of each shift register stage is connected to the first output module 11. Each shift register stage 1 includes a first clock signal input terminal L1, a second clock signal input terminal L2, a first potential signal input terminal D1, and a second potential signal input terminal D2. The first clock signal input terminal L1 is used to input the first clock signal CK1, the second clock signal input terminal L2 is used to input the second clock signal CK2, the first potential signal input terminal D1 is used to input the first potential signal VGL, and the second potential signal input terminal D2 is used to input the second potential signal VGH. This embodiment implements the step-by-step shifting of the signal output by the output terminal OUT2 of each shift register stage, so that the light-emitting control signal output by the output terminal OUT1 of the light-emitting control circuit is shifted step-by-step, thereby realizing the row-by-row lighting of the sub-pixels in the display panel.

[0091] The beneficial effects of the display panel are the same as those of the light emitting control circuit, and will not be described in detail in this embodiment.

[0092] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0093] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A light emitting control circuit, characterized in that: include: A shift register, wherein the shift register comprises a start signal input terminal for inputting a start signal; a first output module, the first output module being connected to an internal node of the shift register and receiving a first potential signal and a second potential signal, the potential of the internal node being controlled by the start signal, the first output module being configured to control the first potential signal or the second potential signal to be transmitted to an output end of the light-emitting control circuit according to the potential of the internal node; Wherein, within a displayed frame, the width of a single pulse of the signal outputted from the output terminal of the light emitting control circuit is associated with the number and period of pulses in the start signal; The shift register includes a second output module, a third output module and an output control module, and the control end of the first output module is connected to the control end of the third output module; The output control module is used to control the potential of the control end of the second output module and the control end of the third output module according to the start signal, the first clock signal, and the first potential signal; During the stage when the output terminal of the light emitting control circuit outputs the second potential signal, the start signal and the first clock signal have the same pulse width, the same pulse period, and the same pulse start time.

2. The light emitting control circuit according to claim 1, characterized in that: The first output module includes a first output unit and a second output unit; The control end of the first output unit is connected to the internal node, and the first output unit is used to be turned on or off according to the potential of its own control end, and to control the second potential signal to be transmitted to the output end of the light emitting control circuit when turned on; The control end of the second output unit is connected to the internal node. The second output unit is used to be turned on or off according to the potential of its own control end, and to control the first potential signal to be transmitted to the output end of the light emitting control circuit when turned on.

3. The light emitting control circuit according to claim 2, characterized in that: The first output unit includes a first transistor, a first electrode of the first transistor is connected to the second potential signal, a second electrode of the first transistor is connected to the output end of the light emitting control circuit, and a gate of the first transistor is connected to the internal node; The second output unit includes a second transistor, a first electrode of the second transistor is connected to the first potential signal, a second electrode of the second transistor is connected to the output end of the light emitting control circuit, and a gate of the second transistor is connected to the internal node.

4. The light emitting control circuit according to claim 1, wherein: The second output module is configured to be turned on or off according to the potential of its own control terminal, and to control the second potential signal to be transmitted to the output terminal of the shift register when turned on; The control end of the third output module serves as the internal node and is connected to the first output module. The third output module is used to turn on or off according to the potential of its own control end, and when turned on, controls the second clock signal to be transmitted to the output end of the shift register.

5. The light emitting control circuit according to claim 4, characterized in that: The output control module includes a first output control unit and a second output control unit, the first output control unit includes a first control end, a second control end, a first end, a second end, and a third end, the first control end of the first output control unit is connected to the first clock signal, the second control end of the first output control unit is connected to the control end of the third output module, the first end of the first output control unit is connected to the first potential signal, the second end of the first output control unit is connected to the first clock signal, and the third end of the first output control unit is connected to the control end of the second output module, the first output control unit is configured to control the first clock signal and the first potential signal to be transmitted to the control end of the second output module according to the first clock signal and the potential of the control end of the third output module; The second output control unit includes a first control end, a second control end, a third control end, a first end, a second end, and a third end. The first control end of the second output control unit is connected to the first clock signal, the second control end of the second output control unit is connected to the control end of the second output module, the third control end of the second output control unit is connected to the second clock signal, the first end of the second output control unit is connected to the start signal, the second end of the second output control unit is connected to the second potential signal, and the third end of the second output control unit is connected to the control end of the third output module. The second output control unit is used to control the transmission of the start signal and the second potential signal to the control end of the third output module according to the first clock signal, the potential of the control end of the second output module, and the second clock signal.

6. The light emitting control circuit according to claim 5, characterized in that: The first output control unit includes a third transistor and a fourth transistor, wherein a first electrode of the third transistor is connected to the first potential signal, a second electrode of the third transistor is connected to the control terminal of the second output module, a gate of the third transistor is connected to the first clock signal, a first electrode of the fourth transistor is connected to the first clock signal, a second electrode of the fourth transistor is connected to the control terminal of the second output module, and a gate of the fourth transistor is connected to the control terminal of the third output module; The second output control unit includes a fifth transistor, a sixth transistor and a seventh transistor, the first electrode of the fifth transistor is connected to the start signal, the second electrode of the fifth transistor is connected to the control end of the third output module, the gate of the fifth transistor is connected to the first clock signal, the first electrode of the sixth transistor is connected to the control end of the third output module, the second electrode of the sixth transistor is connected to the second electrode of the seventh transistor, the gate of the sixth transistor is connected to the second clock signal, the first electrode of the seventh transistor is connected to the second potential signal, and the gate of the seventh transistor is connected to the control end of the second output module.

7. The light emitting control circuit according to claim 6, characterized in that: The third output module also includes an eighth transistor, a first electrode of the eighth transistor is connected to the second electrode of the fifth transistor, a first electrode of the eighth transistor is connected to the first electrode of the sixth transistor, the first electrode of the eighth transistor is also connected to the gate of the fourth transistor, a second electrode of the eighth transistor is connected to the control end of the third output module, and the gate of the eighth transistor is connected to the first potential signal.

8. The light emitting control circuit according to claim 1, wherein: In one displayed frame, the pulse width of the signal outputted from the output terminal of the light emitting control circuit is equal to the product of the number of pulses of the start signal and the pulse period of the start signal.

9. The light emitting control circuit according to claim 4, characterized in that: The second output module includes a ninth transistor and a first capacitor, wherein a first electrode of the ninth transistor is connected to the second potential signal, a second electrode of the ninth transistor is connected to the output terminal of the shift register, a gate of the ninth transistor serves as a control terminal of the second output module, a first terminal of the first capacitor is connected to the first electrode of the ninth transistor, and a second terminal of the first capacitor is connected to the gate of the ninth transistor; The third output module includes a tenth transistor and a second capacitor, the first electrode of the tenth transistor is connected to the second clock signal, the second electrode of the tenth transistor is connected to the output end of the shift register, the gate of the tenth transistor serves as the control end of the third output module, the first end of the second capacitor is connected to the second electrode of the tenth transistor, and the second end of the second capacitor is connected to the gate of the tenth transistor.

10. A display panel, characterized in that: It comprises a plurality of rows of pixel circuits and a light-emitting control circuit as described in any one of claims 1 to 9, wherein the output end of the light-emitting control circuit is connected to the pixel circuit of the corresponding row for outputting a light-emitting control signal to the pixel circuit; the light-emitting control circuit comprises at least two shift registers that are cascaded continuously, and the output end of the shift register of the previous stage is connected to the start signal output end of the shift register of the next stage.

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