Display substrate, display panel, and display device

Abstract

The present disclosure provides a display substrate, a display panel, and a display device. The display substrate includes: a substrate including: a display area and a source drive area, the source drive area being located on one side of the display area and arranged along a first direction with the display area; a plurality of pixel unit groups located on one side of the substrate and within the display area, the plurality of pixel unit groups being arranged along the first direction, the pixel unit groups including a plurality of pixel units arranged along a second direction, the second direction intersecting the first direction; a pixel unit including a driving transistor, a charge storage circuit, and a reset circuit, the charge storage circuit and the reset circuit both being connected to the gate of the driving transistor; the reset circuit being configured to write a reset voltage to the gate of the driving transistor, the charge storage circuit being configured to store the gate voltage of the driving transistor; and, among the plurality of pixel unit groups, the charge storage circuits included in the pixel units in at least two pixel unit groups have different charge storage capacities.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] Active Matrix Organic Light Emitting Diode (AMOLED) panels are becoming increasingly popular. The pixel display device of AMOLED is an organic light-emitting diode (OLED). AMOLEDs emit light by driving thin-film transistors in a saturated state to generate a driving current, which drives the OLED to emit light. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate, a display panel, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0005] A substrate comprising: a display area and a source driving area, wherein the source driving area is located on one side of the display area and is arranged along a first direction with the display area;

[0006] a plurality of pixel unit groups located on one side of the substrate and in the display area, the plurality of pixel unit groups being arranged along the first direction, the pixel unit group including a plurality of pixel units arranged along a second direction, the second direction intersecting the first direction;

[0007] The pixel unit includes a driving transistor, a charge storage circuit and a reset circuit, and the charge storage circuit and the reset circuit are both connected to the gate of the driving transistor;

[0008] The reset circuit is configured to write a reset voltage to the gate of the driving transistor, and the charge storage circuit is configured to store the gate voltage of the driving transistor;

[0009] Among the plurality of pixel unit groups, the charge storage capacity of the charge storage circuits included in the pixel units in at least two of the pixel unit groups is different.

[0010] In some embodiments, the charge storage circuit includes a storage capacitor;

[0011] A first end of the storage capacitor is connected to the gate of the driving transistor, and a second end of the storage capacitor is connected to a preset node.

[0012] In some embodiments, in the plurality of pixel unit groups, along a direction away from the source driving region, the capacitances of the storage capacitors included in the pixel units in the pixel unit group increase sequentially.

[0013] In some embodiments, in the plurality of pixel unit groups, along a direction away from the source driving region, orthographic projections of the storage capacitors included in the pixel units in the pixel unit group on the substrate increase sequentially.

[0014] In some embodiments, the display substrate further comprises: a data writing circuit;

[0015] The data writing circuit is connected to the data line, the first control signal line and the gate of the driving transistor. The data writing circuit is configured to output the data voltage provided by the data line to the gate of the driving transistor in response to the control of the signal provided by the first control signal line.

[0016] In some embodiments, the data writing circuit includes a first transistor, a first electrode of the first transistor is connected to the data line, a second electrode of the first transistor is connected to the gate of the driving transistor, and the gate of the first transistor is connected to the first control signal line;

[0017] The data writing circuit and the reset circuit are the same circuit.

[0018] In some embodiments, the pixel unit further includes a threshold compensation circuit, wherein the threshold compensation circuit is connected to the first voltage signal line, the second control signal line, the gate of the driving transistor, and the first electrode of the driving transistor;

[0019] The threshold compensation circuit is configured to obtain the threshold voltage of the driving transistor in response to the control of the signal provided by the second control signal line, so as to perform threshold compensation on the driving transistor.

[0020] In some embodiments, the threshold compensation circuit includes a first capacitor and a second transistor,

[0021] A first electrode of the second transistor is connected to the first voltage signal line, a gate of the second transistor is connected to the second control signal line, and a second electrode of the second transistor is connected to the first electrode of the driving transistor;

[0022] A first end of the first capacitor is connected to the gate of the driving transistor, and a second end of the first capacitor is connected to the first electrode of the driving transistor.

[0023] In some embodiments, the charge storage circuit includes the first capacitor.

[0024] In some embodiments, the pixel unit further includes a second capacitor;

[0025] A first end of the second capacitor is connected to the first voltage signal line, and a second end of the second capacitor is connected to the first electrode of the driving transistor.

[0026] In some embodiments, the pixel unit further includes a light emitting control circuit and a light emitting element, wherein the light emitting control circuit includes a third transistor;

[0027] The first electrode of the third transistor is connected to the second electrode of the driving transistor, the gate of the third transistor is connected to the third control signal line, and the second electrode of the third transistor is connected to the second voltage signal line;

[0028] A first end of the light emitting element is connected to the second electrode of the driving transistor, and a second end of the light emitting element is connected to the second voltage signal line.

[0029] In a second aspect, an embodiment of the present disclosure provides a display panel comprising the display substrate described in the first aspect.

[0030] In a third aspect, an embodiment of the present disclosure provides a display device comprising the display panel described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0032] Figure 1 A schematic structural diagram of a pixel unit provided in an embodiment of the present disclosure.

[0033] Figure 2 for Figure 1 The working timing diagram of the pixel unit is shown.

[0034] Figure 3 This is a timing diagram of the first control signal line and the second control signal line corresponding to pixel units located at different positions on the display substrate.

[0035] Figure 4 A schematic diagram of a planar structure of storage capacitors included in a plurality of display units provided in an embodiment of the present disclosure.

[0036] Description of reference numerals:

[0037] Storage capacitor Cst;

[0038] Reset circuit 1, data writing circuit 1': first transistor T1;

[0039] Threshold compensation circuit 2: second transistor T2, first capacitor C1;

[0040] Light emitting control circuit 3: third transistor T3;

[0041] Driving transistor TD, second capacitor C2, light emitting element OLED;

[0042] A first control signal line WS, a second control signal line DS, and a third control signal line AZ;

[0043] A first voltage signal line VDD, a second voltage signal line VSS, and a data line DATA;

[0044] The first node N1 and the second node N2. DETAILED DESCRIPTION

[0045] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0046] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0048] It should be noted that the transistors in the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. A transistor generally includes three electrodes: a gate, a source, and a drain. The source and drain in the transistor are symmetrical in structure, wherein the electrode that sends carriers serves as the source electrode and the electrode that receives carriers serves as the drain electrode. In actual application, for a transistor, depending on the position and function of the transistor in the circuit and the channel type of the transistor, the source electrode can be used as the first electrode of the transistor, and accordingly, the drain electrode can be used as the second electrode of the transistor; or, the drain electrode can be used as the first electrode of the transistor, and accordingly, the source electrode can be used as the second electrode of the switch tube.

[0049] In addition, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors; when the transistor is an N-type transistor, its on-voltage is a high-level voltage and its off-voltage is a low-level voltage; when the transistor is a P-type transistor, its on-voltage is a low-level voltage and its off-voltage is a high-level voltage.

[0050] In the present disclosure, the case where all transistors in a pixel unit are simultaneously N-type transistors or simultaneously P-type transistors is merely a preferred embodiment of the present disclosure. In this case, all transistors in the pixel unit can be manufactured simultaneously using the same process, which helps shorten the manufacturing cycle. In the embodiments of the present disclosure, an example is provided in which all transistors in the pixel unit are P-type transistors.

[0051] Active Matrix Organic Light Emitting Diode (AMOLED) panels are becoming increasingly popular. The pixel display device of AMOLED is an organic light-emitting diode (OLED). AMOLED emits light by driving the thin-film transistor in a saturated state to generate a driving current, which drives the OLED to emit light.

[0052] However, in the existing display substrate, during the pixel driving process, after the driving transistors corresponding to pixels at different positions enter the self-discharge state, the gate voltages of the driving transistors are different at the initial moment of the self-discharge stage. Therefore, when the same data voltage is input to the driving transistors, the driving currents generated by the driving transistors are different, resulting in the problem of uneven brightness of the display substrate.

[0053] In order to solve at least one or more of the above-mentioned technical problems, an embodiment of the present disclosure provides a display substrate, which improves the problem of uneven brightness of the display substrate by setting a charge storage circuit corresponding to each pixel unit to maintain the stability of the gate voltage of the driving transistor corresponding to each pixel unit.

[0054] Figure 1 A schematic structural diagram of a pixel unit provided in an embodiment of the present disclosure is shown in FIG. Figure 2 for Figure 1 The working timing diagram of the pixel unit is shown.

[0055] The present disclosure provides a display substrate comprising a substrate and a plurality of pixel unit groups. The substrate comprises a display area and a source drive area, wherein the source drive area is located on one side of the display area and arranged along a first direction with the display area. The plurality of pixel unit groups are located on one side of the substrate and within the display area, wherein the plurality of pixel unit groups are arranged along the first direction, and the pixel unit groups include a plurality of pixel units arranged along a second direction, wherein the second direction intersects the first direction.

[0056] It should be understood that the first direction in the above-mentioned display substrate refers to the row direction, and the second direction refers to the column direction.

[0057] like Figure 1 As shown, the pixel unit includes a driving transistor TD and a reset circuit 1, wherein the reset circuit 1 is connected to the gate of the driving transistor TD; the reset circuit 1 is configured to write a reset voltage into the gate of the driving transistor TD.

[0058] In some embodiments, the display substrate further includes a data writing circuit 1', which is connected to the data line DATA, the first control signal line WS, and the gate of the driving transistor TD. The data writing circuit 1' is configured to output the data voltage provided by the data line DATA to the gate of the driving transistor TD in response to the control of the signal provided by the first control signal line WS.

[0059] In one example, if Figure 1 As shown, the data writing circuit 1' includes a first transistor T1, a first electrode of the first transistor T1 is connected to the data line DATA, a second electrode of the first transistor T1 is connected to the gate of the driving transistor TD, and a gate of the first transistor T1 is connected to the first control signal line WS.

[0060] In the disclosed embodiment, the data writing circuit 1' and the reset circuit 1 are the same circuit. Specifically, in the initialization phase, the first transistor T1 acts as the reset circuit 1 in the pixel unit; in the data writing phase, the first transistor T1 acts as the data writing circuit 1' in the pixel unit.

[0061] In some embodiments, the pixel unit also includes a threshold compensation circuit 2, which is connected to the first voltage signal line VDD, the second control signal line DS, the gate of the driving transistor TD, and the first electrode of the driving transistor TD. It is configured to obtain the threshold voltage of the driving transistor TD in response to the control of the signal provided by the second control signal line DS to perform threshold compensation on the driving transistor TD.

[0062] In one example, if Figure 1 As shown, the threshold compensation circuit 2 includes a first capacitor C1 and a second transistor T2. The first electrode of the second transistor T2 is connected to the first voltage signal line VDD, the gate of the second transistor T2 is connected to the second control signal line DS, and the second electrode of the second transistor T2 is connected to the first electrode of the driving transistor TD. The first end of the first capacitor C1 is connected to the gate of the driving transistor TD, and the second end of the first capacitor C1 is connected to the first electrode of the driving transistor TD.

[0063] It should be understood that the first voltage signal line is a VDD line configured to provide a high-level voltage signal.

[0064] In some embodiments, the pixel unit further includes a light emitting control circuit 3 and a light emitting element OLED, wherein the light emitting control circuit 3 includes a third transistor T3, a first electrode of the third transistor T3 is connected to the second electrode of the driving transistor TD, a gate of the third transistor T3 is connected to a third control signal line AZ, and a second electrode of the third transistor T3 is connected to a second voltage signal line VSS. A first terminal of the light emitting element OLED is connected to the second electrode of the driving transistor TD, and a second terminal of the light emitting element OLED is connected to the second voltage signal line VSS.

[0065] It should be understood that the second voltage signal line VSS is a Vss line configured to provide a reference voltage Vss. Optionally, the reference voltage Vss may be a low-level voltage signal. In this embodiment, the first terminal of the light-emitting element OLED may be an anode, and the second terminal may be a cathode.

[0066] In this embodiment, the working process of the pixel unit may include four stages, such as Figure 1 、 Figure 2 As shown:

[0067] Initialization phase t1: The first control signal line WS provides a low-level signal, and the data line DATA provides a reset voltage Vofs. The first control signal line WS turns on the reset circuit 1, namely the first transistor T1, and writes the reset voltage Vofs to the gate of the drive transistor TD, namely the first node N1. Simultaneously, the second control signal line DS provides a low-level signal, turning on the threshold compensation circuit 2, namely the second transistor T2, and writing the power supply voltage Vdd provided by the first voltage signal line VDD to the first electrode of the drive transistor TD, namely the second node N2. Because the gate-source voltage Vgs (Vofs-Vdd) of the drive transistor TD is less than the threshold voltage Vth of the drive transistor TD, the drive transistor TD is now in the on state.

[0068] At the end of the initialization phase t1 , the voltage at the first node N1 is Vofs, and the voltage at the second node N2 is Vdd.

[0069] Holding stage t1 ′: the first control signal line WS provides a low-level signal, the first transistor T1 is turned off, the first node N1 is floating to maintain the reset voltage, and the second control signal line DS provides a low-level signal, the second transistor T2 is turned on.

[0070] However, in the holding phase, since the first node N1 is floating, the first node will leak through the electrical devices connected to it (for example, the first transistor T1, the driving transistor TD, the first capacitor C1, etc.), and the reset voltage at the first node N1 will decay.

[0071] At the end of the holding phase t1', the voltage at the first node N1 is Vofs_i, and the voltage at the second node N2 is Vdd. The longer the holding phase t1' is, the more severe the attenuation of the reset voltage at the first node N1 is, that is, the smaller the voltage Vofs_i at the first node N1 is at the end of the holding phase t1'.

[0072] Self-discharge stage t2: the first control signal line WS provides a high-level signal, the first transistor T1 is turned off, and the first node N1 remains floating; the second control signal line DS provides a high-level signal, the second transistor T2 is turned off; the third control signal line AZ provides a low-level signal, and the third transistor T3 is turned on.

[0073] When entering the self-discharge stage t2, since the driving transistor TD is in the on state, the second node N2 can be discharged through the second voltage signal line VSS based on the path formed by the driving transistor TD and the third transistor T3, so that the voltage at the second node N2 drops. At the same time, due to the bootstrap effect of the second capacitor C2, the voltage at the first node also drops, but the gate-source voltage Vgs of the driving transistor (the difference between the voltage at the first node N1 and the voltage at the second node N2, which is also the voltage difference between the two ends of the first capacitor C1) shows an overall increasing trend. When the gate-source voltage Vgs of the driving transistor is equal to the threshold voltage Vth of the driving transistor, the driving transistor is in the cut-off state.

[0074] At the end of the self-discharge phase t2 , the voltage at the first node N1 is VN1_t2 , and the voltage at the second node N2 is VN2_t2 . At this time, the gate-source voltage Vgs of the driving transistor TD is VN1_t2 − VN2_t2 = Vth.

[0075] It should be noted that the lower the voltage Vofs_i at the first node N1 at the start of the self-discharge phase t2, the lower the voltage VN1_t2 at the first node N1 at the end of the self-discharge phase t2. Furthermore, because the longer the holding phase t1' lasts, the lower the voltage Vofs_i at the first node N1 at the start of the self-discharge phase t2. Therefore, it can be inferred that the longer the holding phase t1' lasts, the lower the voltage VN1_t2 at the first node N1 at the end of the self-discharge phase t2.

[0076] Data writing stage t3: the first control signal line WS provides a low level signal to control the data writing circuit 1 ′, ie, the first transistor T1 to be turned on. At this time, the second control signal line DS first provides a high level signal and then provides a low level signal.

[0077] Among them, when the second control signal line DS provides a high-level signal, the second node N2 is still in a floating state; at the same time, the data voltage Vdata is written into the gate of the driving transistor TD, that is, the first node N1, through the first transistor T1. At this time, the voltage at the first node N1 changes from VN1_t2 to VN1_t3, where VN1_t3 = Vdata.

[0078] At this time, due to the bootstrap effect of the first capacitor C1 and the capacitive voltage divider effect of the first capacitor C1 and the second capacitor C2, the voltage at the second node N2 becomes VN2_t3, where VN2_t3 = VN2_t2 + [C1 / (C1+C2)] * (Vdata - VN1_t2). Since VN2_t2 = VN1_t2 - Vth, VN2_t3 = VN1_t2 - Vth + [C1 / (C1+C2)] * (Vdata - VN1_t2). At this time, the gate-source voltage of the driving transistor Vgs=VN1_t3-VN2_t3=Vdata-{VN1_t2-Vth+[C1 / (C1+C2)]*(Vdata-VN1_t2)}=[C2 / (C1+C2)]*VN1_t2+[C2 / (C1+C2)]*Vdata+Vth.

[0079] When the second control signal line DS provides a low-level signal, the second transistor is turned on, and the Vdd voltage is written to the second node N2 through the second transistor T2. The voltage VN2_t3' at the second node N2 is Vdd. At the same time, the voltage at the first node N1 is also pulled up to VN1_t3' due to the bootstrap effect of the first capacitor C1. At this time, due to the effect of the first capacitor C1, the gate-source voltage Vgs of the driving transistor TD maintains the previous state, that is, VN1_t3'-VN2_t3'=[C2 / (C1+C2)]*VN1_t2+[C2 / (C1+C2)]*Vdata+Vth.

[0080] Light-emitting phase t4: The second control signal line DS provides a low-level signal, turning on the second transistor T2. Simultaneously, the third control signal line AZ provides a high-level signal, turning off the light-emitting control circuit 3, specifically the third transistor T3. At this point, the data line DATA provides the data voltage Vdata, causing the light-emitting element OLED to emit light.

[0081] At this time, the gate-source voltage Vgs of the driving transistor maintains the state of the previous stage, that is, Vgs=[C2 / (C1+C2)]*VN1_t2+[C2 / (C1+C2)]*Vdata+Vth.

[0082] At this time, Vgs-Vth=[C2 / (C1+C2)]*VN1_t2+[C2 / (C1+C2)]*Vdata. 2 The value of determines the driving current output by the driving transistor TD; (Vgs-Vth) 2 The larger the value of , the larger the driving current value output by the driving transistor TD, and the brighter the light emitting brightness of the light emitting element OLED.

[0083] It can be seen that the luminance of the light-emitting element OLED is not only related to the data voltage Vdata, but also to the voltage VN1_t2 at the first node N1 at the end of the self-discharge phase t2. When Vdata is constant, the larger VN1_t2 is, the greater (Vgs-Vth) 2 The larger the value of , the brighter the OLED's light emission. Furthermore, because the voltage VN1_t2 at the first node N1 at the end of the self-discharge phase t2 is positively correlated with the voltage Vofs_i at the first node N1 at the end of the holding phase t1', when Vdata is constant, the larger the voltage Vofs_i at the first node N1 at the end of the holding phase t1', the brighter the OLED's light emission.

[0084] Figure 3 1 is a timing diagram of the first control signal line and the second control signal line DS corresponding to the pixel units at different positions on the display substrate. Figure 3 As shown, for the convenience of description, the pixel unit group closest to the source driving area in the display area is called the first row of pixel units, and the pixel unit group farthest from the source driving area in the display area is called the last row of pixel units; the first control signal line WS and the second control signal line DS configured for the first row of pixel units are respectively called the first row WS and the first row DS, and the first control signal line WS and the second control signal line DS configured for the last row of pixel units are respectively called the last row WS and the last row DS.

[0085] Combined with the above Figure 2From the timing analysis shown, it can be seen that there are two pulse signals on each first control signal line WS. The first pulse signal is used to write the reset voltage Vofs provided by the data line DATA into the gate of the driving transistor TD during the initialization phase, and the second pulse signal is used to write the data voltage Vdata provided by the data line DATA into the gate of the driving transistor TD during the data writing phase.

[0086] like Figure 2 、 3 As shown, first, for any pixel unit, the rising edge moment when the first control signal line WS configured by the pixel unit changes from a low level signal to a high level signal, that is, the end moment of the first pulse signal, precedes the rising edge moment when the second control signal line DS configured by the pixel unit changes from a low level signal to a high level signal. The period between the above two moments is Figure 2 However, for pixel units located in different rows on the display substrate, the end time of the first pulse signal of the first control signal line WS is the same, but the rising edge time of the second control signal line DS changing from a low-level signal to a high-level signal is delayed according to the order of pixel scanning. The later the pixel unit is in the scanning order, the later the rising edge time of the second control signal line DS changing from a low-level signal to a high-level signal is.

[0087] In one example, the display substrate starts scanning from the first row of pixel units and scans downwards in sequence until the last row of pixels is scanned to complete the refresh of a frame of image. Figure 3 As shown, the holding phase t1' corresponding to the first row of pixel units on the display panel has a duration of Q1; the holding phase t1' corresponding to a middle row of pixel units on the display panel has a duration of Q2; and the holding phase t1' corresponding to the last row of pixel units on the display panel has a duration of Q3.

[0088] During the period when the first transistor T1 is off and the second transistor T2 is on (i.e., the reset voltage hold time), the first node N1 is in a floating state. During this period, leakage current may occur at the first node N1 through the electrical components connected thereto, resulting in a reset voltage attenuation phenomenon at the first node N1. The longer the signal hold time, the more severe the signal attenuation at the first node N1. Specifically, the attenuation of the reset voltage applied to the first node in the first row of pixel units is less than the attenuation of the reset voltage applied to the first node in a middle row of pixel units, and the attenuation of the reset voltage applied to the first node in a middle row of pixel units is less than the attenuation of the reset voltage applied to the first node in the last row of pixel units.

[0089] For the convenience of description, the actual voltage at the first node N1 when the first row of pixel units enters the self-discharge stage t2 is recorded as Vofs_1, the actual voltage at the first node N1 when a middle row of pixel units enters the self-discharge stage t2 is recorded as Vofs_2, and the actual voltage at the first node N1 when the last row of pixel units enters the self-discharge stage t2 is recorded as Vofs_3. Since Q1<Q2<Q3, Vofs_1>Vofs_2>Vofs_3.

[0090] It should be noted that when the first control signal line WS is set to a high level and the first transistor T1 is turned off, the pixel unit enters a self-discharge state, and when the second control signal line DS is set to a low level signal for the second time, the self-discharge ends. Figure 2 、 Figure 3 It can be seen that the self-discharge time of all rows of pixel units is the same, which is Figure 3 The TT period shown in .

[0091] Based on the foregoing description, it can be seen that, given a constant Vdata, the greater the voltage Vofs_i at the first node N1 at the end of the holding phase t1' (i.e., the voltage at the first node N1 when entering the self-discharge phase t2), the brighter the OLED's brightness. Therefore, under the same data voltage, since Vofs_1>Vofs_2>Vofs_3, the brightness of the OLED light-emitting elements in the first row of pixel units is higher than the brightness of the OLED light-emitting elements in the middle row of pixel units, and the brightness of the OLED light-emitting elements in the middle row of pixel units is higher than the brightness of the OLED light-emitting elements in the last row of pixel units.

[0092] From the above analysis, it can be seen that the durations of the holding phases corresponding to pixel units in different rows are different, which may affect the display uniformity of the display substrate.

[0093] Based on this, in the disclosed embodiment, the pixel unit further includes a charge storage circuit connected to the gate of the drive transistor TD and configured to store the gate voltage of the drive transistor TD. Among the multiple pixel unit groups, the pixel units in at least two pixel unit groups may include charge storage circuits having different charge storage capacities.

[0094] In the display substrate provided by the embodiments of the present disclosure, a plurality of pixel cell groups are arranged along the row direction, and each pixel cell group includes a plurality of pixel cells arranged along the column direction, wherein the charge storage capacity of the charge storage circuits included in the pixel cells in at least two pixel cell groups is different. In other words, the charge storage capacity of the charge storage circuits included in the pixel cells located in different rows of the display substrate is different, thereby having different voltage stabilization effects and different abilities to maintain the voltage of the gate of the driving transistor TD. Furthermore, the voltage of the gate of the driving transistor TD is a reset voltage, thereby achieving complementarity with the different reset voltage retention times of the pixel cells in different rows of the display substrate, so that the pixel cells in different rows of the display substrate have the same degree of reset voltage attenuation under different reset voltage retention times, and ultimately have the same or approximately the same reset voltage at the first node N1 when entering the self-discharge stage.

[0095] In some embodiments, the charge storage circuit includes a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor TD, and a second end of the storage capacitor Cst is connected to a predetermined node. In one example, the predetermined node may be a second voltage signal line VSS.

[0096] In another example, Figure 1 As shown, the preset node may be located between the first electrode of the driving transistor TD and the second electrode of the second transistor T2. In this case, the storage capacitor Cst may be the first capacitor C1.

[0097] In some embodiments, in a plurality of pixel unit groups, the capacitance of the storage capacitor Cst included in the pixel units in the pixel unit group increases sequentially along a direction away from the source driving region.

[0098] It should be understood that, on the one hand, the distance from the source drive area will affect the driving order of the pixel units on the display substrate. The farther the pixel unit is from the source drive area, the later the driving order. From the above analysis, it can be seen that the holding time of the reset voltage gradually increases in the direction away from the source drive area, and the longer the holding time, the greater the voltage attenuation. On the other hand, the larger the capacitance, the smaller the leakage of the charge storage circuit, and the stronger the potential holding ability; the smaller the capacitance, the larger the leakage of the charge storage circuit, and the weaker the potential holding ability. Therefore, along the direction away from the source driving area, the capacitance of the storage capacitor Cst included in the pixel unit in the pixel unit group increases successively, that is, the pixel unit close to the source driving area is driven first, and the holding time of the reset voltage is shorter, that is, the leakage time is short, but the capacitance of the storage capacitor Cst is smaller, and the leakage amount per unit time is large; while the pixel unit away from the source driving area is driven later, the holding time of the reset voltage is longer, that is, the leakage time is long, but the capacitance of the storage capacitor Cst is larger, and the leakage amount per unit time is small. The two complement each other, and ultimately achieve the same degree of reset voltage attenuation for pixel units in different rows in the display substrate under different reset voltage holding times.

[0099] It should also be noted that the premise for achieving consistent reset voltage attenuation of pixel units at different positions on the display substrate in the embodiment of the present disclosure is that the capacitance of the storage capacitor Cst included in the pixel unit driven first is smaller, and the capacitance of the storage capacitor Cst included in the pixel unit driven later is larger. In other words, the capacitance of the storage capacitor Cst included in the pixel unit is directly related to the driving order of the pixel units on the display substrate.

[0100] In one example, the driving order of the display substrate is to scan from the middle row of pixel units to both sides at the same time. Then, in at least two pixel unit groups among the corresponding multiple pixel unit groups, the storage capacitor Cst included in the pixel unit located in the middle position has the smallest capacitance, and the capacitance gradually increases in the direction toward both sides.

[0101] Figure 4 A schematic diagram of a planar structure of a storage capacitor included in a plurality of display units provided in an embodiment of the present disclosure. In some embodiments, as Figure 4 As shown, in a plurality of pixel unit groups, along a direction away from the source driving region, the orthographic projections of the storage capacitors Cst included in the pixel units in the pixel unit group on the substrate increase sequentially.

[0102] It should be understood that the orthographic projection of the storage capacitor Cst on the substrate refers to the orthographic projection of the effective area of ​​the storage capacitor Cst on the substrate, and the storage capacitor Cst includes a first electrode plate and a second electrode plate arranged opposite to each other, wherein the above-mentioned effective area refers to the area where the first electrode plate and the second electrode plate are facing and overlapping and can form an electric field.

[0103] In the embodiment of the present disclosure, the capacitance of the storage capacitor Cst is adjusted by adjusting the area of ​​the storage capacitor Cst, thereby achieving complementarity with the different reset voltage holding times of pixel units in different rows of the display substrate, so that the attenuation degree of the reset voltage is consistent under different reset voltage holding times of pixel units in different rows of the display substrate.

[0104] In some embodiments, as Figure 1 As shown, the pixel unit further includes a second capacitor C2, a first end of which is connected to the first voltage signal line VDD, and a second end of which is connected to the first electrode of the drive transistor TD. The second capacitor C2 is configured to be connected in series with the first capacitor C1 during the data writing phase to divide the voltage and improve the load capacity of the pixel unit.

[0105] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel including the above-mentioned display substrate.

[0106] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel.

[0107] The display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the present disclosure does not limit this.

[0108] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate comprising: a display area and a source driving area, wherein the source driving area is located on one side of the display area and is arranged along a first direction with the display area; a plurality of pixel unit groups located on one side of the substrate and in the display area, the plurality of pixel unit groups being arranged along the first direction, the pixel unit group including a plurality of pixel units arranged along a second direction, the second direction intersecting the first direction; The pixel unit includes a driving transistor, a charge storage circuit and a reset circuit, wherein the charge storage circuit and the reset circuit are both connected to the gate of the driving transistor; the voltage of the gate of the driving transistor is a reset voltage; and the gate of the driving transistor is a first node; The reset circuit is configured to write a reset voltage to the gate of the driving transistor, and the charge storage circuit is configured to store the gate voltage of the driving transistor; Among the plurality of pixel unit groups, the charge storage capacity of the charge storage circuits included in the pixel units in at least two of the pixel unit groups is different; The charge storage circuit includes a storage capacitor; the first end of the storage capacitor is connected to the gate of the driving transistor, and the second end of the storage capacitor is connected to a preset node; in the multiple pixel unit groups, the duration of the holding phase of the reset voltage corresponding to the pixel unit increases successively in the direction away from the source driving area, and the capacitance of the storage capacitor included in the pixel unit in the pixel unit group increases successively, and when the pixel units in the pixel unit group enter the self-discharge phase, the reset voltage of the first node is the same.

2. The display substrate according to claim 1, wherein: In the plurality of pixel unit groups, along a direction away from the source driving region, orthographic projections of the storage capacitors included in the pixel units in the pixel unit group on the substrate increase sequentially.

3. The display substrate according to claim 1, wherein The display substrate further includes: a data writing circuit; The data writing circuit is connected to the data line, the first control signal line and the gate of the driving transistor. The data writing circuit is configured to output the data voltage provided by the data line to the gate of the driving transistor in response to the control of the signal provided by the first control signal line.

4. The display substrate according to claim 3, wherein: The data writing circuit includes a first transistor, a first electrode of the first transistor is connected to the data line, a second electrode of the first transistor is connected to the gate of the driving transistor, and the gate of the first transistor is connected to the first control signal line; The data writing circuit and the reset circuit are the same circuit.

5. The display substrate according to claim 1, wherein The pixel unit further includes a threshold compensation circuit, wherein the threshold compensation circuit is connected to the first voltage signal line, the second control signal line, the gate of the driving transistor, and the first electrode of the driving transistor; The threshold compensation circuit is configured to obtain the threshold voltage of the driving transistor in response to the control of the signal provided by the second control signal line, so as to perform threshold compensation on the driving transistor.

6. The display substrate according to claim 5, wherein: The threshold compensation circuit includes a first capacitor and a second transistor, A first electrode of the second transistor is connected to the first voltage signal line, a gate of the second transistor is connected to the second control signal line, and a second electrode of the second transistor is connected to the first electrode of the driving transistor; A first end of the first capacitor is connected to the gate of the driving transistor, and a second end of the first capacitor is connected to the first electrode of the driving transistor.

7. The display substrate according to claim 6, wherein: The charge storage circuit includes the first capacitor.

8. The display substrate according to claim 5, wherein: The pixel unit further includes a second capacitor; A first end of the second capacitor is connected to the first voltage signal line, and a second end of the second capacitor is connected to the first electrode of the driving transistor.

9. The display substrate according to any one of claims 1 to 8, wherein: The pixel unit further includes a light emitting control circuit and a light emitting element, wherein the light emitting control circuit includes a third transistor; The first electrode of the third transistor is connected to the second electrode of the driving transistor, the gate of the third transistor is connected to the third control signal line, and the second electrode of the third transistor is connected to the second voltage signal line; A first end of the light emitting element is connected to the second electrode of the driving transistor, and a second end of the light emitting element is connected to the second voltage signal line.

10. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 9.

11. A display device, characterized in that: The display panel comprises the display panel according to claim 10.

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