Storage devices, memory devices, and methods of operating memory devices

Abstract

This application relates to a storage device, a memory device, and a method of operating the memory device. A memory device includes a plurality of memory cells, peripheral circuitry, and control logic. The peripheral circuitry performs a first read operation on a selected memory cell using a plurality of read voltages. In the first read operation, the control logic controls the peripheral circuitry to perform a cell counting operation, adjusting the remaining read voltage among the plurality of read voltages based on a read offset table and a cell count as a result of the cell counting operation, and performing the first read operation on the selected memory cell using the remaining read voltage. The control logic executes, in parallel among a plurality of consecutively executed read operations, a read data output operation of a second read operation performed prior to the first read operation and a cell counting operation corresponding to the first read operation.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more particularly to storage devices suitable for performing read operations and methods for operating storage devices. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores the data and a memory controller that controls the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are devices that store data only while powered on and lose the stored data when power is cut off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0004] Non-volatile memory devices are devices that retain data even when power is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0005] According to embodiments of this disclosure, a memory device may include a plurality of memory cells, peripheral circuitry, and control logic. The peripheral circuitry may perform a first read operation on a selected memory cell among the plurality of memory cells using a plurality of read voltages. In the first read operation, the control logic may control the peripheral circuitry to perform a cell counting operation that senses the selected memory cell using the first read voltage among the plurality of read voltages, adjusts the remaining read voltages among the plurality of read voltages based on a read offset table and the cell count as a result of the cell counting operation, and performs the first read operation on the selected memory cell using the remaining read voltages. The control logic may also execute, in parallel among a plurality of consecutively executed read operations, a read data output operation of a second read operation performed prior to the first read operation and a cell counting operation corresponding to the first read operation.

[0006] According to embodiments of this disclosure, a method for operating a memory device including a plurality of memory cells may include: performing a first read operation on selected memory cells among the plurality of memory cells using a plurality of read voltages in response to a first read command; and outputting read data of a second read operation on the plurality of memory cells in response to a second read command received prior to the first read command. Performing the first read operation may include: performing a cell counting operation to sense the selected memory cells using a first read voltage among the plurality of read voltages; adjusting the remaining read voltages among the plurality of read voltages based on a read offset table and a cell count as a result of the cell counting operation; and performing the first read operation on the selected memory cells using the remaining read voltages. The cell counting operation may be performed in parallel with the output of read data for the second read operation.

[0007] According to embodiments of this disclosure, a storage device may include a memory device and a memory controller. The memory device may include a plurality of memory cells. The memory controller may provide the memory device with a first read command and a second read command for instructing cache read operations on the plurality of memory cells. In response to the second read command, the memory device may perform read operations on the plurality of memory cells using a plurality of read voltages, wherein the read operations include performing a cell counting operation by sensing the plurality of memory cells with a first read voltage among the plurality of read voltages, adjusting the remaining read voltage among the plurality of read voltages based on a read offset table and a cell count as a result of the cell counting operation, performing read operations on the plurality of memory cells with the remaining read voltages, and performing an output operation and a cell counting operation in parallel based on read data of the first read command received prior to the second read command. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0009] Figure 2 This is an example Figure 1 A diagram of the structure of a memory device.

[0010] Figure 3 This is an example Figure 2 A diagram of a memory cell array.

[0011] Figure 4 This is a diagram illustrating the read operation of using logical page data and multiple read voltages according to an implementation method.

[0012] Figure 5 This is a diagram illustrating an implementation in which the remaining read voltages are adjusted based on the result of a cell counting operation using a first read voltage among multiple read voltages.

[0013] Figure 6 This is an example Figure 2 The graph shows the reading of the offset table.

[0014] Figure 7 This is a diagram illustrating adaptive reading of the use unit count (ARC) according to an implementation method.

[0015] Figure 8 This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0016] Figure 9 This is an example Figure 8 The diagram shows the normal read operation and ARC in the read / write circuit structure.

[0017] Figure 10 This is an example Figure 8 A diagram showing the latency of cache read operations in the read / write circuit structure.

[0018] Figure 11 This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0019] Figure 12A This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0020] Figure 12B This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0021] Figure 13 This is an example reference. Figure 12A and Figure 12B The diagram illustrates an implementation where the overhead of ARC is reduced.

[0022] Figure 14 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative to describe embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed may be implemented in various forms and should not be construed as limited to those described in this specification or application.

[0024] Embodiments of this disclosure provide a storage device for performing read operations with improved cache read performance, and a method for operating the storage device.

[0025] According to the present technology, in one embodiment, a storage device for performing read operations with improved cache read performance and a method for operating the storage device are provided.

[0026] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 The storage device 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device. The storage device 50 is a device for storing data under the control of a host such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0028] Depending on the host interface, which serves as the method of communication with the host, the storage device 50 can be manufactured as one of various types of storage devices. For example, the storage device 50 can be configured as any of various types of storage devices such as SSDs, multimedia cards in the form of MMC, eMMC, RS-MMC, and micro-MMC, secure digital cards in the form of SD, mini-SD, and micro-SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card storage devices, peripheral component interconnect (PCI) card storage devices, high-speed PCI (PCI-E) card storage devices, compact flash memory (CF) cards, smart media cards, and memory sticks.

[0029] Storage device 50 can be manufactured as any of various types of packages. For example, storage device 50 can be manufactured as any of various package types such as point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0030] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data.

[0031] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0032] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0033] A memory block can be a unit used to erase data. In embodiments, memory device 100 can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that memory device 100 is NAND flash memory.

[0034] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access address-selected regions in a memory cell array. That is, memory device 100 can perform operations instructed by commands on address-selected regions. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the address-selected region. During a read operation, memory device 100 can read data from the address-selected region. During an erase operation, memory device 100 can erase data stored in the address-selected region.

[0035] In one implementation, the memory device 100 may include a plurality of memory cells. The memory device 100 may receive a first read command and a second read command from the memory controller 200, indicating a cache read operation on the plurality of memory cells. The cache read operation may be performed by overlapping a read data output operation used for a previous read command and a read operation used for the current read command.

[0036] The memory device 100 can perform read operations on a plurality of memory cells in response to a first read command.

[0037] The memory device 100 can perform a read operation on a plurality of memory cells in response to a second read command. The memory device 100 can use a plurality of read voltages to perform the read operation according to the second read command. The memory device 100 can perform a cell counting operation by sensing a plurality of memory cells using a first read voltage among the plurality of read voltages.

[0038] Memory device 100 can adjust the remaining read voltage among a plurality of read voltages based on a read offset table and a cell count as a result of a cell counting operation. The read offset table may include at least one of an evaluation time offset, a read voltage offset, and a bit line precharge voltage offset corresponding to each of the plurality of read voltages. Memory device 100 can adjust at least one of the read voltage level, bit line precharge level, and evaluation time of the remaining read voltage based on the cell count and the read offset table. Memory device 100 can perform read operations on a plurality of memory cells using the remaining read voltage.

[0039] The memory device 100 can perform in parallel an output operation of read data based on a first read command received prior to a second read command and a cell counting operation corresponding to the second read command.

[0040] The memory controller 200 controls the overall operation of the storage device 50.

[0041] When power is applied to storage device 50, memory controller 200 can execute firmware. When storage device 100 is a flash memory device, memory controller 200 can operate firmware such as flash translation layer (FTL) to control communication between the host and storage device 100.

[0042] In one implementation, the memory controller 200 can receive data and logical block addresses (LBAs) from the host and convert the logical block addresses (LBAs) into physical block addresses (PBAs), the physical block addresses (PBAs) indicating the address of the memory cell where the data included in the memory device 100 is to be stored.

[0043] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to a request from the host. During a programming operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erasing operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0044] In one implementation, the memory controller 200 can generate and send commands, addresses, and data to the memory device 100 independently of requests from the host. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0045] In one implementation, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method can be an operational method used to overlap the operating periods of at least two memory devices 100.

[0046] The host can communicate with the storage device 50 using at least one of a variety of communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-off DIMM (LRDIMM).

[0047] Figure 2 This is an example Figure 1 A diagram of the structure of a memory device.

[0048] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented in hardware, software, or a combination of both. For example, the control logic 130 may be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0049] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 123 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells are defined as a physical page. That is, the memory cell array 110 is composed of multiple physical pages. According to an embodiment of this disclosure, each of the multiple memory blocks BLK1 to BLKz included in the memory cell array 110 may include multiple dummy cells. At least one of the dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0050] Each memory cell of the memory device 100 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0051] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0052] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can control the voltage applied to memory cell array 110 to perform programming, reading, and erasing operations.

[0053] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and virtual word lines. According to embodiments of this disclosure, row lines RL may also include pipe select lines.

[0054] Address decoder 121 is configured to operate in response to control by control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0055] Address decoder 121 is configured to decode the block address in the received address ADDR. Address decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 is also configured to decode the row address in the received address ADDR. Address decoder 121 can select at least one word line from the word lines of the selected memory block based on the decoded address. Address decoder 121 can apply the operating voltage Vop received from voltage generator 122 to the selected word line.

[0056] During programming operations, address decoder 121 can apply a programming voltage to the selected word line and a pass voltage with a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0057] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage with a level greater than the read voltage to the unselected word line.

[0058] According to embodiments of this disclosure, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the address ADDR input to the memory device 100 includes a block address. The address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line input to the selected memory block.

[0059] According to embodiments of this disclosure, address decoder 121 can be configured to decode the column address in the transmitted address ADDR. The decoded column address can be transmitted to read / write circuitry 123. As an example, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0060] Voltage generator 122 is configured to generate multiple operating voltages Vop by using an external power supply voltage provided to memory device 100. Voltage generator 122 operates in response to control of control logic 130.

[0061] As an implementation, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0062] As an implementation, voltage generator 122 can generate multiple operating voltages Vop using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0063] In order to generate multiple operating voltages Vop with various voltage levels, voltage generator 122 may include multiple pumping capacitors that receive internal voltages and selectively activate multiple pumping capacitors in response to control logic 130 to generate multiple operating voltages Vop.

[0064] Multiple generated operating voltages Vop can be provided to the memory cell array 110 by the address decoder 121.

[0065] Read / write circuit 123 includes first page buffers PB1 to m-th page buffers PBm. First page buffers PB1 to m-th page buffers PBm are connected to memory cell array 110 via first bit line BL1 to m-th bit line BLm, respectively. First page buffers PB1 to m-th page buffers PBm operate in response to control logic 130.

[0066] The first page buffer PB1 to the m-th page buffer PBm communicate with the data input / output circuit 124 to receive the data DATA to be stored through the data input / output circuit 124 and the data line DL during programming.

[0067] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA to be stored to the selected memory cell via bit lines BL1 to BLm, i.e., the data DATA received through the data input / output circuit 124. The memory cell of the selected page is programmed according to the transmitted data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0068] During a read operation, the read / write circuit 123 can read data DATA from the memory cell of the selected page via bit line BL and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0069] During the erase operation, the read / write circuit 123 can float the bit line BL. As an implementation, the read / write circuit 123 may include a column decoder.

[0070] In an implementation, the read / write circuit 123 may include a page buffer circuit, a first buffer circuit, and a second buffer circuit.

[0071] A page buffer circuit can include multiple page buffers. Figure 2 In this context, multiple page buffers can be from the first page buffer PB1 to the m-th page buffer PBm.

[0072] The first buffer circuit may include a first cache buffer that stores data received from the page buffer circuit.

[0073] The second buffer circuit may include a second cache buffer for storing data received from the page buffer circuit. In another embodiment, the second buffer circuit may include a plurality of adders for accumulating data received from the page buffer circuit and adding the data received from the page buffer circuit.

[0074] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates in response to the control logic 130.

[0075] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 outputs data DATA transferred from the first page buffer PB1 to the m-th page buffer PBm included in the read / write circuit 123 to the external controller.

[0076] In one implementation, the data input / output circuit 124 may include data pads that output data received from the read / write circuit 123 to an external controller.

[0077] During a read or verification operation, the sensing circuit 125 may generate a reference current in response to the signal of the enable bit VRYBIT generated by the control logic 130, and may compare the sensed voltage VPB received from the read / write circuit 123 with the reference voltage generated by the reference current to output a pass signal or a failure signal to the control logic 130.

[0078] In one embodiment, the sensing circuit 125 may include a failure bit counter that counts the failure bits included in the sensing data received from the read / write circuit 123.

[0079] Control logic 130 can be connected to address decoder 121, voltage generator 122, read / write circuit 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can be configured to control all operations of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0080] Control logic 130 can generate various signals to control peripheral circuit 120 in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, address ADDR, read / write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, address ADDR to address decoder 121, read / write control signal to read / write circuit 123, and enable bit VRYBIT to sensing circuit 125. In addition, control logic 130 can determine whether the verification operation is successful or unsuccessful in response to pass / fail signal PASS / FAIL output by sensing circuit 125.

[0081] In one implementation, the peripheral circuit 120 may use multiple read voltages to perform a first read operation on a selected memory cell among multiple memory cells.

[0082] Control logic 130 can control peripheral circuitry 120 to perform a cell counting operation in a first read operation, sensing a selected memory cell using a first read voltage among a plurality of read voltages. The cell counting operation can be an operation of counting the number of data bits with a set logic value among the data bits sensed from the selected memory cell.

[0083] Control logic 130 can adjust the remaining read voltage among multiple read voltages based on the read offset table and the cell count as a result of the cell counting operation. Control logic 130 can store the read offset table. (See reference...) Figure 6 The read offset table may include at least one of a read voltage offset, a bit line precharge voltage offset, and an evaluation time offset corresponding to each of a plurality of read voltages. See reference... Figure 7 and Figure 13 The control logic 130 can adjust at least one of the following: the read voltage level, the bit line precharge level, and the evaluation time, based on the cell count and read offset table. The control logic 130 can control the peripheral circuitry 120 to perform a first read operation on the selected memory cell using the adjusted remaining read voltage.

[0084] Control logic 130 can control peripheral circuit 120 to execute the read data output operation of the second read operation and the cell counting operation corresponding to the first read operation in parallel. The second read operation can be a read operation executed before the first read operation among multiple consecutively executed read operations. The multiple consecutively executed read operations can be buffered read operations.

[0085] Figure 3 This is an example Figure 2 A diagram of a memory cell array.

[0086] Reference Figure 3 The first storage block BLK1 to the z-th storage block BLKz are all connected to the first bit line BL1 to the m-th bit line BLm. Figure 3 For ease of description, the elements included in the first storage block BLK1 of the plurality of storage blocks BLK1 to BLKz are shown, and the elements included in each of the remaining storage blocks BLK2 to BLKz are omitted. It will be understood that each of the remaining storage blocks BLK2 to BLKz is configured similarly to the first storage block BLK1.

[0087] The memory block BLK1 may include multiple cell strings CS1_1 to CS1_m (m is a positive integer). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first cell string CS1_1 to the m-th cell string CS1_m includes a drain selection transistor DST, multiple memory cells MC1 to MCn (n is a positive integer) connected in series, and a source selection transistor SST.

[0088] The gate terminal of the drain select transistor DST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the drain select line DSL1. The gate terminals of the first memory cell MC1 to the n-th memory cell MCn included in each of the first unit strings CS1_1 to the n-th word line WL1 to the n-th word line WLn are respectively connected to the first word line WL1 to the n-th word line WLn. The gate terminal of the source select transistor SST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the source select line SSL1.

[0089] For ease of description, the structure of the unit strings will be described with reference to the first unit string CS1_1 among the multiple unit strings CS1_1 to CS1_m. However, it will be understood that each of the remaining unit strings CS1_2 to CS1_m is configured similarly to the first unit string CS1_1.

[0090] The drain terminal of the drain selection transistor DST included in the first cell string CS1_1 is connected to the first bit line BL1. The source terminal of the drain selection transistor DST included in the first cell string CS1_1 is connected to the drain terminal of the first memory cell MC1 included in the first cell string CS1_1. The first memory cell MC1 to the nth memory cell MCn are connected in series with each other. The drain terminal of the source selection transistor SST included in the first cell string CS1_1 is connected to the source terminal of the nth memory cell MCn included in the first cell string CS1_1. The source terminal of the source selection transistor SST included in the first cell string CS1_1 is connected to the common source line CSL. As an implementation, the common source line CSL can be connected to the first memory block BLK1 to the zth memory block BLKz.

[0091] Drain select line DSL1, first word line WL1 to nth word line WLn and source select line SSL1 are included Figure 2 In the row line RL, the drain selection line DSL1, the first word lines WL1 to the nth word lines WLn, and the source selection line SSL1 are controlled by the address decoder 121. The common source line CSL is controlled by the control logic 130. The first bit line BL1 to the mth bit line BLm are controlled by the read / write circuit 123.

[0092] Figure 4 This is a diagram illustrating the read operation of using logical page data and multiple read voltages according to an implementation method.

[0093] Reference Figure 4 The memory cell can be a TLC that stores three data bits. The TLC can store the most significant bit (MSB), the middle significant bit (CSB), and the least significant bit (LSB). The number of data bits stored in the memory cell is not limited to this embodiment.

[0094] The memory cell can be programmed into any of the erase state E and the first programming states P1 through the seventh programming states P7. The memory cell can store three data bits corresponding to each state. Multiple read voltages R1 through R7 can be used to distinguish between two adjacent states.

[0095] exist Figure 4 In this implementation, the erase state E can correspond to a 3-bit binary code including the data bit '111'. The first programming states P1 to the seventh programming states P7 can correspond to 3-bit binary codes including the data bits '110', '100', '000', '010', '011', '001', and '101', respectively. The value of the data bit corresponding to each state is not limited to this embodiment.

[0096] During a read operation, multiple read voltages can be applied to the selected word line, which is connected to the selected memory cell among multiple memory cells. The selected memory cells can form a physical page.

[0097] Depending on the number of data bits stored in the memory cell, a physical page can correspond to at least one logical page. In the case of TLC, a physical page can correspond to an MSB logical page, a CSB logical page, and an LSB logical page.

[0098] During a read operation on each logic page, multiple read voltages can be applied to the selected word line. For example, during a read operation on the MSB logic page, read voltages R3 and R7 can be applied to the selected word line. During a read operation on the CSB logic page, read voltages R2, R4, and R6 can be applied to the selected word line. During a read operation on the LSB logic page, read voltages R1 and R5 can be applied to the selected word line.

[0099] Figure 5 This is a diagram illustrating an implementation of adjusting the remaining read voltages based on the result of a cell counting operation using a first read voltage among multiple read voltages.

[0100] Reference Figure 5 During the programming operation, the input data can be randomized so that the memory cells are evenly distributed across each state. This randomized data can then be programmed into the memory cells. t1 can represent the initial threshold voltage distribution of the programmed memory cells.

[0101] t2 can represent the threshold voltage distribution of memory cells where retention deterioration has progressed since t1. In t2, compared to t1, the threshold voltage distribution of the memory cells may shift to the left. However, the aspects of threshold voltage distribution deterioration in memory cells are not limited to this embodiment. For example, the direction and degree of threshold voltage distribution shift may differ for each state.

[0102] exist Figure 5 In the middle, you can execute the reference. Figure 4 The MSB page read operation is described. In the MSB page read operation, read voltages R3 and R7 can be applied to the selected word line.

[0103] At t2, during the MSB page read operation, the read voltage R7 can be applied as the first read voltage to the selected word line. A sensing operation using the read voltage R7 can be performed, and the cell count can be calculated using a failure bit counter. The cell count can be the number of memory cells (failure bits) sensed as failure bits at t2 among the memory cells programmed to the seventh programming state P7, compared to t1 when the initial distribution of the threshold voltage is given.

[0104] The remaining read voltage R3 can be adjusted to read voltage R3' based on the cell count and read offset table. At t2, the adjusted remaining read voltage R3' can be used to subsequently perform MSB page read operations, thereby improving the reliability of the read operations.

[0105] The remaining read voltages, excluding the first read voltage, can be adjusted based on cell counts and a read offset table. Adjusting these remaining read voltages improves the reliability of the read operation. This can be defined as adaptive read operation (Adaptive Read Using Cell Counts (ARC)), as discussed later. Figure 7 Describe it.

[0106] Figure 6 This is an example Figure 2 The graph shows the reading of the offset table.

[0107] Reference Figure 6 The read offset table may include at least one of the following: a read voltage offset corresponding to each of a plurality of read voltages for each failure bit count level, a bit line precharge voltage offset, and an evaluation time offset.

[0108] exist Figure 6 For ease of description, the read offset table only shows the read voltage offset corresponding to each of the multiple read voltages when the failure bit count level is C1. The failure bit count level can be determined from the reference... Figure 5 The size of the described cell count determines the read voltage offset. The read voltage offset can be positive or negative. The read voltage offset can differ for each read voltage and each failure bit count level.

[0109] exist Figure 6In this context, when read voltage R1 is the first read voltage among multiple read voltages R1 to R7, and the failure bit count level determined based on the cell count sensed by read voltage R1 is C1, read voltage offsets RO2_1 to RO7_1 can be read voltage offsets of the remaining read voltages R2 to R7, respectively. The first read voltage refers to the read voltage initially applied to the selected word line during the read operation. The read voltage levels of the remaining read voltages R2 to R7 can be adjusted based on read voltage offsets RO2_1 to RO7_1.

[0110] When read voltage R2 is the first read voltage among multiple read voltages R1 to R7, and the failure bit count level determined based on the cell count sensed by read voltage R2 is C1, read voltage offsets RO1_2 and RO3_2 to RO7_2 can be the read voltage offsets of the remaining read voltages R1 and R3 to R7, respectively. The read voltage levels of the remaining read voltages R1 and R3 to R7 can be adjusted based on read voltage offsets RO1_2 and RO3_2 to RO7_2.

[0111] Similarly, when read voltage R7 is the first read voltage among multiple read voltages R1 to R7 and the failure bit count level determined based on the cell count sensed by read voltage R7 is C1, read voltage offsets RO1_7 to RO6_7 can be read voltage offsets of the remaining read voltages R1 to R6, respectively. The read voltage levels of the remaining read voltages R1 to R6 can be adjusted based on read voltage offsets RO1_7 to RO6_7.

[0112] Although reference Figure 6 An implementation of adjusting the read voltage level based on the read voltage offset has been described. However, in another implementation, the bit line precharge voltage level can be adjusted based on the bit line precharge voltage offset corresponding to each read voltage level. In yet another implementation, the evaluation time can be adjusted during the sensing period based on the evaluation time offset corresponding to each read voltage level. See below for further details. Figure 13 This will be described.

[0113] Figure 7 This is a diagram illustrating adaptive readout (ARC) using unit counts according to an implementation method.

[0114] Reference Figure 7 In reference Figure 4 During the described CSB logic page read operation, multiple read voltages R6, R4, and R2 can be applied to the selected word line. The multiple read voltages applied to the selected word line during the read operation and the type of logic page are not limited to this embodiment.

[0115] When ARC is executed, the read voltage R6, which is first applied to the selected word line among multiple read voltages, can be the first read voltage. A cell counting operation can be performed to find the cell count based on data sensed by the read voltage R6. The read offset for the remaining read voltages R4 and R2 can be calculated with reference to the read offset based on the cell count. The remaining read voltages R4 and R2 can be adjusted to read voltages R4' and R2' based on the calculated read offset.

[0116] During a normal read operation, multiple read voltages R6, R4, and R2 can be applied to the selected word line. During ARC, the first read voltage R6 and the remaining adjusted read voltages R4' and R2' can be applied to the selected word line. By performing ARC in consideration of the degradation of the threshold voltage distribution of the memory cell, data can be read more reliably compared to using a normal read operation. In this implementation, the optimal read level calculation is a process of finding the optimal read voltage using a read offset. The read offset can compensate for the effects of the degradation of the threshold voltage distribution of the memory cell.

[0117] Figure 8 This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0118] Reference Figure 8 The read / write circuit can include a page buffer circuit and a cache buffer circuit.

[0119] The page buffer circuit may include multiple page buffers PB<7:0> to PB<1023:1016>. The cache buffer circuit may include multiple cache buffers CB<7:0> to CB<1023:1016>. The multiple cache buffers CB<7:0> to CB<1023:1016> may be connected to the multiple page buffers PB<7:0> to PB<1023:1016> respectively.

[0120] The number of page buffers included in the page buffer circuit and the number of cache buffers included in the cache buffer circuit are not limited to this embodiment. A page buffer can store eight data bits. A cache buffer can store eight data bits. The number of data bits stored by the page buffer and the cache buffer is not limited to this embodiment.

[0121] Sensing data from multiple memory cells can be stored in a page buffer circuit. Data stored in the page buffer circuit can then be transferred to a cache buffer circuit. This is based on the column selection signal CS output by the column selection decoder CSDEC<127:0>. <0> To CS <127> Data stored in the buffer circuit can be sequentially transmitted to the input / output sense amplifier IOSA via the data output lines DOUT<7:0>. In the implementation, the column selection decoder CSDEC... <n:0>This refers to CSDEC <n>To CSDEC <0> A set of column select decoders. That is, column select decoder CSDEC<127:0> represents 128 column select decoders. Data transmitted to the input / output sense amplifier IOSA can be output to the data pad PAD or the failure bit counter FBC via the data line DL<7:0>.

[0122] In cell counting operations, sensed data stored in the page buffer circuit can be transferred to the cache buffer circuit. The sensed data transferred to the cache buffer circuit can be output to the failure bit counter FBC via data lines DL<7:0>. The sensed data can be obtained by sensing the selected memory cell using a first read voltage among multiple read voltages.

[0123] In data output operations, sensed data stored in the page buffer circuit can be transferred to the cache buffer circuit. Data can be read by reading logical page data obtained from the selected memory cell using multiple read voltages. The read data transferred to the cache buffer circuit can be output to the data pads (PAD) via the data lines DL<7:0>.

[0124] As will be referred to below. Figure 10 When performing a cache read operation as described, because the data output operation of the previous read operation and the cell counting operation of the current read operation share a single data line DL<7:0>, the data output operation of the previous read operation and the cell counting operation of the current read operation are not executed in parallel. In other words, the execution of the data output operation of the previous read operation does not overlap with the execution of the cell counting operation of the current read operation. Therefore, since the data output operation of the previous read operation needs to be executed after the cell counting operation of the current read operation, there may be overhead based on the cell counting operation.

[0125] Figure 9 This is an example Figure 8 The diagram shows the normal read operation and ARC in the read / write circuit structure.

[0126] Reference Figure 9 , as reference Figure 4 As described, multiple read voltages can be applied to the selected word line during a read operation. The period during which each read voltage is applied may include a word line voltage setting period (WL setting), a bit line precharge voltage setting period (BL setting), and a sensing period (sensing) for sensing the threshold voltage of the memory cell.

[0127] The first read operation O1 can be a normal read operation. In the first read operation O1, multiple read voltages R6, R4, and R2 can be applied sequentially to the selected word line.

[0128] The second read operation O2 can be a reference. Figure 6 The ARC described. The first read voltage R6 and the remaining read voltages R4' and R2' can be applied sequentially to the selected word line in the second read operation O2.

[0129] Compared to a normal read operation, ARC may include overhead due to cell counting operations and read offset calculations. The cell counting operation can be an operation that calculates cell counts based on data sensed via the first read voltage R6. The read offset calculation can be an operation that calculates read voltage offsets for the remaining read voltages R4 and R2, excluding the first read voltage, based on the cell count and a read offset table. In subsequent read operations, read voltages R4 and R2 can be adjusted to read voltages R4' and R2' based on the calculated read voltage offsets.

[0130] Figure 10 This is an example Figure 8 A diagram showing the latency of cache read operations in the read / write circuit structure.

[0131] Reference Figure 10 `Ext.Busy` indicates the busy or idle state of the memory device from an external perspective. `Int.Busy` indicates the busy or idle state of the memory device from an internal perspective.

[0132] In case 1, a cache read operation can be performed based on a normal read operation.

[0133] The first command CMD(ADD1) can be input to the memory device. The memory device can perform a first read operation in response to the first command CMD(ADD1). The first cache busy period t_busy1 can be the period during which the first read operation is performed. The read data DAT1 of the first read operation can be stored in a reference... Figure 8 In the described page buffer circuit.

[0134] When the first read operation is completed, the second command CMD(ADD2) can be input to the memory device. The memory device can then perform a second read operation in response to the second command CMD(ADD2). After inputting the second command CMD(ADD2) in the second read operation, the read data DAT1 stored in the page buffer circuit can be transferred to the cache buffer circuit. The second cache busy period t_busy2 can be the period during which the read data DAT1 stored in the page buffer circuit is transferred to the cache buffer circuit.

[0135] The read data DAT1 transmitted to the buffer circuit can be output to the external memory device. After outputting the read data DAT1, the third command CMD (ADD3) can be input to the memory device. After the second read operation is completed, the read data DAT2 stored in the page buffer circuit can be transmitted to the buffer circuit. The third buffer busy period t_busy3 can be the time from the completion of the input of the third command CMD (ADD3) to the completion of the transmission of the read data DAT2 to the buffer circuit.

[0136] In scenario 2, cache read operations can be performed based on ARC.

[0137] A first command CMD(ADD1) can be input to the memory device. The memory device can perform a first read operation in response to the first command CMD(ADD1). A first cache busy period t_busy1' can be the period during which the first read operation is performed. In this case, since the first read operation is an ARC operation different from the normal read operation in case 1, the first cache busy period t_busy1' additionally includes the overhead of the cell count operation Read1 CC corresponding to the first read operation. The read data DAT1 of the first read operation can be stored in a reference... Figure 8 In the described page buffer circuit.

[0138] When the first read operation is completed, the second command CMD(ADD2) can be input to the memory device. The memory device can then execute a second read operation in response to the second command CMD(ADD2). Since the second read operation is ARC, it can include a cell counting operation Read2 CC corresponding to the second read operation.

[0139] Because of the cell counting operation Read2 CC corresponding to the second read operation, the read data DAT1 stored in the page buffer circuit was not directly transmitted to the buffer circuit after the input of the second command CMD (ADD2) was completed in the second read operation. This is because the execution of the data output operation of the previous read operation and the execution of the cell counting operation of the current read operation do not overlap, as shown in the reference... Figure 8 As described.

[0140] Therefore, after completing the cell counting operation Read2 CC corresponding to the second read operation, the read data DAT1 stored in the page buffer circuit can be transferred to the cache buffer circuit.

[0141] The second busy period t_busy2' can be the time from the completion of the input of the second command CMD(ADD2) to the completion of the transfer of the read data DAT1 to the buffer circuit.

[0142] The read data DAT1 transmitted to the buffer circuit can be output to the outside of the memory device. After outputting the read data DAT1, the third command CMD (ADD3) can be input to the memory device. After the input of the third command CMD (ADD3) is completed, the third read operation can be executed. As described above, after completing the cell counting operation Read3 CC corresponding to the third read operation, the read data DAT2 stored in the page buffer circuit can be transmitted to the buffer circuit.

[0143] The third cache busy period t_busy3' can be the time from the completion of the input of the third command CMD (ADD3) to the completion of the transfer of data DAT2 to the cache buffer circuit.

[0144] For reference Figure 10 As mentioned above, when performing a cache read operation based on ARC, the data output operation of the previous read operation and the cell counting operation of the current read operation are not executed in parallel. Therefore, compared with a cache read operation based on a normal read operation, an ARC-based cache read operation typically increases the cache busy time.

[0145] Therefore, refer to Figure 11 , Figure 12A and Figure 12B Describes a buffer circuit structure for performing data output operations of previous read operations and cell counting operations of the current read operation in parallel.

[0146] Figure 11 This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0147] Reference Figure 11 The read / write circuit may include a reference. Figure 8 The page buffer circuit described. The read / write circuit may include a first buffer circuit and a second buffer circuit. The first buffer circuit may have the same characteristics as the referenced circuit. Figure 8 The described buffer circuit has the same structure. The second buffer circuit may have the same structure as the first buffer circuit.

[0148] The first and second buffer circuits, which operate independently of each other, can be connected to the page buffer circuit.

[0149] The first buffer circuit can be used for data output operations from previous read operations. The first buffer circuit can store the read data from previous read operations.

[0150] The second buffer circuit can be used for cell counting operations corresponding to the current read operation. The second buffer circuit can store the sensing data obtained based on the cell counting operation corresponding to the current read operation.

[0151] Therefore, since the first and second buffer circuits operate independently of each other, the data output operation of the previous read operation and the cell counting operation of the current read operation can be performed in parallel. In other words, because the data output operation of the previous read operation and the cell counting operation of the current read operation overlap, the overall cache busy time in ARC-based cache read operations can be reduced.

[0152] Figure 12A This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0153] Reference Figure 12A , refer to Figure 11 The page buffer circuit and the first buffer circuit described can have the same configuration.

[0154] The second buffer circuit may include multiple adders to replace the second buffer buffer. Figure 12A In this implementation, the adder can be a four-bit adder. However, the number of data bits calculated by the adder is not limited to this embodiment.

[0155] and Figure 11 In contrast, a second register is needed to store eight bits in the case of a second buffer, while a register is needed to store four bits in the case of an adder. Therefore, an adder can include fewer registers than the number of registers in a second buffer. That is, in implementations, by replacing the second buffer with multiple adders, fewer registers can be used, and the reference size can be further reduced. Figure 11 The area of ​​the second buffer circuit described.

[0156] Figure 12B This is an example based on the implementation method. Figure 2 The diagram shows the read / write circuit.

[0157] Reference Figure 12A The page buffer circuit and the first buffer circuit described can have the same configuration.

[0158] With reference Figure 12A The four-bit adder described is different. Figure 12B The adder in the code can be a five-bit adder. The number of registers included in an adder increases from four to five, but the total number of adders can be reduced from 128 to 64. Therefore, in implementations, the reference size can be further reduced. Figure 12A The area of ​​the second buffer circuit described.

[0159] As the number of data bits computed by the adders increases, the total number of adders decreases, but the computation time increases. Therefore, in an implementation, the number of data bits computed by the adders can be appropriately set to account for the increase in computation time and the decrease in total circuit area.

[0160] Figure 13 This is an example reference. Figure 12A and Figure 12B The diagram illustrates an implementation where the overhead of ARC is reduced.

[0161] Reference Figure 9 and Figure 13 The second read operation O2 can be an ARC in which the read voltage level of the remaining read voltage is adjusted based on the cell count and read offset.

[0162] The third operation O3 can be an ARC where the bit line precharge voltage level is adjusted based on cell count and read offset to adjust the remaining read voltage.

[0163] The fourth operation O4 can be ARC, in which the evaluation time is adjusted during the sensing period based on cell count and read offset.

[0164] Figure 14 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0165] Reference Figure 14 In step S1401, the memory device may receive a read command.

[0166] In step S1403, the memory device can initiate a read operation using multiple read voltages according to a read command.

[0167] In step S1405, the memory device may use a first read voltage among a plurality of read voltages to perform a cell counting operation.

[0168] In step S1407, the memory device may adjust the remaining read voltage among a plurality of read voltages based on the cell count as a result of the cell counting operation.

[0169] In step S1409, the memory device can use the remaining read voltage to perform a read operation.

[0170] In step S1411, the memory device may perform a read data output operation based on a read command received prior to the read command.

[0171] In this implementation, steps S1405 and S1411 can be executed in parallel. All or part of steps S1411 and S1405 can overlap.

[0172] Cross-references to related applications

[0173] This application claims priority to Korean Patent Application No. 10-2021-0086589, filed on July 1, 2021, the entire contents of which are incorporated herein by reference.< / n>

Claims

1. A memory device, the memory device comprising: Multiple memory units; The peripheral circuitry uses multiple read voltages to perform a first read operation on a selected memory cell among the plurality of memory cells; as well as The control logic, in the first read operation, controls the peripheral circuitry to perform a cell counting operation of the selected memory cell using a first read voltage among the plurality of read voltages, adjusts the remaining read voltage among the plurality of read voltages based on a read offset table and the cell count as a result of the cell counting operation, and controls the peripheral circuitry to perform the first read operation on the selected memory cell using the remaining read voltage. The control logic controls the peripheral circuitry to execute, in parallel among multiple consecutive read operations, a read data output operation of a second read operation performed before the first read operation, and a cell counting operation corresponding to the first read operation. The peripheral circuit includes: Page buffer circuit, the page buffer circuit including multiple page buffers connected to the plurality of memory cells via bit lines; A first buffer circuit and a second buffer circuit, wherein the first buffer circuit and the second buffer circuit store data received from the page buffer circuit; Data pads, the data pads outputting data received from the first buffer circuit; and A failure bit counter, which counts failure bits based on data received from the second buffer circuit, and The control logic controls the peripheral circuit to output the read data of the second read operation stored in the first buffer circuit to the data pad through the first data line, and to output the sensed data for the first read voltage stored in the second buffer circuit to the failure bit counter through the second data line.

2. The memory device according to claim 1, wherein, The first buffer circuit includes first cache buffers respectively connected to the plurality of page buffers. The second buffer circuit includes second cache buffers respectively connected to the plurality of page buffers, and The failure bit counter receives the sensed data stored in the second buffer via the second data line.

3. The memory device according to claim 1, wherein, The first buffer circuit includes first cache buffers respectively connected to the plurality of page buffers. The second buffer circuit includes multiple adders connected to the plurality of page buffers, and The failure bit counter receives the sum of sensed data stored in the plurality of adders via the second data line.

4. The memory device according to claim 3, wherein, Each of the plurality of adders is connected to at least one of the plurality of page buffers.

5. The memory device according to claim 1, wherein, The failure bit counter operates on the cell count corresponding to the first read operation based on the sensed data for the first read voltage.

6. The memory device according to claim 1, wherein, The read offset table includes at least one of the read voltage offset, bit line precharge voltage offset, and evaluation time offset corresponding to each of the plurality of read voltages.

7. The memory device according to claim 6, wherein, The peripheral circuitry adjusts at least one of the read voltage level, bit line precharge level, and evaluation time of the remaining read voltage based on the cell count and the read offset table.

8. A method of operating a memory device comprising a plurality of memory cells, the method comprising the steps of: In response to a first read command, a first read operation is performed on a selected memory cell among the plurality of memory cells using multiple read voltages; as well as In response to a second read command received prior to the first read command, read data for a second read operation on the plurality of memory cells is output. The steps for performing the first read operation include the following: Perform a cell counting operation using a first read voltage among the plurality of read voltages to sense the selected memory cell; The remaining read voltage among the plurality of read voltages is adjusted based on the read offset table and the cell count as a result of the cell counting operation; and The first read operation is performed on the selected memory cell using the remaining read voltage. The cell counting operation is performed in parallel with the step of outputting the read data of the second read operation. The memory device includes: Page buffer circuitry, the page buffer circuitry storing data sensed from the plurality of memory cells; and A first buffer circuit and a second buffer circuit, wherein the first buffer circuit and the second buffer circuit store data received from the page buffer circuit, and The steps involved in performing the cell counting operation include the following: The sensed data obtained by sensing the selected memory cell using the first read voltage is stored in the page buffer circuit; The sensed data stored in the page buffer circuit is transmitted to the second buffer circuit; and The unit count is calculated based on the sensed data.

9. The method according to claim 8, wherein, The second buffer circuit includes multiple buffers that store data bits included in the sensed data, and The step of calculating the cell count includes counting the number of data bits having a logical value based on the data bits stored in the plurality of buffer buffers.

10. The method according to claim 8, wherein, The second buffer circuit includes multiple adders, which accumulate and add the data bits included in the sensed data in units of preset data bits. The step of performing the cell count operation includes counting the number of data bits having logical values ​​set based on values ​​stored in the plurality of adders.

11. The method of claim 8, wherein, The steps for outputting the read data from the second read operation include the following: The read data stored in the page buffer circuit for the second read operation is transferred to the first buffer circuit; and The read data stored in the first buffer circuit is output to the data pad.

12. The method according to claim 8, wherein, The read offset table includes at least one of the read voltage offset, bit line precharge voltage offset, and evaluation time offset corresponding to each of the plurality of read voltages.

13. The method according to claim 8, wherein, The step of adjusting the remaining read voltage includes the following steps: adjusting at least one of the read voltage level, bit line precharge level, and evaluation time of the remaining read voltage based on the cell count and the read offset table.

14. A storage device, the storage device comprising: A memory device, the memory device comprising a plurality of memory cells; as well as A memory controller provides the memory device with a first read command and a second read command for instructing cache read operations on the plurality of memory cells. The memory device, in response to the second read command, performs a read operation on the plurality of memory cells using a plurality of read voltages. During the read operation, a cell counting operation is performed to sense the plurality of memory cells using a first read voltage among the plurality of read voltages. The remaining read voltage among the plurality of read voltages is adjusted based on a read offset table and the cell count as a result of the cell counting operation. The read operation is then performed on the plurality of memory cells using the remaining read voltage. Furthermore, an output operation based on read data from the first read command received prior to the second read command and the cell counting operation are performed in parallel. The memory device further includes: Page buffer circuit, the page buffer circuit including multiple page buffers connected to the plurality of memory cells via bit lines; A first buffer circuit and a second buffer circuit, wherein the first buffer circuit and the second buffer circuit store data received from the page buffer circuit; Data pads, the data pads outputting data received from the first buffer circuit; and A failure bit counter, which counts failure bits based on data received from the second buffer circuit, and The memory device outputs the read data stored in the first buffer circuit according to the first read command to the data pad through the first data line, and outputs the sensed data for the first read voltage stored in the second buffer circuit to the failure bit counter through the second data line.

15. The storage device according to claim 14, wherein, The read offset table includes at least one of the read voltage offset, bit line precharge voltage offset, and evaluation time offset corresponding to each of the plurality of read voltages.

16. The storage device according to claim 15, wherein, The memory device adjusts at least one of the read voltage level, bit line precharge level, and evaluation time of the remaining read voltage based on the cell count and the read offset table.

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