Method of manufacturing a semiconductor device

Abstract

Provided is a method for manufacturing a semiconductor device that improves the characteristics of the semiconductor device. The method for manufacturing a semiconductor device includes: a step of etching a conductive layer on an upper layer of an oxide semiconductor using plasma generated from a first processing gas composed of a Cl-based gas; and a step of removing a damage layer formed in a channel region of the oxide semiconductor using plasma generated from a second processing gas composed of Ar gas.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device. Background Technology

[0002] Patent Document 1 discloses a semiconductor device comprising: a gate electrode; a gate insulating film overlapping the gate electrode; an oxide stacked film overlapping the gate electrode with the gate insulating film in between; a source electrode and a drain electrode contacting the oxide stacked film; and an oxide insulating film contacting the source electrode and the drain electrode.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-78339 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] However, in BCE (Back Channel Etching) type TFTs (Thin Film Transistors) as described in Patent Document 1, after forming a conductive layer on an oxide semiconductor (oxide multilayer film), the source and drain electrodes are formed by etching the conductive layer through plasma processing. This plasma processing causes damage to the channel region of the oxide semiconductor, degrading the characteristics of the TFT.

[0008] In view of the above-mentioned technical problems, in one aspect, the objective is to provide a method for manufacturing a semiconductor device that improves the characteristics of the semiconductor device.

[0009] Technical solutions for solving technical problems

[0010] To solve the above-mentioned technical problems, a method for manufacturing a semiconductor device is provided, comprising: etching an upper conductive layer of an oxide semiconductor using a plasma formed by a first processing gas composed of Cl-type gases; and removing a damage layer formed in the channel region of the oxide semiconductor using a plasma formed by a second processing gas composed of Ar gases.

[0011] Invention Effects

[0012] In one aspect, a method for manufacturing a semiconductor device that improves the characteristics of the semiconductor device can be provided. Attached Figure Description

[0013] Figure 1This is a cross-sectional schematic diagram illustrating an example of a plasma processing apparatus according to an embodiment.

[0014] Figure 2 This is a flowchart illustrating an example of substrate processing in the manufacture of semiconductor devices.

[0015] Figure 3 This is an example of a cross-sectional schematic diagram of the substrate being processed.

[0016] Figure 4 This is an example of XPS analysis of an oxide semiconductor exposed to plasma formed by a first processing gas.

[0017] Figure 5 It represents the O on the surface of an oxide semiconductor. I With O II A chart showing an example of the peak ratio results.

[0018] Figure 6 It represents the O on the surface of an oxide semiconductor. I With O II A chart showing an example of the peak ratio results.

[0019] Figure 7 It represents the O on the surface of an oxide semiconductor. I With O II A chart showing an example of the peak ratio results.

[0020] Figure 8 It represents the O on the surface of an oxide semiconductor. I With O II A chart showing an example of the peak ratio results.

[0021] Figure 9 This is a graph showing an example of the results of the IV characteristics of a semiconductor device.

[0022] Explanation of reference numerals in the attached figures

[0023] 10. Plasma processing device

[0024] 15 First High-Frequency Power Supply (Generation Source Power Supply)

[0025] 29 Second High-Frequency Power Supply (Bias Power Supply)

[0026] 210 matrix

[0027] 220 Gate electrode

[0028] 230 gate insulating film

[0029] 240 Oxide Semiconductor

[0030] 245 Damage layer

[0031] 250 Conductor Layer

[0032] 251 Source Electrode

[0033] 252 Drain electrode

[0034] 260 Insulating film. Detailed Implementation

[0035] Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings. In the drawings, the same structural parts are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.

[0036] [Plasma Processing Device]

[0037] First, use Figure 1 The plasma processing apparatus 10 of the embodiment will be described. Figure 1 This is a cross-sectional schematic diagram showing an example of the plasma processing apparatus 10 according to an embodiment. The plasma processing apparatus 10 of this embodiment is a device that generates plasma through inductive coupling within a processing chamber 4 to process the substrate G to be processed. The plasma processing apparatus 10 of this embodiment is used, for example, for etching metal films, ITO films, oxide films, etc., and for ashing resist films during the formation of thin-film transistors on glass substrates for FPDs (Flat Panel Displays). Here, examples of FPDs include liquid crystal displays (LCDs), electroluminescent (EL) displays, and plasma display panels (PDPs).

[0038] The plasma processing apparatus 10 has a cylindrical, hermetically sealed processing container 1 made of a conductive material, such as aluminum with an anodized inner wall (acid-resistant aluminum treatment). The processing container 1 is grounded via a grounding wire 1a. The processing container 1 is divided into an upper antenna chamber 3 and a lower processing chamber 4 by a metal window 2 formed to insulate the processing container 1. In this example, the metal window 2 forms the top wall of the processing chamber 4. The metal window 2 is made of, for example, a non-magnetic and conductive metal. An example of a non-magnetic and conductive metal is aluminum or an aluminum-containing alloy. The metal window 2 is supported by the side wall of the processing container 1.

[0039] A gas supply pipe 20a is provided, running through the center of the antenna chamber 3 and communicating with the gas flow path 12. The gas flow path 12 branches into multiple branch pipes (not shown), which are connected to the partial windows of the metal windows 2, which are divided into multiple sections by the insulator 6, and supply gas to each partial window. Each partial window has a gas space (not shown) inside and multiple gas release ports on the side facing the processing chamber 4, through which gas is supplied into the processing chamber 4. The gas supply pipe 20a extends from the top of the processing container 1 outwards and is connected to the processing gas supply section 20, which includes a processing gas supply source and valve system. Therefore, in plasma processing, the processing gas supplied from the processing gas supply section 20 is released into the processing chamber 4 via the gas supply pipe 20a.

[0040] Inside the antenna chamber 3, a high-frequency (RF) antenna 13 is arranged facing the metal window 2. The RF antenna 13 is spaced apart from the metal window 2 by a spacer 17 made of insulating material. The RF antenna 13 forms a spiral antenna (not shown), and the metal window 2 is divided into partial windows, for example, 24, at the lower part of the spiral antenna. The RF antenna 13 is an example of an inductively coupled antenna arranged above the metal window 2 via the spacer 17 of insulating material in the antenna chamber 3, generating inductively coupled plasma in the processing chamber 4.

[0041] In plasma processing, high-frequency electrical power, for example at a frequency of 13.56 MHz, is supplied from a first high-frequency power source (generator power source) 15 via a matching unit 14 and a power supply component 16 to a high-frequency antenna 13 to generate an induced electric field. Although not shown in the diagram, the high-frequency antenna 13 in this example is concentrically constructed from an outer loop antenna, a middle loop antenna, and an inner loop antenna, each having power supply sections 41, 42, and 43 connected to the power supply component 16. Antenna wires extend circumferentially from these power supply sections 41, 42, and 43, forming three loop-shaped high-frequency antennas 13. A capacitor 18 is connected to the end of each antenna wire, and each antenna wire is grounded via the capacitor 18 and connected to the sidewall 3a of the high-frequency antenna 13. Using the high-frequency electrical power supplied to the high-frequency antenna 13 in this way, an induced electric field is generated within the processing chamber 4 via the metal window 2, and the processing gas supplied to the processing chamber 4 is plasmaized using this induced electric field.

[0042] Below the processing chamber 4, a stage ST for placing the substrate G to be processed, such as a glass substrate, is provided opposite the high-frequency antenna 13 through a metal window 2. The stage ST has a base 23 and an insulating frame 24. The base 23 is made of a conductive material, such as aluminum with an anodized surface.

[0043] The base 23 is housed within the insulating frame 24 and is supported by the bottom surface of the processing chamber 4. Furthermore, the side wall 4a of the processing chamber 4 is provided with an inlet / outlet 27a for feeding in and out the substrate G to be processed, and a gate 27 for opening and closing the inlet / outlet 27a.

[0044] The base 23 is connected to a second high-frequency power supply (bias power supply) 29 via a matching device 28 through a power supply line 25a disposed within the hollow support column 25. During plasma processing, the second high-frequency power supply 29 applies high-frequency electrical power for bias voltage, for example, a high-frequency electrical power with a frequency of 3.2 MHz, to the base 23. This high-frequency electrical power for bias voltage generates a bias voltage on the substrate G being processed, and ions in the plasma generated within the processing chamber 4 are attracted to the substrate G being processed.

[0045] An electrostatic chuck 26 is disposed on a base 23, on which the substrate G to be processed is placed. The electrostatic chuck 26 is configured to have a chuck electrode 26a sandwiched between insulators. The chuck electrode 26a is connected to a DC power supply 47. By applying a DC voltage to the chuck electrode 26a from the DC power supply 47, a Coulomb force is generated, and the substrate G to be processed is attracted and held by the electrostatic chuck 26.

[0046] Furthermore, within the base 23, a temperature control mechanism and a temperature sensor, consisting of heating units such as ceramic heaters and refrigerant flow paths, can be installed to control the temperature of the substrate G being processed. The piping and wiring for these mechanisms and components are routed out of the processing container 1 via the hollow support pillar 25.

[0047] A baffle 32 is provided between the workbench ST and the side wall 4a of the processing chamber 4, continuously or intermittently surrounding the workbench ST in a ring shape, allowing gas to flow from the processing chamber 4 to the exhaust space. An exhaust device 30, including a vacuum pump, is connected to the bottom of the processing chamber 4 via an exhaust pipe 31. The exhaust device 30 is used to exhaust gas from the exhaust space below the baffle 32. During plasma processing, the processing chamber 4 is set and maintained at a predetermined vacuum atmosphere (e.g., 1.33 Pa).

[0048] A He gas flow path 55 is provided between the electrostatic chuck 26 and the substrate G to be processed, for supplying He gas as a heat transfer gas. The He gas flow path 55 is connected to the He gas pipeline 56 and is connected to the He source via a pressure control valve 57.

[0049] Each component of the plasma processing apparatus 10 is connected to a control unit 50, which is composed of a computer, forming a structure controlled by the control unit 50. Furthermore, the control unit 50 is connected to a user interface 51, which includes a keyboard for inputting commands by process managers to manage the plasma processing apparatus 10, and a display for visually displaying the operating status of the plasma processing apparatus 10. The control unit 50 is also connected to a storage unit 52. The storage unit 52 stores control programs for implementing various processes in the plasma processing apparatus 10 under the control of the control unit 50, and programs (schemes) for executing processes by each component of the plasma processing apparatus 10 according to processing conditions. Schemes can be stored in a hard disk, semiconductor memory, or stored in a designated location in the storage unit 52 in a portable storage medium such as a CD-ROM or DVD. Schemes can also be appropriately transmitted from other devices via, for example, dedicated lines. Then, as needed, any scheme is retrieved from the storage unit 52 according to instructions from the user interface 51, and the control unit 50 executes it, thereby performing the desired processing on the substrate G within the processing chamber 4 of the plasma processing apparatus 10.

[0050] In the plasma processing apparatus 10 with the above-described structure, an induced electric field is formed in the processing chamber 4 via the metal window 2 using the high-frequency electrical power supplied to the high-frequency antenna 13. This induced electric field is used to plasmaize the processing gas supplied to the processing chamber 4, and the substrate G to be processed is subjected to the desired processing using inductively coupled plasma.

[0051] Next, use Figure 2 and Figure 3 The manufacturing method of semiconductor devices is explained. Figure 2 This is a flowchart illustrating an example of substrate processing in the manufacture of semiconductor devices. Figure 3 This is an example of a cross-sectional schematic diagram of the substrate G being processed. Here, as a semiconductor device, a BCE (Back Channel Etching) type TFT (Thin Film Transistor) is formed.

[0052] In step S101, the substrate G to be processed is prepared. Figure 3 (a) is an example of a cross-sectional schematic diagram of the substrate G to be processed prepared in step S101. The substrate G to be processed has a substrate 210, a gate electrode 220, a gate insulating film 230, an oxide semiconductor 240, and a conductive layer 250.

[0053] The substrate 210 is formed, for example, of an insulating film such as a silicon oxide film or a silicon nitride film. The gate electrode 220 is formed, for example, of a conductor such as molybdenum or tungsten, and is formed on the substrate 210. The gate insulating film 230 is formed, for example, of an insulator such as a silicon oxide film or a silicon nitride film, and is formed on the substrate 210 and the gate electrode 220. The oxide semiconductor 240 is formed, for example, of an indium gallium zinc oxide semiconductor (hereinafter also referred to as IGZO), and is formed on the gate insulating film 230. The conductive layer 250 is formed, for example, of a conductor such as titanium, aluminum, or tungsten, and is formed on the oxide semiconductor 240 and the gate insulating film 230.

[0054] In step S102, the conductive layer 250 is etched to form the source electrode 251 and the drain electrode 252. First, a photoresist mask (not shown) is formed on the conductive layer 250. Next, the conductive layer 250 is etched using the photoresist mask to form the source electrode 251 and the drain electrode 252. Here, a plasma processing apparatus 10 (see reference 10) is used. Figure 1 An etching gas (first processing gas) is supplied from the processing gas supply unit 20 into the processing chamber 4. Plasma is generated within the processing chamber 4 via inductive coupling, thereby etching the conductive layer 250. The etching gas can be a gas containing Cl (Cl-type gas), such as Cl2 gas or Cl2 with added BCl3. Then, the photoresist mask is removed.

[0055] Figure 3 (b) is an example of a cross-sectional schematic diagram of the substrate G that underwent etching in step S102. By etching the conductive layer 250, a source electrode 251 and a drain electrode 252 are formed.

[0056] Furthermore, the plasma etching the conductive layer 250 damages the oxide semiconductor 240, forming a damage layer (oxygen defect layer) 245. For example... Figure 3 As shown in (b), a damage layer 245 is formed in the channel region between the source electrode 251 and the drain electrode 252. In the damage layer 245, the oxide semiconductor 240 is exposed to plasma, thereby generating oxygen (O) defects (vacancies), and the oxide semiconductor 240 becomes conductive.

[0057] In step S103, the damaged layer (oxygen defect layer) 245 of the oxide semiconductor 240 is removed. Here, a plasma processing apparatus 10 (see reference 10) is used. Figure 1Ar gas (the second processing gas) is supplied from the processing gas supply unit 20 into the processing chamber 4, where plasma is generated via inductive coupling. For example, the Ar gas is pressurized to 10 mT, the generation source power of the first high-frequency power supply (generation source power supply) 15 is set to 4 kW, and the bias power of the second high-frequency power supply (bias power supply) 29 is set to 2 kW, and a discharge process is performed for 120 seconds. Through this process, argon (Ar) is ionized by the generation source power, and the ionized argon (Ar) has kinetic energy due to the bias power, colliding with the surface of the substrate G being processed. By colliding the ionized argon (Ar) with the damaged layer 245 of the oxide semiconductor 240, the damaged layer 245 is physically etched and removed.

[0058] Figure 3 (c) is an example of a cross-sectional schematic diagram of the substrate G processed in step S103. The damaged layer 245 (see reference) is removed by ionized argon (Ar) collision. Figure 3 (b)

[0059] In step S104, an insulating film 260 is formed on the oxide semiconductor 240, the source electrode 251, and the drain electrode 252. The insulating film 260 is formed, for example, from an insulator such as a silicon oxide film or a silicon nitride film. The insulating film 260 is formed, for example, by a CVD (Chemical Vapor Deposition) apparatus.

[0060] Figure 3 (d) is an example of a cross-sectional schematic diagram of the substrate G that has undergone processing in step S104. An insulating film 260 is formed on the oxide semiconductor 240, the source electrode 251, and the drain electrode 252.

[0061] In step S105, the substrate G is subjected to an annealing process. The annealing process activates the semiconductor device. As a result, a TFT, serving as a semiconductor device, is formed on the substrate G.

[0062] Next, use Figures 4 to 7 The damage to the oxide semiconductor 240 is explained.

[0063] Figure 4This is an example of XPS analysis of an oxide semiconductor 240 exposed to plasma formed by a first processing gas. Here, damage to the oxide semiconductor 240 during the etching process of the conductive layer 250 in step S102 is simulated. Plasma etching is performed on the oxide semiconductor 240 (IGZO) using the first processing gas (Cl2 gas), forming a damage layer 245 on the surface of the oxide semiconductor 240. XPS analysis is then performed on the oxide semiconductor 240 with the damage layer 245 formed on its surface.

[0064] Figure 4 In (a), the horizontal axis represents the binding energy (eV), and the vertical axis represents the intensity (au). Furthermore, spectrum 301 represents the results of XPS analysis of the surface of the oxide semiconductor 240. Additionally, spectra 302–312 represent the results of XPS analysis at locations where the surface of the oxide semiconductor 240 is penetrated 1.3 nm in the depth direction. Figure 4 (b) represents the results of XPS analysis of the surface of oxide semiconductor 240. Figure 4 (c) represents the result of XPS analysis at a depth of 1.3 nm from the surface of oxide semiconductor 240.

[0065] Here, the spectrum of the O1s orbital (represented by solid lines) can be separated into O I Spectrum (represented by dashed lines) and O II Spectrum (represented by dashed lines). I The spectrum is based on the bonding of oxygen atoms with metal atoms. O II The spectrum is based on oxygen vacancies (oxygen defects). Therefore, O I The peak intensity of the spectrum (indicated by arrows) and O II The ratio of peak intensity (indicated by arrows) of the spectrum (O) I With O II Peak ratio, O I / O II It is used as an indicator of oxygen vacancies. The more oxygen vacancies, the higher the O2 content. I With O II Peak ratio (O) I / O II The smaller the value, the fewer oxygen vacancies, and the lower the oxygen content. I With O II Peak ratio (O) I / O II The larger it is.

[0066] exist Figure 4 In (b), O I With O II Peak ratio (O) I / OII The value is 0.31. Figure 4 O in (c) I With O II Peak ratio (O) I / O II The value is 35.6. That is, compared with... Figure 4 Compared to the surface of the oxide semiconductor 240 shown in (b), O I With O II Peak ratio (O) I / O II From Figure 4 As shown in (c), the oxide semiconductor 240 increases sharply from a depth of 1.3 nm from its surface. That is, the damage layer 245 of the oxide semiconductor 240 is locally present within 1.5 nm from its surface.

[0067] Figure 5 It represents the O on the surface of oxide semiconductor 240. I With O II Peak ratio (O) I / O II A graph illustrating an example of the results. Here, the effects of the types of the first and second processing gases on the damage to the oxide semiconductor 240 and the improvement of that damage are explained.

[0068] Figure 5 (a) represents the O on the surface of the untreated (initial) oxide semiconductor 240. I With O II Peak ratio (O) I / O II ). Figure 5 (b) indicates that the surface of the oxide semiconductor 240 was treated with a gas obtained by adding BCl3 gas to Cl2 gas as the first processing gas, and the treatment was performed using plasma formed by the first processing gas. I With O II Peak ratio (O) I / O II ). Figure 5 (c) indicates that the surface of the oxide semiconductor 240 was treated using Cl2 gas as the first processing gas and plasma formed by the first processing gas was used to remove O. I With O II Peak ratio (O) I / O II ).

[0069] and Figure 5 Compared to the surface of the untreated oxide semiconductor 240 shown in (a), the surface treated by using... Figure 5The surface of the oxide semiconductor 240, treated by the plasma formed by the first processing gas shown in (b) and (c), was subjected to processing. I With O II Peak ratio (O) I / O II This reduces [the damage]. Specifically, the plasma formed by the first processing gas causes damage to the oxide semiconductor 240. Furthermore, the addition of BCl3 gas... Figure 5 (b) and (without BCl3 gas) Figure 5 Compared to (c), the damage to oxide semiconductor 240 is greater.

[0070] Figure 5 (d) to (g) use a gas obtained by adding BCl3 gas to Cl2 gas as the first processing gas, and use plasma formed by the first processing gas to process the oxide semiconductor 240. Figure 5 (d) indicates that the surface of the oxide semiconductor 240 was treated using O2 gas as the second processing gas and the treatment was performed using plasma formed by the second processing gas. I With O II Peak ratio (O) I / O II ). Figure 5 (e) indicates that the surface of the oxide semiconductor 240 was treated using a mixture of CF4 and O2 as the second processing gas, and the treatment was performed using plasma formed by the second processing gas. I With O II Peak ratio (O) I / O II ). Figure 5 (f) indicates that the surface of the oxide semiconductor 240 was processed using Ar gas as the second processing gas and the plasma formed by the second processing gas was used to process the O. I With O II Peak ratio (O) I / O II ). Figure 5 (g) indicates that the surface of the oxide semiconductor 240 was treated using O2 gas as a second processing gas, and then a bias electric power was applied to utilize the plasma formed by the second processing gas. I With O II Peak ratio (O) I / O II ).

[0071] Plasma treatment of O2 gas (see reference) Figure 5 Plasma treatment of (d) and mixed gases of CF4 and O2 (refer to) Figure 5In (e)), no improvement in the damage to the oxide semiconductor 240 was observed. On the other hand, in Ar gas plasma treatment (see...) Figure 5 In (f)), the damage to the oxide semiconductor 240 was improved. Furthermore, plasma treatment with O2 gas under applied bias power (see reference...) Figure 5 In (d), the damage to oxide semiconductor 240 is aggravated.

[0072] Figure 6 It represents the O on the surface of oxide semiconductor 240. I With O II Peak ratio (O) I / O II A graph illustrating an example of the results. Here, the effect of the ratio of the source power to the bias power during plasma treatment on the improvement of damage to the oxide semiconductor 240 is explained.

[0073] exist Figure 6 In this process, a gas obtained by adding BCl3 gas to Cl2 gas is used as the first processing gas. After the oxide semiconductor 240 is processed using plasma formed by the first processing gas, Ar gas is used as the second processing gas, and the oxide semiconductor 240 is processed using plasma formed by the second processing gas. I With O II Peak ratio (O) I / O II Furthermore, the Ar gas supply rate was set to 1000 sccm, the pressure in the processing chamber 4 was set to 10 mT, the power of the generator source was set to 4 kW, and the processing time was set to 120 seconds. The results are shown below when the bias power is set to 0 kW, 2 kW, and 4 kW, respectively. Additionally, Ref represents the O of the oxide semiconductor 240 processed using plasma formed from the first processing gas. I With O II Peak ratio (O) I / O II ).

[0074] like Figure 6 As shown, when the bias power is 2kW and 4kW, O I With O II Peak ratio (O) I / O II Significant improvement. In other words, within a range where the ratio of "source power to bias power" is greater than 2:1 and less than 1:1, damage to the oxide semiconductor 240 can be appropriately improved.

[0075] Figure 7 It represents the O on the surface of oxide semiconductor 240. I With OII Peak ratio (O) I / O II A graph illustrating an example of the results. Here, the effect of improving the damage to the oxide semiconductor 240 caused by processing time is explained.

[0076] exist Figure 7 In this process, a gas obtained by adding BCl3 gas to Cl2 gas is used as the first processing gas. After the oxide semiconductor 240 is processed using plasma formed by the first processing gas, Ar gas is used as the second processing gas, and the surface of the oxide semiconductor 240 is treated using plasma formed by the second processing gas to remove O. I and O II Peak ratio (O) I / O II Furthermore, in plasma processing using the second processing gas, the Ar gas supply rate is set to 1000 sccm, the pressure of processing chamber 4 is set to 10 mT, the power of the generation source is set to 4 kW, and the bias power is set to 2 kW. Figure 7 (b) represents the result when the processing time for the second processing gas is set to 120 seconds. Figure 7 (c) represents the result when the processing time for the second processing gas is set to 240 seconds. Furthermore, Figure 7 (a) represents the O on the surface of the oxide semiconductor 240 that has been processed using plasma formed by the first processing gas. I With O II Peak ratio (O) I / O II ).

[0077] like Figure 7 As shown, when the processing time is 120 seconds, the O on the surface of the oxide semiconductor 240 I With O II Peak ratio (O) I / O II Significant improvement. Furthermore, as shown in the results at a processing time of 240 seconds, it can be confirmed that O... I With O II Peak ratio (O) I / O II (This is relative to the saturation of processing time.)

[0078] Next, use Figure 8 and Figure 9 The damage to oxide semiconductor 240 and the characteristics of semiconductor devices are explained.

[0079] Figure 8 It represents the O on the surface of oxide semiconductor 240. I With OII Peak ratio (O) I / O II A chart showing an example of the results.

[0080] Figure 8 (a) represents the O on the surface of the untreated (initial) oxide semiconductor 240. I With O II Peak ratio (O) I / O II ). Figure 8 (b) indicates that the surface of the oxide semiconductor 240 was treated using Cl2 gas as the first processing gas and plasma formed by the first processing gas. I With O II Peak ratio (O) I / O II ). Figure 8 (c) indicates that the oxide semiconductor 240 surface O was treated using a gas obtained by adding BCl3 gas to Cl2 gas as the first processing gas, and the treatment was performed using plasma formed by the first processing gas. I With O II Peak ratio (O) I / O II ). Figure 8 (d) indicates that the oxide semiconductor 240 is treated with a gas obtained by adding BCl3 gas to Cl2 gas as the first processing gas, and then Ar gas is used as the second processing gas to treat the surface of the oxide semiconductor 240 with plasma formed by the second processing gas. I With O II Peak ratio (O) I / O II In addition, in Figure 8 In the middle, O I With O II Peak ratio (O) I / O II The standardization was performed with (a) set to 1.

[0081] Figure 9 It means Figure 8 A graph illustrating an example of the IV characteristics of the semiconductor device in (b) to (d). The horizontal axis of each graph represents the gate-source voltage Vgs, and the vertical axis represents the drain current Id. Furthermore, the results for a drain voltage Vd of 5.1V are shown with a solid line, and the results for a drain voltage Vd of 0.1V are shown with a dashed line. Figure 9The term "etching" refers to the state in step S102 where the conductive layer 250 is etched to form the source electrode 251 and the drain electrode 252 (see reference). Figure 3 IV characteristics of each semiconductor device under (b)). Figure 9 The term "Ar treatment" indicates the state in step S103 where the damaged layer 245 of the oxide semiconductor 240 has been removed (see reference). Figure 3 IV characteristics of each semiconductor device under (c)). Figure 9 The “CVD” indicates the state in step S104 where the insulating film 260 is formed (refer to...). Figure 3 IV characteristics of each semiconductor device in (d)). Figure 9 The term "after annealing" indicates the IV characteristics of each semiconductor device after the annealing process in step S105.

[0082] exist Figure 9 In step (b), Cl2 gas is used as the first processing gas in step S102, step S103 is skipped, the insulating film 260 is formed in step S104, and annealing is performed in step S105 to form a semiconductor device. Hysteresis occurs in the IV characteristics after annealing. Furthermore, the drain current Id increases when the gate-source voltage Vgs is greater than 0V.

[0083] exist Figure 9 In step (c), the gas obtained by adding BCl3 gas to Cl2 gas is used as the first processing gas in step S102. Step S103 is skipped, and the insulating film 260 is formed in step S104. In step S105, annealing is performed to form a semiconductor device. In the IV characteristics after annealing, insulation occurs.

[0084] exist Figure 9 In step (d), in step S102, a gas obtained by adding BCl3 gas to Cl2 gas is used as the first processing gas; in step S103, Ar gas is used as the second processing gas; in step S104, an insulating film 260 is formed; and in step S105, an annealing process is performed to form a semiconductor device. The IV characteristics after annealing show improved hysteresis. Furthermore, the drain current Id increases when the gate-source voltage Vgs is approximately 0V. That is, the IV characteristics of the semiconductor device can be improved.

[0085] As explained above, the semiconductor device manufacturing method according to this embodiment can improve the damage of oxide semiconductor 240 and improve the characteristics of semiconductor device.

[0086] The methods for manufacturing semiconductor devices according to the embodiments disclosed in this invention are illustrative in all respects and should not be considered limiting. The embodiments can be modified and improved in various ways without departing from the appended scope (claims) and their spirit. The contents described in the above embodiments can be otherwise configured and combined without contradiction.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: The step of etching the upper conductive layer of an oxide semiconductor using plasma formed by a first processing gas composed of Cl-type gases. and The step of physically etching away a damage layer formed in the channel region of the oxide semiconductor using a plasma formed by a second processing gas composed of Ar gas, wherein the damage layer is an oxygen defect layer.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that: The oxide semiconductor is an indium gallium zinc oxide semiconductor.

3. The method for manufacturing a semiconductor device as described in claim 1 or 2, characterized in that: In the step of etching the damaged layer, the ratio of the source power to the bias power is greater than 2:1 and less than 1:1.

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