Capacitance test structure of flash memory device and method of manufacturing the same

Abstract

The application provides a capacitor test structure of a flash memory device and a preparation method thereof. The method comprises the following steps: providing a semiconductor structure; removing a floating gate polysilicon layer, an intergate dielectric layer, a control gate polysilicon layer and the floating gate oxide layer formed in a peripheral device area to expose the substrate, and forming a peripheral gate oxide layer and a peripheral gate polysilicon layer on the surface thereof; etching the floating gate polysilicon layer, the intergate dielectric layer and the control gate polysilicon layer formed in a memory device area to form a memory device unit; etching the peripheral gate polysilicon layer to form a peripheral polysilicon gate, and synchronously etching the control gate polysilicon layer with a preset width and the intergate dielectric layer with a preset thickness below the control gate polysilicon layer at the edge of a capacitor test area to form a lower plate of the capacitor test structure, at this time, the control gate polysilicon layer of the capacitor test area is an upper plate of the capacitor test structure. The application solves the problem that the thickness of the intergate dielectric layer cannot be directly tested by using the existing method.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a capacitor test structure of a flash memory device and a preparation method thereof. BACKGROUND

[0002] The thickness of the interpoly dielectric layer (IPO) between the control gate and the floating gate in the flash memory device is very critical, which determines the coupling efficiency of the control gate and the floating gate of the flash memory device and the reliability of the data retention. If the thickness of the interpoly dielectric layer is too thick, the coupling efficiency of the device will be too low, and if the thickness of the interpoly dielectric layer is too thin, the data retention will fail. Therefore, it is necessary to detect the electrical thickness of the interpoly dielectric layer.

[0003] However, in the basic process of the flash memory device, the control gate and the floating gate are defined together, so the thickness of the interpoly dielectric layer cannot be directly tested. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a capacitor test structure of a flash memory device and a preparation method thereof, which solves the problem that the thickness of the interpoly dielectric layer cannot be directly tested by the existing method.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides a preparation method of a capacitor test structure of a flash memory device, which comprises:

[0006] Step 1) providing a semiconductor structure, wherein the semiconductor structure is divided into a memory device area, a capacitor test area and a peripheral device area, and the semiconductor structure comprises a substrate and a floating gate oxide layer, a floating gate polysilicon layer, an interpoly dielectric layer and a control gate polysilicon layer formed on the substrate in sequence;

[0007] Step 2) removing the floating gate polysilicon layer, the interpoly dielectric layer, the control gate polysilicon layer and the floating gate oxide layer formed in the peripheral device area to expose the substrate, and forming a peripheral gate oxide layer and a peripheral gate polysilicon layer on the surface thereof;

[0008] Step 3) etching the floating gate polysilicon layer, the interpoly dielectric layer and the control gate polysilicon layer formed in the memory device area to form a memory device unit, and the memory device unit and the capacitor test area have a spacing therebetween;

[0009] Step 4) etching the peripheral gate polysilicon layer to form a peripheral polysilicon gate, and the peripheral polysilicon gate and the capacitor test area have a spacing therebetween, and synchronously etching the control gate polysilicon layer of a predetermined width at the edge of the capacitor test area and the interpoly dielectric layer of a predetermined thickness thereunder to form a lower plate of a capacitor test structure, at this time, the control gate polysilicon layer of the capacitor test area is an upper plate of the capacitor test structure.

[0010] Optionally, the semiconductor structure comprises a word line polysilicon and a definition oxide layer, wherein the floating gate polysilicon layer, the inter-gate dielectric layer and the control gate polysilicon layer are formed on both sides of the word line polysilicon, and the definition oxide layer is formed on the surface of the control gate polysilicon layer and the word line polysilicon in the memory device region, for defining the range of the control gate.

[0011] Optionally, the semiconductor structure further comprises a shallow trench isolation structure, which is used for isolating the memory device region, the capacitance test region and the peripheral device region.

[0012] Optionally, before step 2) is performed, the method comprises a step of forming a hard mask layer on the surface of the control gate polysilicon layer, which is used for protecting the memory device region and the capacitance test region when step 2) is performed.

[0013] Optionally, before step 3) is performed, the method comprises a step of removing the hard mask layer.

[0014] Optionally, in step 4), the control gate polysilicon layer of a preset width near the memory device region on one side of the capacitance test region and the inter-gate dielectric layer of a preset thickness thereunder are etched to form the lower plate of the capacitance test structure.

[0015] Optionally, before step 4) is performed, the method comprises a step of forming a mask layer on the surface of the structure formed in step 3) and performing a patterning process thereon.

[0016] Optionally, the method further comprises a step of forming a contact hole on the surface of the upper plate and the lower plate.

[0017] Optionally, the inter-gate dielectric layer comprises an ONO structure, which comprises a bottom oxide layer, an intermediate nitride layer and a top oxide layer, wherein the intermediate nitride layer is formed between the bottom oxide layer and the top oxide layer, and in step 4), when the inter-gate dielectric layer of the preset thickness is etched, the top oxide layer and the intermediate nitride layer are etched and removed and stopped on the bottom oxide layer.

[0018] Optionally, the inter-gate dielectric layer comprises an oxide layer, and in step 4), when the inter-gate dielectric layer of the preset thickness is etched, the inter-gate dielectric layer is required to be etched completely.

[0019] Correspondingly, the application also provides a capacitance test structure of a flash memory device, which is prepared by using the preparation method in any of the above-mentioned schemes.

[0020] As described above, the capacitor test structure of the flash memory device and the preparation method thereof of the present application, by forming the peripheral polysilicon layer before the peripheral device area after the internal structure (semiconductor structure) of the flash memory device is completed, then forming the memory device unit in the memory device area, finally, forming the capacitor test structure in the capacitor test area, and forming the peripheral polysilicon gate in the peripheral device area. The capacitor test structure formed by the above-mentioned way can realize the test of the thickness of the gate dielectric layer; and moreover, the capacitor test structure formed by the above-mentioned method does not need to increase the additional mask, and can achieve the purpose of reducing the process steps and saving the process cost. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The flow chart of the preparation method of the capacitor test structure of the flash memory device of the present application is shown.

[0022] Figure 2 The cross-sectional structure schematic diagram of the semiconductor structure of the present application is shown.

[0023] Figure 3 The cross-sectional structure schematic diagram of the structure shown after removing the hard mask layer is shown. Figure 2 The cross-sectional structure schematic diagram of the structure shown after removing the control gate polysilicon layer, the gate dielectric layer, the floating gate polysilicon layer and the floating gate oxide layer of the peripheral device area of the structure and forming the peripheral gate oxide layer is shown.

[0024] Figure 4 The cross-sectional structure schematic diagram of the structure shown after forming the peripheral gate polysilicon layer of the peripheral device area of the structure is shown. Figure 3

[0025] The cross-sectional structure schematic diagram of the structure shown after removing the hard mask layer is shown. Figure 5 Figure 4 The cross-sectional structure schematic diagram of the structure shown after forming the memory device unit of the memory device area of the structure is shown.

[0026] Figure 6 Figure 5 The cross-sectional structure schematic diagram of the structure shown after forming the patterned photoresist of the memory device area, the capacitor test area and the peripheral device area of the structure is shown.

[0027] Figure 7 The cross-sectional structure schematic diagram of the structure shown after forming the capacitor test structure of the capacitor test area of the structure is shown. Figure 6

[0028] The cross-sectional structure schematic diagram of the structure shown after forming the contact hole on the surface of the structure is shown. Figure 8 Figure 6 The cross-sectional structure schematic diagram of the structure shown after forming the contact hole on the surface of the structure is shown.

[0029] Figure 9 Figure 8 The cross-sectional structure schematic diagram of the structure shown after forming the contact hole on the surface of the structure is shown.

[0030] BRIEF DESCRIPTION OF DRAWINGS ​​​​

[0031] 100: semiconductor structure; 101: substrate; 102: floating gate oxide layer; 103: floating gate polysilicon layer; 104: inter-gate dielectric layer; 105: control gate polysilicon layer; 106: word line polysilicon; 107: defining oxide layer; 108: tunneling oxide layer; 109: side wall; 109a: first oxide layer; 109b: second nitride layer; 110: shallow trench isolation structure; 111: peripheral gate oxide layer; 112: peripheral gate polysilicon layer; 112a: peripheral polysilicon gate; 200: hard mask layer; 300: memory device cell; 400: mask layer; 500: contact hole; 600: interlayer dielectric layer DETAILED DESCRIPTION

[0032] Other advantages and effects of the present application will be easily understood by those skilled in the art from the above description. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0033] Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings. Figures 1 to 9 It is to be understood that the drawings only show the basic concept of the present application, and the components shown in the drawings are not drawn according to the number, shape and size of the components in actual implementation, and the shape, number and proportion of the components in actual implementation can be arbitrarily changed, and the layout form of the components can be more complex.

[0034] As shown in Figure 1 The present embodiment provides a method for preparing a capacitance test structure of a flash memory device, which comprises steps 1), 2), 3) and 4).

[0035] As shown in Figure 2 In step 1), a semiconductor structure 100 is provided, which is divided into a memory device area A, a capacitance test area B and a peripheral device area D, and comprises a substrate 101 and a floating gate oxide layer 102, a floating gate polysilicon layer 103, an inter-gate dielectric layer 104 and a control gate polysilicon layer 105 formed on the substrate 101 in sequence.

[0036] Specifically, the semiconductor structure 100 comprises a word line polysilicon 106 and a defining oxide layer 107, wherein the floating gate polysilicon layer 103, the gate oxide layer 102 and the control gate polysilicon layer 105 are formed on both sides of the word line polysilicon 106, and the defining oxide layer 107 is formed on the surface of the control gate polysilicon layer 105 and the word line polysilicon 106 in the memory device area A, for defining the range of the control gate.

[0037] As shown in Figure 2 the embodiment, the word line polysilicon 106 has a tunneling oxide layer 108 between the substrate 101, the floating gate polysilicon layer 103, the inter-gate dielectric layer 104 and the control gate polysilicon layer 105, and a side wall 109 is formed outside the tunneling oxide layer 108, the side wall 109 includes a first oxide layer 109a and a second nitride layer 109b, and the second nitride layer 109b is formed between the first oxide layer 109a and the tunneling oxide layer 108.

[0038] The material of the definition oxide layer 107 includes silicon oxide, which is used to define the length and width of the control gate.

[0039] Specifically, the semiconductor structure 100 further includes a shallow trench isolation structure 110, which is used to isolate the memory device area A, the capacitance test area B and the peripheral device area D.

[0040] As an example, the inter-gate dielectric layer 104 includes an ONO structure, which includes a bottom oxide layer, an intermediate nitride layer and a top oxide layer, and the intermediate nitride layer is formed between the bottom oxide layer and the top oxide layer, and in step 4), when etching the inter-gate dielectric layer 104 with the preset thickness, the top oxide layer and the intermediate nitride layer are etched and removed, and the etching stops on the bottom oxide layer. In the embodiment, the material of the bottom oxide layer and the top oxide layer includes silicon oxide, and the material of the intermediate nitride layer includes silicon nitride.

[0041] As an example, the inter-gate dielectric layer 104 includes an oxide layer, and in step 4), when etching the inter-gate dielectric layer 104 with the preset thickness, it is necessary to ensure that the inter-gate dielectric layer 104 is not etched completely. In the embodiment, the material of the oxide layer includes silicon oxide.

[0042] Specifically, before step 2) is performed, the method includes a step of forming a hard mask layer 200 on the surface of the control gate polysilicon layer 105, which is used to protect the memory device area A and the capacitance test area B when step 2) is performed. In the embodiment, the material of the hard mask layer 200 is silicon oxide.

[0043] As shown in Figure 3 and Figure 4 in step 2), the floating gate polysilicon layer 103, the inter-gate dielectric layer 104, the control gate polysilicon layer 105 and the floating gate oxide layer 102 formed in the peripheral device area D are removed to expose the substrate 101, and a peripheral gate oxide layer 111 and a peripheral gate polysilicon layer 112 are formed on the surface thereof.

[0044] In this embodiment, the floating gate oxide layer 102 will be damaged when the floating gate polysilicon layer 103, the inter-gate dielectric layer 104 and the control gate polysilicon layer 105 are removed by etching process. If the floating gate oxide layer 102 is remained in the peripheral device region D, the performance of the device will be affected. Therefore, the floating gate oxide layer 102 is removed by cleaning process to form the peripheral gate oxide layer 111 in the peripheral device region D. When the peripheral gate polysilicon layer 112 is formed, a polysilicon layer can be formed on the whole surface of the semiconductor structure 100 by furnace tube process, and then the polysilicon layer formed in the memory device region A and the capacitor test region B is removed by etching process, and only the polysilicon layer in the peripheral device region D is remained as the peripheral gate polysilicon layer 112. The material of the peripheral gate oxide layer 111 includes silicon oxide.

[0045] Specifically, before step 3) is performed, the method includes a step of removing the hard mask layer 200. As shown in Figure 5 In this embodiment, the hard mask layer 200 can be removed by wet etching process.

[0046] As shown in Figure 6 In step 3), the floating gate polysilicon layer 103, the inter-gate dielectric layer 104 and the control gate polysilicon layer 105 formed in the memory device region A are etched to form memory device units 300, and the memory device units 300 and the capacitor test region B have a spacing therebetween.

[0047] In this embodiment, when step 3) is performed, the capacitor test region B and the peripheral device region D are protected by a photoresist layer, the photoresist layer formed in the memory device region A is patterned, and then the control gate polysilicon layer 105, the inter-gate dielectric layer 104 and the floating gate polysilicon layer 103 in the region other than the region covered by the definition oxide layer 107 are etched by etching process to form memory device units 300.

[0048] As shown in Figure 7 and Figure 8 In step 4), the peripheral gate polysilicon layer 112 is etched to form a peripheral polysilicon gate 112a, and the peripheral polysilicon gate 112a and the capacitor test region B have a spacing therebetween, and the control gate polysilicon layer 105 with a preset width at the edge of the capacitor test region B and the inter-gate dielectric layer 104 with a preset thickness thereunder are etched synchronously to form a lower plate of a capacitor test structure, at this time, the control gate polysilicon layer 105 of the capacitor test region B is an upper plate of the capacitor test structure.

[0049] In the embodiment, the lower plate of the capacitance test structure is the floating gate polysilicon layer 103 and a certain thickness of the inter-gate dielectric layer 104 (the bottom oxide layer of the ONO structure or a certain thickness of the oxide layer) reserved on the surface thereof, and the upper plate of the capacitance test structure is the control gate polysilicon layer 105 formed in the capacitance test region B.

[0050] In the embodiment, since the material of the inter-gate dielectric layer 104 includes the oxide layer, and the oxide layer has a high selectivity to polysilicon, when the control gate polysilicon layer 105 of the capacitance test region B, the inter-gate dielectric layer 104, the floating gate polysilicon layer 103 and the peripheral gate polysilicon layer 112 of the peripheral device region D are etched, the capacitance test region B can be left with a certain thickness of the inter-gate dielectric layer 104, and the unprotected peripheral gate polysilicon layer 112 of the peripheral device region D can be completely etched and removed to expose the peripheral gate oxide layer 111.

[0051] Specifically, in step 4), the control gate polysilicon layer 105 of a predetermined width on the side of the capacitance test region B close to the memory device region A and the inter-gate dielectric layer 104 of a predetermined thickness thereunder are etched to form the lower plate of the capacitance test structure.

[0052] Specifically, before step 4) is performed, the method includes the step of forming a mask layer 400 on the surface of the structure formed in step 3) and patterning the mask layer 400.

[0053] As shown in FIG. 4B, after the mask layer 400 is formed on the surface of the structure formed in step 3), the mask layer 400 is patterned. Figure 7 In the embodiment, the mask layer 400 is patterned to expose the control gate polysilicon layer 105 of a predetermined width on the side of the capacitance test region B close to the memory device region A, the peripheral gate polysilicon layer 112 of a certain width on the side of the peripheral device region D close to the capacitance test region B, and the peripheral gate polysilicon layer 112 of a certain width on the side of the peripheral device region D away from the capacitance test region B. In the embodiment, the material of the mask layer 400 includes photoresist.

[0054] Specifically, the method further includes the step of forming a contact hole 500 on the surface of the upper plate and the lower plate.

[0055] As shown in FIG. 4B, after the mask layer 400 is formed on the surface of the structure formed in step 3), the mask layer 400 is patterned. Figure 9 In the embodiment, an interlayer dielectric layer 600 is formed on the surface of the structure formed in step 4), and the contact hole 500 is formed in the interlayer dielectric layer 600.

[0056] In the embodiment, when the thickness of the inter-gate dielectric layer 104 between the control gate polysilicon layer 105 and the floating gate polysilicon layer 103 is measured by using the formed capacitor test structure, the upper plate and the lower plate are applied with voltage, and the distance d (i.e. the thickness of the inter-gate dielectric layer 104) between the two plates is calculated by the capacitor formula C=εS / 4πkd, where C represents the capacitor value, ε is a constant, S is the facing area of the capacitor plate, i.e. the area of the control gate polysilicon layer 105, k represents two electrostatic force constants, and d represents the distance between the two plates, i.e. the thickness of the inter-gate dielectric layer 104.

[0057] Correspondingly, the embodiment also provides a capacitor test structure of a flash memory device, which is prepared by using the preparation method in any of the above-mentioned schemes. Specifically, the capacitor test structure is formed in the capacitor test area B of the semiconductor structure 100, and includes an upper plate and a lower plate. The floating gate polysilicon layer 103 and the oxide layer with a certain thickness on the surface of the floating gate polysilicon layer 103 serve as the lower plate of the capacitor test structure, and the control gate polysilicon layer 105 serves as the upper plate of the capacitor test structure.

[0058] In summary, the capacitor test structure of a flash memory device and the preparation method thereof can form the peripheral polysilicon layer in the peripheral device area before the internal structure (semiconductor structure) of the flash memory device is completed, form the memory device unit in the memory device area, and then form the capacitor test structure in the capacitor test area and the peripheral polysilicon gate in the peripheral device area. The capacitor test structure is formed by the above-mentioned method to realize the measurement of the thickness of the inter-gate dielectric layer. Moreover, the capacitor test structure is formed by the above-mentioned method without the need of additional masks, so that the process steps are reduced and the process cost is saved. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0059] The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a capacitance test structure for a flash memory device, characterized in that, The method comprises: Step 1) providing a semiconductor structure, the semiconductor structure is divided into a memory device area, a capacitance test area and a peripheral device area, and the semiconductor structure comprises a substrate and a floating gate oxide layer, a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer formed on the substrate in sequence; Step 2) removing the floating gate polysilicon layer, the inter-gate dielectric layer, the control gate polysilicon layer and the floating gate oxide layer formed in the peripheral device area to expose the substrate, and forming a peripheral gate oxide layer and a peripheral gate polysilicon layer on the surface thereof; Step 3) etching the floating gate polysilicon layer, the inter-gate dielectric layer and the control gate polysilicon layer formed in the memory device area to form a memory device unit, and the memory device unit and the capacitance test area have a spacing therebetween; Step 4) etching the peripheral gate polysilicon layer to form a peripheral polysilicon gate, and the peripheral polysilicon gate and the capacitance test area have a spacing therebetween, and simultaneously etching the control gate polysilicon layer with a preset width at the edge of the capacitance test area and the inter-gate dielectric layer with a preset thickness thereunder to form a lower plate of a capacitance test structure, at this time, the control gate polysilicon layer of the capacitance test area is an upper plate of the capacitance test structure.

2. The method of claim 1, wherein the method further comprises: The semiconductor structure comprises a word line polysilicon and a definition oxide layer, wherein the floating gate polysilicon layer, the inter-gate dielectric layer and the control gate polysilicon layer are formed on both sides of the word line polysilicon, and the definition oxide layer is formed on the surface of the control gate polysilicon layer and the word line polysilicon in the memory device area, for defining the range of the control gate.

3. The method of claim 1, wherein the method further comprises: The semiconductor structure further comprises a shallow trench isolation structure for isolating the memory device area, the capacitance test area and the peripheral device area.

4. The method of claim 1, wherein the method further comprises: Before step 2) is performed, the method comprises a step of forming a hard mask layer on the surface of the control gate polysilicon layer, which is used to protect the memory device area and the capacitance test area when step 2) is performed.

5. The method of claim 4, wherein the method further comprises: Before step 3) is performed, the method comprises a step of removing the hard mask layer.

6. The method of claim 1, wherein the method further comprises: In step 4), the control gate polysilicon layer with a preset width near the memory device area and the inter-gate dielectric layer with a preset thickness thereunder of the capacitance test area are etched to form the lower plate of the capacitance test structure.

7. The method of claim 6, wherein the method further comprises: Before step 4) is performed, the method comprises a step of forming a mask layer on the surface of the structure formed in step 3) and performing a patterning process thereon.

8. The method of claim 1, wherein the method further comprises: The method further comprises a step of forming a contact hole on the surface of the upper plate and the lower plate.

9. The method of claim 1, wherein the method further comprises: The inter-gate dielectric layer comprises an ONO structure, the ONO structure comprises a bottom oxide layer, an intermediate nitride layer and a top oxide layer, wherein the intermediate nitride layer is formed between the bottom oxide layer and the top oxide layer, at this time, in step 4), when the inter-gate dielectric layer with the preset thickness is etched, the top oxide layer and the intermediate nitride layer are etched and removed and stopped on the bottom oxide layer.

10. The method of claim 1, wherein the method further comprises: The intergate dielectric layer comprises an oxide layer, and in step 4), the intergate dielectric layer of the preset thickness is etched, and the intergate dielectric layer is not etched completely.

11. A capacitance test structure for a flash memory device, comprising: The capacitor test structure of the flash memory device is prepared by the preparation method in any one of claims 1-10.

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