Packaging structure, method for manufacturing packaging structure, and electronic product

Abstract

The application discloses a packaging structure, a preparation method of the packaging structure and electronic products. The packaging structure comprises a packaging assembly, a stacking assembly and a uniform heating assembly. The packaging assembly comprises a substrate and a packaging layer connected with each other. The stacking assembly comprises a first stacking module. The first stacking module comprises at least two first chips stacked in the packaging layer from the side close to the substrate to the direction away from the substrate. In the first stacking module, one first chip close to the substrate is connected with the substrate, and the rest of the first chips are connected with the substrate through first leads arranged in the packaging layer. The uniform heating assembly comprises a uniform heating layer arranged in the packaging layer. A uniform heating layer is arranged between any two adjacent first chips. The packaging structure of the application stacks the first chips, arranges the uniform heating layer between any two adjacent first chips, and encapsulates in the packaging layer, so as to ensure the heat dissipation of the first chips, and meanwhile, the overall structure size is small, the occupied space is small, and the mounting is simple.

Description

Technical Field

[0001] This invention relates to the field of electronic product technology, and in particular to a packaging structure, a method for preparing the packaging structure, and an electronic product. Background Technology

[0002] With the development of technology, many electronic products are gradually moving towards miniaturization and integration, and the internal circuits of electronic products are also becoming more modular. Current semiconductor packaging technology typically packages some components together on one side of a substrate, with the entire packaged structure housed within the electronic product. However, as electronic products become increasingly functional, the number and types of chips required also increase, making mounting complex. Furthermore, the heat generated by the chips necessitates heat dissipation, resulting in a larger footprint and hindering further optimization and improvement in the miniaturization and integration of electronic products.

[0003] In view of the above-mentioned defects, it is necessary to provide a new packaging structure, a method for preparing the packaging structure, and an electronic product. Summary of the Invention

[0004] The main objective of this invention is to provide a packaging structure, a method for preparing the packaging structure, and an electronic product, aiming to solve the problem that electronic products with multiple functions require a large number of chips and heat dissipation, resulting in complex mounting and large space occupation.

[0005] To achieve the above objectives, the packaging structure proposed in this invention includes:

[0006] Packaging components, including interconnected substrates and packaging layers;

[0007] A stacking assembly includes a first stacking module, the first stacking module including at least two first chips disposed within the encapsulation layer and stacked sequentially from the side closest to the substrate to the side furthest from the substrate; in the first stacking module, one first chip closest to the substrate is connected to the substrate, and the remaining first chips are connected to the substrate through a first lead disposed within the encapsulation layer.

[0008] The heat dissipation assembly includes a heat dissipation layer disposed within the encapsulation layer, and a heat dissipation layer is disposed between any two adjacent first chips.

[0009] Preferably, the stacking assembly further includes a second stacking module spaced apart from the first stacking module along a first direction. The second stacking module includes at least two second chips disposed within the encapsulation layer and stacked sequentially from the side closest to the substrate to the side furthest from the substrate. In the second stacking module, one second chip closest to the substrate is connected to the substrate, and the remaining second chips are connected to the first chips stacked in the same layer via second leads disposed within the encapsulation layer.

[0010] Preferably, the stacking height of the second stacking module is higher than the stacking height of the first stacking module.

[0011] Preferably, the encapsulation layer includes a plurality of sub-encapsulation layers stacked sequentially, the number of the sub-encapsulation layers being consistent with the number of the second chips and configured in a one-to-one correspondence, the sub-encapsulation layers having a first step and a second step that are interconnected, the first chip being disposed in the first step of the corresponding sub-encapsulation layer, and the second chip being disposed in the second step of the corresponding sub-encapsulation layer.

[0012] Preferably, a heat dissipation layer is provided between any two adjacent second chips.

[0013] Preferably, the number of the first stacking modules is multiple, and the multiple first stacking modules are spaced apart within the encapsulation layer along the second direction; and / or, the number of the second stacking modules is multiple, and the multiple second stacking modules are spaced apart within the encapsulation layer along the second direction, the second direction being perpendicular to the first direction.

[0014] Preferably, the packaging structure further includes a photosensitive component, the photosensitive component including a photosensitive chip connected to the substrate, the photosensitive chip being disposed within the packaging layer and spaced apart from the first stacked module, the photosensitive chip having a photosensitive area exposed in the packaging layer.

[0015] Preferably, there are multiple photosensitive chips arranged around the outer periphery of the stacked assembly.

[0016] Preferably, the packaging structure further includes a shielding component, the shielding component including a first shielding layer and a second shielding layer disposed within the packaging layer, the second shielding layer being disposed around the outer periphery of the stacked assembly and connected to the substrate, the first shielding layer and the second shielding layer being connected to the side of the second shielding layer away from the substrate, the first shielding layer and the second shielding layer forming a receiving space for accommodating the stacked assembly.

[0017] In addition, to achieve the above objectives, the present invention also proposes a method for preparing an encapsulation structure, the method comprising the following steps:

[0018] A first chip is mounted on the substrate;

[0019] A heat dissipation layer is attached to the side of the first chip that is away from the substrate;

[0020] The first chip and the heat dissipation layer are encapsulated to form a packaging layer;

[0021] Another of the first chips is mounted on the side of the heat spreader away from the substrate;

[0022] Another of the first chips is connected to the substrate via a first lead;

[0023] If there are two first chips, the other first chip and the first lead are encapsulated to form another encapsulation layer;

[0024] If the number of the first chip is greater than two, another heat spreader is mounted on the side of the other first chip away from the substrate; the other first chip, the other heat spreader, and the first lead are encapsulated to form another encapsulation layer; the steps of mounting another first chip on the side of the heat spreader away from the substrate and subsequent steps are repeated until the mounting of the last first chip is completed, and the last first chip and the first lead are encapsulated to form the last encapsulation layer.

[0025] In addition, to achieve the above objectives, the present invention also proposes an electronic product, the electronic product comprising a housing and an encapsulation structure as described above disposed within the housing.

[0026] In the technical solution of this invention, the packaging structure includes a packaging component, a stacking component, and a heat dissipation component. The packaging component includes a substrate and a packaging layer connected to each other. The stacking component includes a first stacking module, which includes at least two first chips disposed within the packaging layer and stacked sequentially from the side closest to the substrate to the side furthest from the substrate. In the first stacking module, one first chip closest to the substrate is connected to the substrate, and the remaining first chips are connected to the substrate through first leads disposed within the packaging layer. The heat dissipation component includes a heat dissipation layer disposed within the packaging layer, and a heat dissipation layer is disposed between any two adjacent first chips. The packaging structure of this invention reduces the space occupied by the first chips by stacking at least two first chips within the packaging layer. Furthermore, by providing a heat dissipation layer within the packaging layer and between any two adjacent first chips, each first chip can dissipate heat uniformly through the heat dissipation layer in contact with it. This allows the packaging structure to ensure heat dissipation for each first chip while maintaining a small overall size, occupying little space, and being easy to mount. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0028] Figure 1 This is a cross-sectional schematic diagram of the packaging structure in one embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0036] Figure 9 This is a schematic diagram of the packaging structure during fabrication in one embodiment of the present invention;

[0037] Figure 10 This is a schematic flowchart of a method for preparing an encapsulation structure according to an embodiment of the present invention.

[0038] Explanation of icon numbers:

[0039] label name label name 1 Encapsulation components 22 Second stacking module 11 substrate 221 Second chip 111 conductive components 222 Second lead 12 Encapsulation layer 23 Heat exchanger 121 Sub-encapsulation layer 3 Light sensor components 1211 First step 31 optical sensor chip 1212 Second step 311 Light-sensitive area 2 Stacked components 4 Shielding components 21 First stacking module 41 First shielding layer 211 First chip 42 Second shielding layer 212 First lead

[0040] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0042] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0043] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0044] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0045] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0046] This invention proposes a packaging structure, a method for preparing the packaging structure, and an electronic product, aiming to solve the problem that electronic products with multiple functions require a large number of components and heat dissipation, resulting in complex mounting and large space occupation.

[0047] Please combine Figure 1 and Figure 9 The packaging structure includes a packaging component 1, a stacking component 2, and a heat dissipation component. The packaging component 1 includes a substrate 11 and a packaging layer 12 that are interconnected. The stacking component 2 includes a first stacking module 21. The first stacking module 21 includes at least two first chips 211 disposed in the packaging layer 12 and stacked sequentially from the side closest to the substrate 11 to the side away from the substrate 11. In the first stacking module 21, one first chip 211 close to the substrate 11 is connected to the substrate 11, and the remaining first chips 211 are connected to the substrate 11 through a first lead 212 disposed in the packaging layer 12. The heat dissipation component includes a heat dissipation layer 23 disposed in the packaging layer 12, and a heat dissipation layer 23 is disposed between any two adjacent first chips 211.

[0048] The packaging structure of this invention can be mainly applied to smart wearable products or other scenarios requiring optical signal sensing and processing. The packaging structure stacks at least two first chips 211 to form a first stacked module 21. A heat dissipation layer 23 is provided between any two adjacent first chips 211 to dissipate excess heat caused by the stacking of the first chips 211, thereby increasing the overall heat dissipation performance of the packaging structure. The first stacked module 21 and the heat dissipation layer 23 are encapsulated together in a packaging layer 12. The packaging layer 12 prevents external dust, water droplets, etc., from interfering with the stacked assembly 2, thus protecting the stacked assembly 2. The packaging layer 12 can be plastic-encapsulated, obtained through mold filling, and connected to an external circuit board via a substrate 11. The packaging structure of the present invention reduces the space occupied by the first chips 211 by stacking at least two first chips 211 within the packaging layer 12. Furthermore, a heat dissipation layer 23 is provided within the packaging layer 12. By placing the heat dissipation layer 23 between any two adjacent first chips 211, each first chip 211 can dissipate heat uniformly through the heat dissipation layer 23 in contact with it. This allows the packaging structure to ensure heat dissipation for each first chip 211 while maintaining a small overall size, minimal space occupation, and easy mounting. Any two first chips 211 among the plurality of first chips 211 can be the same or different. The first chips 211 can be audio controllers, memory, MEMS (Micro-Electro-Mechanical Systems) chips, or ASIC (Integrated Circuit) chips, etc.

[0049] The heat spreader can be a VC (vapor chamber), a vacuum cavity with a finely structured inner wall, typically made of copper, filled with a phase change coolant. The bottom has a mesh-like structure similar to a screen. The VC heat spreader is positioned between two first chips 211, primarily addressing the problem of excessive heat accumulation at the interface between adjacent first chips 211 during chip stacking. Heat is transferred outwards via the silicon wafers above and below the heat spreader, upwards and downwards (towards the substrate). The VC heat spreader has a thermal conductivity of 2000-5000 W / m*K, effectively reducing the diffusion thermal resistance between the heat source and the heat sink, thus improving heat dissipation efficiency. Heat transfer is achieved through gas-liquid conversion. The specific principle is as follows: When a portion of the vapor chamber (evaporation end) comes into contact with the heat source, the water in that area rapidly absorbs heat and evaporates into water vapor. This water vapor automatically moves towards the area of ​​lower pressure. In the lower-temperature area (condensation end), it releases heat and condenses back into liquid water. The liquid water droplets fall onto the bottom mesh and, due to capillary action, flow towards the dry evaporation section, ultimately forming a self-circulation for heat transfer. Additionally, by creating a vacuum, the vaporization point of water is lowered, and its liquefaction point is raised, thus reducing the temperature required to activate the VC vapor chamber.

[0050] In one embodiment, the stacking assembly 2 further includes a second stacking module 22 that is spaced apart from the first stacking module 21 along a first direction. The second stacking module 22 includes at least two second chips 221 disposed within the encapsulation layer 12 and stacked sequentially from the side closest to the substrate 11 toward the side furthest from the substrate 11. In the second stacking module 22, one second chip 221 close to the substrate 11 is connected to the substrate 11, and the remaining second chips 221 are connected to the first chip 211 stacked in the same layer through a second lead 222 disposed within the encapsulation layer 12. To integrate more chips, the stacking assembly 2 further includes a second stacking module 22, which is spaced apart from the first stacking module 21 along a first direction. The second stacking module 22 includes at least two second chips 221 stacked sequentially from the side closest to the substrate 11 toward the side furthest from the substrate 11. In one embodiment, the number of second chips 221 is equal to the number of first chips 211, and the second chips 221 correspond one-to-one with the first chips 211. To reduce the number of connection leads between each chip and the substrate 11, the second chips 221 can be connected to the first chips 211 stacked in the same layer through corresponding second leads 222. To protect the second chips 221 and the second leads 222, the second chips 221 and the second leads 222 are encapsulated by an encapsulation layer 12. Any two second chips 221 among the plurality of second chips 221 can be the same or different. The second chips 221 can be audio controllers, memory, MEMS (microelectromechanical systems) chips, or ASIC (integrated circuit) chips, etc.

[0051] Furthermore, the stacking height of the second stacking module 22 is higher than that of the first stacking module 21. The higher stacking height of the second stacking module 22 allows the second lead 222 on the second stacking module 22 to be separated from the first lead 212 on the first stacking module 21, making it less likely for them to cross.

[0052] In another embodiment, the encapsulation layer 12 includes a plurality of sub-encapsulation layers 121 stacked sequentially. The number of sub-encapsulation layers 121 is the same as the number of second chips 221 and they are arranged in a one-to-one correspondence. The sub-encapsulation layers 121 are provided with interconnected first steps 1211 and second steps 1212. The first chip 211 is disposed in the first step 1211 of the corresponding sub-encapsulation layer 121, and the second chip 221 is disposed in the second step 1212 of the corresponding sub-encapsulation layer 121. To obtain an encapsulation layer 12 with better process performance, a stepped structure can be provided on each sub-encapsulation layer 121 of the encapsulation layer 12 to reduce the impact of the mold flow. An encapsulation layer 12 with less mold flow impact has better structural performance. By sequentially molding, layer by layer of plastic encapsulation is obtained, and multiple sub-encapsulation layers 121 are stacked sequentially. The sub-encapsulation layers 121 are combined with the first chip 211 and the second chip 221. For example, after stacking the first chip 211 and the second chip 221, a plastic encapsulation is performed. The stacking heights of the first chip 211 and the second chip 221 are different, thereby obtaining the first step 1211 and the second step 1212. The first lead 212 of the first chip 211, which is far away from the substrate 11, and the second lead 222 of the second chip 221, which is far away from the substrate 11, can be separated from each other due to the height difference, effectively reducing the risk of short circuit caused by lead crossing and enhancing reliability.

[0053] In another embodiment, a heat dissipation layer 23 is provided between any two adjacent second chips 221. Providing a heat dissipation layer 23 between any two adjacent second chips 221 can dissipate excess heat caused by the stacking of the second chips 221, thereby increasing the overall heat dissipation performance of the package structure.

[0054] Furthermore, to achieve high integration of electronic products, in one embodiment, there are multiple first stacking modules 21, which are spaced apart along the second direction within the encapsulation layer 12. Multiple first stacking modules 21 can be spaced apart along the second direction in the encapsulation structure simultaneously. The number of first stacking modules 21 can be 2, 3, 4, etc., depending on actual development needs.

[0055] In another embodiment, there are multiple second stacked modules 22, which are spaced apart within the encapsulation layer 12 along a second direction perpendicular to the first direction. Multiple second stacked modules 22 can be simultaneously arranged in the encapsulation structure along the second direction, and the number of second stacked modules 22 can be 2, 3, 4, etc., depending on actual development needs. In other embodiments, multiple first stacked modules 21 and multiple second stacked modules 22 can also be simultaneously arranged in the encapsulation structure along the second direction, i.e., spaced apart. It should be noted that the number and arrangement of the first stacked modules 21 and the second stacked modules 22 are not limited to the above embodiments and can also be staggered, etc.

[0056] Furthermore, the packaging structure also includes a photosensitive component 3, which includes a photosensitive chip 31 connected to the substrate 11. The photosensitive chip 31 is disposed within the packaging layer 12 and spaced apart from the first stacked module 21. The photosensitive chip 31 has a photosensitive area 311 that exposes the packaging layer 12. The photosensitive chip 31 of the photosensitive component 3 is packaged within the packaging layer 12. This allows both the photosensitive chip 31 and the first chip 211 to be packaged within the packaging structure, resulting in a smaller footprint and easier mounting.

[0057] Furthermore, in the above embodiments, there are multiple photosensitive chips 31, which are arranged around the outer periphery of the stacked assembly 2. To meet the functional requirements of various electronic products, the number of photosensitive chips 31 in the package structure can be multiple, such as 2, 3, 4, 5, etc. During mounting, multiple photosensitive chips 31 can be arranged at intervals on the outer periphery of the stacked assembly 2, and the photosensitive chips 31 can be arranged separately to prevent optical path interference. This method can be applied to wearable module products.

[0058] In one embodiment, the encapsulation structure further includes a shielding component 4, which includes a first shielding layer 41 and a second shielding layer 42 disposed within the encapsulation layer 12. The second shielding layer 42 is disposed around the outer periphery of the stacked assembly 2 and connected to the substrate 11. The first shielding layer 41 and the second shielding layer 42 are connected to the side away from the substrate 11, and the first shielding layer 41 and the second shielding layer 42 form a receiving space for accommodating the stacked assembly 2. When the stacked assembly 2 needs to be shielded, the shielding component 4 can be provided. The shielding component 4 includes a first shielding layer 41 and a second shielding layer 42. The second shielding layer 42 can be obtained by laser-drilling grooves and filling the grooves with silver paste, embedding the shielding structure into the encapsulation layer 12. At the same time, an electromagnetic shielding film such as the first shielding layer 41 is added to the side of the second shielding layer 42 away from the first shielding layer 41 to improve the electromagnetic shielding capability of the encapsulation structure.

[0059] Furthermore, a plurality of conductive elements 111 are provided on the side of the substrate 11 away from the encapsulation layer 12. The photosensitive chip 31 is connected to an external circuit board through some of the conductive elements 111, and the first chip 211 is connected to an external circuit board through another portion of the conductive elements 111. The conductive elements 111 on the side of the substrate 11 away from the encapsulation layer 12 are multiple and arranged in an array, which can be a multi-row, multi-column array or a circular array. The photosensitive chip 31 is electrically connected to the external circuit board through some of the conductive elements 111, and the first chip 211 is electrically connected to the external circuit board through another portion of the conductive elements 111. The conductive elements 111 can be electrically connected to the external circuit board through surface contact, line contact, or point contact. Solder balls or solder joints are provided on the conductive elements 111 and fixed by soldering to ensure the reliability of the connection between the substrate 11 and the external circuit board.

[0060] In addition, the present invention also proposes a method for preparing a packaging structure, the method comprising the following steps:

[0061] S10, a first chip is mounted on the substrate;

[0062] S20, a heat dissipation layer is attached to the side of the first chip away from the substrate;

[0063] S30, the first chip and the heat dissipation layer are encapsulated to form a packaging layer;

[0064] S40, another first chip is attached to the side of the heat dissipation layer away from the substrate;

[0065] S50, another of the first chips is connected to the substrate via a first lead;

[0066] S60, if there are two first chips, the other first chip and the first lead are encapsulated to form another encapsulation layer;

[0067] S70, if the number of the first chips is greater than two, another heat dissipation layer is attached to the side of another first chip away from the substrate; the other first chip, the other heat dissipation layer and the first lead are encapsulated to form another encapsulation layer; the step of attaching another first chip to the side of the heat dissipation layer away from the substrate and the subsequent steps are repeated until the last first chip is attached, and the last first chip and the first lead are encapsulated to form the last encapsulation layer.

[0068] In one embodiment, please refer to the appendix. Figures 1 to 9 The method for manufacturing the packaging structure of the present invention is as follows:

[0069] Please refer to the appendix. Figure 2 The first chip 211, the second chip 221, and the photosensitive chip 31 are respectively mounted onto the substrate 11 using SMT; please refer to the attached document. Figure 3 Phase change heat dissipation structures are respectively mounted on the first chip 211 and the second chip 221; please refer to the attached diagram. Figure 4 The first chip 211, the second chip 221, and the photosensitive chip 31 are encapsulated in an irregular shape to form a first sub-encapsulation layer 121. The height of the first chip 211 is greater than the height of the second chip 221. After the irregular encapsulation, a first step 1211 is formed at the first chip 211, and a second step 1212 is formed at the second chip 221. Please refer to the attached diagram. Figure 5 To fabricate the electromagnetic shielding component 4, grooves can be machined along the outer periphery of the stacked component 2 using a laser, and then filled with silver paste to obtain the second shielding layer 42; please refer to the attached document. Figure 6 Continue stacking and mounting the first chip 211 on top of the first chip 211, and then stacking and mounting the second chip 221 on top of the second chip 221, exposing the pads of the first chip 211 and the second chip 221 for subsequent wiring; please refer to the attached document. Figure 7 The first chip 211, located away from the substrate 11, is connected to the substrate 11 via a first lead 212, and the second chip 221, also located away from the substrate 11, is connected to the substrate 11 via a second lead 222. Alternatively, the first chip 211 can be connected to the second chip 221, located away from the substrate 11, via the first lead 212. Please refer to the attached diagram. Figure 8 Another photosensitive chip 31 is mounted on the substrate 11. This photosensitive chip 31 and the previously packaged photosensitive chip 31 are located on opposite sides of the stacked assembly 2. Please refer to the attached diagram. Figure 9 The photosensitive film assembly, the first chip 211 and the second chip 221 away from the substrate 11 are then encapsulated to form another sub-encapsulation layer 121; please refer to the attached diagram. Figure 1 The electromagnetic shielding component 4 is then fabricated. Grooves are machined along the outer periphery of the stacked component 2 using a laser, and these grooves are filled with silver paste to create a second shielding layer 42 on the sub-encapsulation layer 121. A first shielding layer 41, in the form of an electromagnetic shielding film, is then attached to the side of the cover sub-encapsulation layer 121 away from the substrate 11, and the electromagnetic shielding film is connected to the second shielding layer 42. Connections between the stacked chips are achieved through SMT, molding, wire bonding, etc., eliminating the need for other expensive packaging methods such as TSV processes, resulting in low process costs.

[0070] Furthermore, this invention also proposes an electronic product, which includes a housing and a packaging structure as described above disposed within the housing. The specific structure of the packaging structure in this electronic product is as described in the above embodiments. Since this electronic product adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here. The electronic product may be a TWS (True Wireless Stereo) headset, microphone, watch, or fitness tracker, etc.

[0071] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: Packaging components, including interconnected substrates and packaging layers; A stacking assembly includes a first stacking module, the first stacking module including at least two first chips disposed within the encapsulation layer and stacked sequentially from the side closest to the substrate to the side furthest from the substrate; in the first stacking module, one first chip closest to the substrate is connected to the substrate, and the remaining first chips are connected to the substrate through a first lead disposed within the encapsulation layer. A heat dissipation assembly includes a heat dissipation layer disposed within the encapsulation layer, and a heat dissipation layer is disposed between any two adjacent first chips; The stacking assembly further includes a second stacking module spaced apart from the first stacking module along a first direction. The second stacking module includes at least two second chips disposed within the encapsulation layer and stacked sequentially from the side closest to the substrate to the side furthest from the substrate. The stacking height of the second stacking module is higher than the stacking height of the first stacking module. In the second stacking module, one second chip closest to the substrate is connected to the substrate, and the remaining second chips are connected to the first chips stacked in the same layer through second leads disposed within the encapsulation layer. The encapsulation layer includes a plurality of sub-encapsulation layers stacked sequentially. The number of sub-encapsulation layers is the same as the number of the second chips and they are arranged in a one-to-one correspondence. Each sub-encapsulation layer has a first step and a second step that are interconnected. The first chip is disposed in the first step of the corresponding sub-encapsulation layer, and the second chip is disposed in the second step of the corresponding sub-encapsulation layer.

2. The packaging structure as described in claim 1, characterized in that, A heat dissipation layer is provided between any two adjacent second chips.

3. The packaging structure as described in claim 1, characterized in that, The number of first stacked modules is multiple, and the multiple first stacked modules are spaced apart within the encapsulation layer along a second direction; and / or, the number of second stacked modules is multiple, and the multiple second stacked modules are spaced apart within the encapsulation layer along a second direction, the second direction being perpendicular to the first direction.

4. The packaging structure as described in any one of claims 1 to 3, characterized in that, The packaging structure further includes a photosensitive component, which includes a photosensitive chip connected to the substrate. The photosensitive chip is disposed within the packaging layer and spaced apart from the first stacked module. The photosensitive chip has a photosensitive area that is exposed in the packaging layer.

5. The packaging structure as described in claim 4, characterized in that, The number of the photosensitive chips is multiple, and the multiple photosensitive chips are arranged around the outer periphery of the stacked component.

6. The packaging structure as described in any one of claims 1 to 3, characterized in that, The packaging structure further includes a shielding component, which includes a first shielding layer and a second shielding layer disposed within the packaging layer. The second shielding layer is disposed around the outer periphery of the stacked assembly and connected to the substrate. The first shielding layer and the second shielding layer are connected to the side away from the substrate. The first shielding layer and the second shielding layer form a receiving space for accommodating the stacked assembly.

7. A method for preparing a packaging structure, characterized in that, The method for preparing the encapsulation structure includes the following steps: A first chip is mounted on a substrate, and a second chip is mounted on the substrate. A heat dissipation layer is attached to the side of the first chip that is away from the substrate, and a heat dissipation layer is attached to the side of the second chip that is away from the substrate. The first chip and its heat dissipation layer are encapsulated to form an encapsulation layer, and the second chip and its heat dissipation layer are encapsulated to form an encapsulation layer. The height of the first chip is greater than the height of the second chip. During encapsulation, a first step can be formed at the first chip and a second step can be formed at the second chip. Another of the first chips is mounted on the side of the heat spreader away from the substrate; Another of the first chips is connected to the substrate via a first lead; If there are two first chips, the other first chip and the first lead are encapsulated to form another encapsulation layer; If the number of the first chip is greater than two, another heat spreader is mounted on the side of the other first chip away from the substrate; the other first chip, the other heat spreader, and the first lead are encapsulated to form another encapsulation layer; the steps of mounting another first chip on the side of the heat spreader away from the substrate and subsequent steps are repeated until the mounting of the last first chip is completed, and the last first chip and the first lead are encapsulated to form the last encapsulation layer.

8. An electronic product, characterized in that, The electronic product includes a housing and an encapsulation structure as described in any one of claims 1 to 6 disposed within the housing.

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