Semiconductor structure and method of forming the same, and mask layout

Abstract

A semiconductor structure, a forming method thereof, and a mask layout, the forming method comprising: providing a substrate, including a substrate and a plurality of fins standing on the substrate, the fins extending along a first direction and being arranged in parallel along a second direction, the substrate including a plurality of memory cell regions, each of the memory cell regions including first and second sub-cell regions which are adjacent to each other and are center-symmetric, each of the first and second sub-cell regions including a pass transistor region, a pull-down transistor region and a pull-up transistor region, in each of the memory cell regions, a gate structure is formed on the substrate, the gate structure crossing the fins and covering part of the top and part of the sidewall of the fins; removing the gate structure at the boundary between the first and second sub-cell regions to form a partition opening, the partition opening being used to divide the gate structure in the second direction; and forming a partition structure in the partition opening. The partition openings are all formed on the same extension line and can be formed in the same step by using the same mask.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same, as well as a photomask layout. Background Technology

[0002] With the gradual development of semiconductor process technology, semiconductor process nodes are continuously shrinking in accordance with Moore's Law. To adapt to the shrinking process nodes and the development of highly integrated semiconductor devices, the critical dimensions of metal-oxide-semiconductor (MOS) devices are also constantly shrinking, with gate length and gate pitch also shrinking to even smaller dimensions. Correspondingly, the manufacturing process of semiconductor devices is also constantly being improved to meet people's requirements for device performance.

[0003] Currently, the gate structure forming process typically employs gate cutting technology to cut the strip gate. The cut gate corresponds to different transistors, which can improve the transistor integration density. In addition, when multiple gates are arranged in a row along the extension direction, gate cutting technology can precisely reduce the spacing in the mating direction between the disconnected gates after cutting (Gate Cut CD). Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, including a base and a plurality of fins protruding from the substrate, the fins extending along a first direction and arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction; the substrate including a plurality of memory cell regions, each memory cell region including a first sub-cell region and a second sub-cell region that are adjacent and centrally symmetrical, each of the first and second sub-cell regions including a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; a gate structure located on the substrate and spanning the plurality of fins along the second direction, the gate structure including a gate dielectric layer covering part of the sidewalls and part of the top of the fins, and a gate electrode layer located on the gate dielectric layer; and a partition structure located at the junction of the first and second sub-cell regions and penetrating the gate structure at the junction of the first and second sub-cell regions, the partition structure dividing the gate structure in the second direction.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of fins protruding from the substrate, the fins extending along a first direction and arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction; the substrate including a plurality of memory cell regions, the memory cell regions including adjacent and centrally symmetrical first sub-cell regions and second sub-cell regions, each of the first and second sub-cell regions including a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region; in the memory cell regions, a gate structure is formed on the substrate, the gate structure traversing the fins along the second direction and covering a portion of the top and a portion of the sidewalls of the fins; removing the gate structure located at the junction of the first and second sub-cell regions to form a partition opening, the partition opening being used to divide the gate structure in the second direction; and forming a partition structure in the partition opening.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this invention, the memory cell region includes a first sub-cell region and a second sub-cell region that are adjacent and centrally symmetrical. Both the first and second sub-cell regions include a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region. The partition structure is located at the boundary between the first and second sub-cell regions. Therefore, the partition structures are all arranged along the boundary line between the first and second sub-cell regions. Compared to a scheme where the partition structures are located at the boundary between the transmission gate transistor region and the pull-up transistor region in the first sub-cell region, and at the boundary between the transmission gate transistor region and the pull-up transistor region in the second sub-cell region, in this invention, for memory cell regions in the same column, the partition structures are all located on the same extension line. Therefore, the partition openings used to form the partition structures are also all located on the same extension line. Thus, the partition openings can be formed in the same step using the same photomask, simplifying the process flow, saving process costs, and improving process efficiency.

[0009] In the formation method provided by this embodiment of the invention, the memory cell region includes an adjacent and centrally symmetrical first sub-cell region and a second sub-cell region. Both the first and second sub-cell regions include a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region. By removing the gate structure located at the boundary between the first and second sub-cell regions to form an isolation port, the isolation ports are arranged along the boundary line between the first and second sub-cell regions. Compared to a scheme where the isolation ports are formed at the boundary between the transmission gate transistor region and the pull-up transistor region of the first sub-cell region, and at the boundary between the transmission gate transistor region and the pull-up transistor region of the second sub-cell region, in this embodiment of the invention, for memory cell regions in the same column, the isolation ports are all formed on the same extension line. Therefore, the isolation ports can be formed in the same step using the same photomask, simplifying the process flow, saving process costs, and improving process efficiency. Attached Figure Description

[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 8 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0013] Figures 16 to 17 This is the mask plate of the present invention. Figure 1 A schematic diagram of an embodiment. Detailed Implementation

[0014] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0015] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] Reference Figure 1 and Figure 2 , Figure 1 This is a top view of the fin and gate structure. Figure 2 for Figure 1 A cross-sectional view along the AA direction is provided, showing a substrate (not shown) including a substrate 10 and a plurality of fins 11 protruding from the substrate 10, the fins 11 being along a first direction (e.g., ...). Figure 1 Extending in the X direction and along the second direction (e.g., the middle X direction) and along the second direction (e.g.) Figure 1The substrate 10 includes multiple memory cell regions (not shown), each including a first sub-cell region 10A and a second sub-cell region 10B that are adjacent and centrally symmetrical. Both the first sub-cell region 10A and the second sub-cell region 10B include a transmission gate transistor region 10G, a pull-down transistor region 10D, and a pull-up transistor region 10U. In each memory cell region, a gate structure 20 is formed on the substrate 10. The gate structure 20 spans the fin 11 and covers part of the top and part of the sidewall of the fin 11. In the first sub-cell region 10A and the second sub-cell region 10B, a portion of the gate structure 20 located between the fin 11 of the transmission gate transistor region 10G and the fin 11 of the pull-up transistor region 10U is removed to form an isolation opening 21.

[0017] Reference Figure 3 and Figure 4 , Figure 3 Based on Figure 1 Top view, Figure 4 for Figure 3 Based on the cross-sectional view along the AA direction, a partition structure 22 is formed in the partition opening 21.

[0018] When forming the isolation opening 21, the isolation opening 21 is formed at the junction of the transmission gate transistor region 10G and the pull-up transistor region 10U in the first sub-unit region 10A, and at the junction of the transmission gate transistor region 10G and the pull-up transistor region 10U in the second sub-unit region 10B. Therefore, different photomasks are required to form the isolation opening 21 in the first sub-unit region 10A and the isolation opening 21 in the second sub-unit region 10B, respectively. The process is relatively complicated. Furthermore, with the continuous reduction of process nodes and the increasing integration of semiconductor structures, it is becoming increasingly difficult to separate the photolithographic pattern forming the isolation opening 21, thereby affecting the semiconductor structure formation process.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a base and a plurality of fins protruding from the substrate, the fins extending along a first direction and arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction; the substrate including a plurality of memory cell regions, each memory cell region including an adjacent and centrally symmetrical first sub-cell region and a second sub-cell region, each of the first and second sub-cell regions including a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; in each memory cell region, a gate structure is formed on the substrate, the gate structure traversing the fins along the second direction and covering a portion of the top and a portion of the sidewalls of the fins; removing the gate structure located at the junction of the first and second sub-cell regions to form a partition opening, the partition opening being used to divide the gate structure in the second direction; and forming a partition structure in the partition opening.

[0020] In the formation method provided by this embodiment of the invention, the memory cell region includes an adjacent and centrally symmetrical first sub-cell region and a second sub-cell region. Both the first and second sub-cell regions include a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region. By removing the gate structure located at the boundary between the first and second sub-cell regions to form an isolation port, the isolation ports are arranged along the boundary line between the first and second sub-cell regions. Compared to a scheme where the isolation ports are formed at the boundary between the transmission gate transistor region and the pull-up transistor region of the first sub-cell region, and at the boundary between the transmission gate transistor region and the pull-up transistor region of the second sub-cell region, in this embodiment of the invention, for memory cell regions in the same column, the isolation ports are all formed on the same extension line. Therefore, the isolation ports can be formed in the same step using the same photomask, simplifying the process flow, saving process costs, and improving process efficiency.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein, Figure 5 This is a top view of the fin and gate structure. Figure 6 for Figure 5 A top view of any memory cell area. Figure 7 Figure 6 is a cross-sectional view based on the AA direction.

[0023] The semiconductor structure includes: a substrate (not shown), including a substrate 101 and a plurality of fins 111 protruding from the substrate 101, the fins 111 being arranged along a first direction (e.g., Figure 5Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 5 The substrate includes a plurality of memory cell regions 101S, arranged in parallel along the Y-direction, with the second direction perpendicular to the first direction. Each memory cell region 101S includes a first sub-cell region 101A and a second sub-cell region 101B that are adjacent and centrally symmetrical. Both the first sub-cell region 101A and the second sub-cell region 101B include a transmission gate transistor region 101G, a pull-down transistor region 101D, and a pull-up transistor region 101U. A gate structure 201 is located on the substrate and spans the plurality of fins 111 along the second direction. The gate structure 201 includes a gate dielectric layer 231 covering part of the sidewalls and part of the top of the fins 111, and a gate electrode layer 241 located on the gate dielectric layer 231. A partition structure 221 is located at the junction of the first sub-cell region 101A and the second sub-cell region 101B and extends through the gate structure 221 at the junction of the first sub-cell region 101A and the second sub-cell region 101B. The gate structure 201 is divided in the second direction.

[0024] The substrate provides the basis for the process operation of forming the semiconductor structure.

[0025] In this embodiment, the substrate includes a substrate 101, and the material of the substrate 101 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0026] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the fin 111 is used to provide the channel of the fin field-effect transistor.

[0027] In this embodiment, the fin 111 and the substrate 101 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0028] In this embodiment, the material of the fin 111 is the same as the material of the substrate 101, and the material of the fin 111 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0029] In this embodiment, the substrate further includes an isolation layer 121, which covers part of the sidewall of the fin 111. The isolation layer 121 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 121 is usually formed between NMOS transistors and PMOS transistors.

[0030] In this embodiment, the material of the isolation layer 121 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0031] In this embodiment, the semiconductor structure includes an SRAM device, which includes a plurality of memory cell regions 101S.

[0032] Specifically, in an SRAM device, multiple memory cell regions 101S are arranged in a matrix along a first direction and a second direction. In the matrix arrangement of the multiple memory cell regions 101S, the first direction is parallel to the column direction of the multiple memory cell regions 101S, and the second direction is parallel to the row direction of the multiple memory cell regions 101S.

[0033] As an example, Figure 5 The diagram shows a 2×2 matrix arrangement of memory cell regions 101S, meaning there are four memory cell regions 101S, but the number of memory cell regions 101S contained in an SRAM device is not limited to four.

[0034] In this embodiment, the memory cell region 101S includes a centrally symmetrical first sub-cell region 101A and a second sub-cell region 101B. Both the first sub-cell region 101A and the second sub-cell region 101B include a transmission gate transistor region 101G, a pull-down transistor region 101D, and a pull-up transistor region 101U. Figure 6 Only the transmission gate transistor region 101G, pull-down transistor region 101D, and pull-up transistor region 101U in the first sub-unit region 101A are shown. The second sub-unit region 101B is symmetrical to the first sub-unit region 101A.

[0035] Specifically, the transmission gate transistor region 101G and the pull-down transistor region 101D are arranged adjacent to each other in the first direction, and the transmission gate transistor region 101G and the pull-down transistor region 101D are arranged adjacent to the pull-up transistor region 101U in the second direction.

[0036] The transmission gate transistor region 101G is used to form a transmission gate transistor, the pull-down transistor region 101D is used to form a pull-down transistor, and the pull-up transistor region 101U is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0037] In this embodiment, along the first direction, the fins 111 in the pull-up transistor region 101U in adjacent memory cell regions 101S are disconnected. Therefore, in the pull-up transistor region 101U, the end of the fin 111 located on the side of the gate transistor region 101G is recessed relative to the end of the fin 111 in the gate transistor region 101G, effectively preventing the fins 111 in the pull-up transistor region 101U in adjacent memory cell regions 101S from contacting each other in the first direction.

[0038] The gate structure 201 is used to control the opening and closing of the transistor's channel.

[0039] The gate dielectric layer 231 is used to isolate the gate electrode layer 241 from the fin 111.

[0040] The material of the gate dielectric layer 231 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0041] In this embodiment, the gate structure 201 is a metal gate structure. Therefore, the gate dielectric layer 231 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0042] It should be noted that the gate dielectric layer 231 may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the fin 111. Specifically, the material of the gate oxide layer may be silicon oxide.

[0043] In this embodiment, the gate electrode layer 241 is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0044] Specifically, the gate electrode layer 241 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0045] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0046] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 401 (e.g., Figure 6 As shown, the sidewall of the gate structure 201 is located on the substrate 101 on the side of the gate structure 201 and covers the sidewall of the gate structure 201.

[0047] The interlayer dielectric layer 401 serves to isolate adjacent devices and also provides a process platform for forming the gate structure 201.

[0048] The material of the interlayer dielectric layer 401 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0049] The isolation structure 221 is used to insulate the gate structures 201 from each other in the second direction, so that the electrical connection of each transistor in the SRAM device meets the design requirements.

[0050] In the semiconductor structure provided in this embodiment, the memory cell region 101S includes an adjacent and centrally symmetrical first sub-cell region 101A and a second sub-cell region 101B. Both the first sub-cell region 101A and the second sub-cell region 101B include a transmission gate transistor region 101G, a pull-down transistor region 101D, and a pull-up transistor region 101U. The partition structure 221 is located at the boundary between the first sub-cell region 101A and the second sub-cell region 101B. Therefore, the partition structures 221 are all arranged along the boundary line between the first sub-cell region 101A and the second sub-cell region 101B. Compared to schemes where the partition structures are located at the boundaries between the transmission gate transistor region and the pull-up transistor region of the first sub-cell region, and at the boundaries between the transmission gate transistor region and the pull-up transistor region of the second sub-cell region, in this embodiment, for memory cell regions 101S in the same column, the partition structure 221... Since all the openings are located on the same extension line, the openings used to form the partition structure 221 are also located on the same extension line. Therefore, the openings can be formed in the same step using the same photomask, which simplifies the process, saves process costs, and improves process efficiency.

[0051] In this embodiment, the partition structure 221 extends along the first direction and penetrates the interlayer dielectric layer 401 on both sides of the gate structure 201. In the first direction, the partition structures 221 located in the same column are an integral structure.

[0052] The isolation structure 221 extends along the first direction and penetrates the interlayer dielectric layer 401 on both sides of the gate structure 201, thereby increasing the size of the isolation structure 221 in the first direction. This is beneficial for obtaining a larger process window when forming the isolation structure 221, thereby reducing the process difficulty of forming the isolation structure 221 and forming a high-quality isolation structure 221. This is beneficial for ensuring that the isolation structure 221 completely isolates the gate structure 201 in the second direction.

[0053] Meanwhile, in the first direction, the partition structures 221 located in the same column are an integral structure, which helps to simplify the process of forming the partition structures 221 in the same column. By using a partition structure 221 that is connected as one unit, multiple gate structures 201 arranged along the first direction can be divided.

[0054] It should be noted that, along the second direction, the width d of the partition structure 221 (e.g., Figure 6 The width d of the partition structure 221 should not be too large or too small. If the width d of the partition structure 221 is too large, then along the second direction, the remaining gate structure 201 of the pull-up transistor region 101U extending from the fin 111 of the pull-up transistor region 101U to the partition structure 221 will be too small, thus affecting the coverage of the corresponding fin 111 by the gate structure 201 of the pull-up transistor region 101U, and consequently affecting the performance of the semiconductor structure. If the width d of the partition structure 221 is too small, then the insulation of the partition structure 221 will be poor, making it difficult to completely isolate the gate structure 201 in the second direction. Furthermore, since the partition structure 221 is formed in the partition opening, if the width d of the partition structure 221 is too small, then the width of the partition opening will also be too small. When forming the partition opening, the process window will be small, making it difficult to form a partition opening with precise position and size, thus affecting the formation of the partition structure 221 and the performance of the semiconductor structure. Therefore, in this embodiment, the width d of the partition structure 221 along the second direction is 10 nm to 50 nm.

[0055] The material of the isolation structure 221 has high hardness and density, thereby reducing the probability of the isolation structure 221 being damaged during the formation of the semiconductor structure, and thus ensuring the isolation performance of the isolation structure 221.

[0056] For example, during the formation of the semiconductor structure, after the gate structure 201 is formed, a portion of the gate structure 201 may be removed according to process requirements. By making the material of the isolation structure 221 have higher hardness and density, the probability of the isolation structure 221 being damaged during the removal of the gate structure 201 can be effectively reduced, thereby improving the integrity of the isolation structure 221.

[0057] Therefore, the material of the partition structure 221 includes a nitrogen-containing dielectric material. In this embodiment, the material of the partition structure 221 is silicon nitride. In other embodiments, depending on actual process requirements, the material of the partition structure can also be an oxygen-containing dielectric material, including silicon oxide.

[0058] In this embodiment, the semiconductor structure further includes a source / drain doped layer 301 located within the fins 111 on both sides of the gate structure 201.

[0059] The source / drain doped layer 301 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 301 is the same as the channel conductivity type of the corresponding transistor.

[0060] In this embodiment, in the memory cell region 101S, in the second direction, the source and drain doped layers 301 of the adjacent pull-up transistor region 101U are located on both sides of the isolation structure 221.

[0061] In this embodiment, the isolation structure 221 extends along the first direction and penetrates the interlayer dielectric layer 401 on both sides of the gate structure 201. In the first direction, the isolation structures 221 located in the same column are an integral structure. Therefore, in the second direction, the source and drain doped layers 301 of adjacent pull-up transistor regions 101U are respectively located on both sides of the isolation structure 221, so that the isolation structure 221 further isolates the source and drain doped layers 301 of adjacent pull-up transistor regions 101U from each other, thereby enhancing the isolation effect between the source and drain doped layers 301 of adjacent pull-up transistor regions 101U.

[0062] In this embodiment, the semiconductor structure further includes: a shared plug 501 located on top of the gate structure 201 of the pull-up transistor region 101U. In the same memory cell region 101S, the shared plug 501 in the first sub-cell region 101A extends into the pull-up transistor 101U of the second sub-cell region 101b and is connected to the source / drain doped layer 301 between adjacent gate structures 201. The shared plug 501 in the second sub-cell region 101B extends into the pull-up transistor region 101U of the first sub-cell region 101A and is connected to the source / drain doped layer 301 between adjacent gate structures 201.

[0063] In the memory cell region 101S, the pull-up transistors and pull-down transistors in the first sub-cell region 101A constitute a first inverter, and the pull-up transistors and pull-down transistors in the second sub-cell region 101B constitute a second inverter. The input terminal of the first inverter and the output terminal of the second inverter are connected to form a latch, and the input terminal of the second inverter and the output terminal of the first inverter are connected to form a latch. That is, the gate structure 201 of the pull-up transistor region 101U in the first sub-cell region 101A and the source / drain doped layer 301 of the pull-up transistor region 101U in the second sub-cell region 101B are electrically connected through a shared plug 501, and the gate structure 201 of the pull-up transistor region 101U in the second sub-cell region 101B and the source / drain doped layer 301 of the pull-up transistor region 101U in the first sub-cell region 101A are electrically connected through a shared plug 501.

[0064] Figures 8 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0065] Reference Figures 8 to 10 ,in, Figure 8 This is a top view of the fin and gate structure. Figure 9 This is a top view of any storage cell area in Figure 8. Figure 10 for Figure 9 A cross-sectional view along the AA direction is provided, showing a substrate (not shown) including a substrate 100 and a plurality of fins 110 protruding from the substrate 100, the fins 110 being aligned along a first direction (e.g., ...). Figure 8 Extending in the X direction and along the second direction (e.g., the middle X direction) and along the second direction (e.g.) Figure 8The substrate 100 includes a plurality of memory cell regions 100S, arranged in parallel in the Y direction, with the second direction perpendicular to the first direction. Each memory cell region 100S includes a first sub-cell region 100A and a second sub-cell region 100B that are adjacent and centrally symmetrical. Both the first sub-cell region 100A and the second sub-cell region 100B include a transmission gate transistor region 100G, a pull-down transistor region 100D, and a pull-up transistor region 100U. In each memory cell region 100S, a gate structure 200 is formed on the substrate 100. The gate structure 200 spans the fin 110 and covers part of the top and part of the sidewalls of the fin 110.

[0066] The substrate provides the basis for the process operation of forming the semiconductor structure.

[0067] In this embodiment, the substrate includes a substrate 100, and the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0068] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the fin portion 110 is used to provide the channel of the fin field-effect transistor.

[0069] In this embodiment, the fin 110 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0070] In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0071] In this embodiment, the substrate further includes an isolation layer 120, which covers part of the sidewall of the fin 110. The isolation layer 120 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 120 is usually formed between NMOS transistors and PMOS transistors.

[0072] In this embodiment, the material of the isolation layer 120 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0073] In this embodiment, the semiconductor structure includes an SRAM device, which includes multiple memory cell regions 100S.

[0074] Specifically, in an SRAM device, multiple memory cell regions 100S are arranged in a matrix along a first direction and a second direction. In the matrix arrangement of the multiple memory cell regions 100S, the first direction is parallel to the column direction of the multiple memory cell regions 100S, and the second direction is parallel to the row direction of the multiple memory cell regions 100S.

[0075] As an example, Figure 5 The diagram shows a 2×2 matrix arrangement of memory cell regions 100S, meaning there are four memory cell regions 100S, but the number of memory cell regions 100S contained in an SRAM device is not limited to four.

[0076] In this embodiment, the memory cell region 100S includes a centrally symmetrical first sub-cell region 100A and a second sub-cell region 100B. Both the first sub-cell region 100A and the second sub-cell region 100B include a transmission gate transistor region 100G, a pull-down transistor region 100D, and a pull-up transistor region 100U. Figure 6 The diagram only shows the transmission gate transistor region 100G, pull-down transistor region 100D, and pull-up transistor region 100U in the first sub-unit region 100A. The second sub-unit region 100B is symmetrical to the first sub-unit region 100A.

[0077] Specifically, the transmission gate transistor region 100G and the pull-down transistor region 100D are arranged adjacent to each other in the first direction, and the transmission gate transistor region 100G and the pull-down transistor region 100D are arranged adjacent to the pull-up transistor region 100U in the second direction.

[0078] The transmission gate transistor region 100G is used to form a transmission gate transistor, the pull-down transistor region 100D is used to form a pull-down transistor, and the pull-up transistor region 100U is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0079] In this embodiment, along the first direction, the fin 110 in the pull-up transistor region 100U in adjacent memory cell regions 100S is disconnected. Therefore, in the pull-up transistor region 100U, the end of the fin 110 located on the side of the gate transistor region 100G is recessed relative to the end of the fin 110 in the gate transistor region 100G, effectively preventing the fins 110 in the pull-up transistor region 100U in adjacent memory cell regions 100S from contacting each other in the first direction.

[0080] In this embodiment, during the step of providing the substrate, the gate structure 200 includes a device gate structure or a dummy gate structure. The device gate structure is used to control the turning on and off of the transistor channel, while the dummy gate structure is used to occupy space for forming the device gate structure.

[0081] In this embodiment, the gate structure 200 is a device gate structure. Therefore, after the device gate structure is formed, the gate is cut off. There is no need to consider the influence of the linewidth of the subsequently formed isolation opening along the second direction on the filling performance of the device gate structure. It is easier to set the linewidth of the isolation opening along the second direction more flexibly.

[0082] The gate structure 200 is used to control the opening and closing of the transistor's channel.

[0083] The gate dielectric layer 230 is used to isolate the gate electrode layer 240 from the fin 110.

[0084] The material of the gate dielectric layer 230 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0085] In this embodiment, the gate structure 200 is a metal gate structure. Therefore, the gate dielectric layer 230 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0086] It should be noted that the gate dielectric layer 230 may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the fin 110. Specifically, the material of the gate oxide layer may be silicon oxide.

[0087] In this embodiment, the gate electrode layer 240 is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0088] Specifically, the gate electrode layer 240 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0089] In other embodiments, the device gate structure may also be a polysilicon gate structure, depending on process requirements.

[0090] In this embodiment, during the step of providing the substrate, an interlayer dielectric layer 400 is further formed on the substrate 100 on the side of the gate structure 200, and the interlayer dielectric layer 400 covers the sidewall of the gate structure 200.

[0091] The interlayer dielectric layer 400 serves to isolate adjacent devices and also provides a process platform for forming the gate structure 200.

[0092] The material of the interlayer dielectric layer 400 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0093] In this embodiment, during the step of providing the substrate, an active drain doped layer 300 is also formed in the fins 110 on both sides of the gate structure 200.

[0094] The source / drain doped layer 300 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 300 is the same as the channel conductivity type of the corresponding transistor.

[0095] Reference Figure 11 and Figure 12 , Figure 11 For based on Figure 9 Top view, Figure 12 for Figure 11 Based on the cross-sectional view along the AA direction, the gate structure 200 located at the junction of the first sub-cell region 100A and the second sub-cell region 100B is removed to form an isolation opening 210, which is used to divide the gate structure 200 in the second direction.

[0096] In the formation method provided in this embodiment, the memory cell region 100S includes an adjacent and centrally symmetrical first sub-cell region 100A and a second sub-cell region 100B. Both the first sub-cell region 100A and the second sub-cell region 100B include a transmission gate transistor region 100G, a pull-down transistor region 100D, and a pull-up transistor region 100U. The gate structure 200 located at the boundary between the first sub-cell region 100A and the second sub-cell region 100B is removed to form an isolation port 210. The isolation ports 210 are all arranged along the boundary line between the first sub-cell region 100A and the second sub-cell region 100B. Compared to a scheme where the isolation ports are formed at the boundary between the transmission gate transistor region and the pull-up transistor region of the first sub-cell region, and at the boundary between the transmission gate transistor region and the pull-up transistor region of the second sub-cell region, in this embodiment, for memory cell regions 100S in the same column, the isolation ports 210 are all formed on the same extension line. Therefore, the isolation ports 210... The same photomask can be formed in the same step, which simplifies the process, saves process costs, and improves process efficiency.

[0097] By cutting off the gate structure 200 by forming the isolation opening 210, the integration density of the transistor can be improved, and the distance of the line end of the disconnected gate structure 200 can be reduced with high precision in the extension direction of the gate structure 200.

[0098] The partition opening 210 is used to provide space for the subsequent formation of the partition structure.

[0099] In this embodiment, after the device gate structure is formed, the gate is cut off. Therefore, there is no need to consider the influence of the linewidth dimension of the isolation opening 210 along the second direction on the filling performance of the device gate structure, and it is easier to set the linewidth dimension of the isolation opening 210 along the second direction more flexibly.

[0100] In this embodiment, the partition opening 210 is formed in the same process using the same photomask.

[0101] The partition opening 210 can be formed using the same photomask in the same process, which simplifies the process flow, saves process costs, and improves process efficiency.

[0102] In this embodiment, in the step of removing the gate structure 200 located at the junction of the first sub-cell region 100A and the second sub-cell region 100B to form the isolation opening 210, at the junction of the first sub-cell region 100A and the second sub-cell region 100B, the interlayer dielectric layer 400 located at the junction of the first sub-cell region 100A and the second sub-cell region 100B is also removed. The isolation opening 210 extends along the first direction and penetrates the interlayer dielectric layers 400 on both sides of the gate structure 200. In the first direction, the isolation openings 210 located in the same column are connected.

[0103] The isolation opening 210 extends along the first direction and penetrates the interlayer dielectric layer 400 on both sides of the gate structure 200, thereby increasing the size of the isolation opening 210 in the first direction. This is beneficial for obtaining a larger process window when forming the isolation opening 210, thereby reducing the process difficulty of forming the isolation opening 210 and forming a high-quality isolation opening 210. This is beneficial for ensuring that the isolation opening 210 completely isolates the gate structure 200 in the second direction.

[0104] Meanwhile, in the first direction, the partition openings 210 located in the same column are an integral structure, which helps to simplify the process of forming the partition openings 210 in the same column. By using a partition opening 210 that is connected as one unit, multiple gate structures 200 arranged along the first direction can be divided.

[0105] In this embodiment, during the step of forming the isolation opening 210, in the memory cell region 100S, in the second direction, the source and drain doped layers 300 of the adjacent pull-up transistor region 100U are respectively located on both sides of the isolation opening 210.

[0106] In this embodiment, the isolation opening 210 extends along the first direction and penetrates the interlayer dielectric layer 400 on both sides of the gate structure 200. In the first direction, the isolation openings 210 located in the same column are connected. Therefore, in the second direction, the source and drain doped layers 300 of adjacent pull-up transistor regions 100U are respectively located on both sides of the isolation opening 210. After the isolation structure is formed in the isolation opening, the isolation structure further isolates the source and drain doped layers 300 of adjacent pull-up transistor regions 100U from each other, thereby enhancing the isolation effect between the source and drain doped layers 300 of adjacent pull-up transistor regions 100U.

[0107] In this embodiment, the separation opening 210 is formed by a dry etching process.

[0108] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, the etching is more directional, which is beneficial to improving the opening size accuracy of the partition opening 210.

[0109] It should be noted that the width d of the isolation opening 210 along the second direction should not be too large or too small. If the width d of the isolation opening 210 is too large, then along the second direction, the remaining gate structure 200 of the pull-up transistor region 100U extending from the fin 110 of the pull-up transistor region 100U to the isolation opening 210 will be too small, thus affecting the coverage of the corresponding fin 110 by the gate structure 200 of the pull-up transistor region 100U, and consequently affecting the performance of the semiconductor structure. If the width d of the isolation opening 210 is too small, then the isolation opening 210 will be difficult to completely isolate the gate structure 200 in the second direction. Furthermore, if the width d of the isolation opening 210 is too small, the process window will be small when forming the isolation opening 210, making it difficult to form an isolation opening 210 with precise position and size, thereby affecting the formation of subsequent isolation structures and the performance of the semiconductor structure. Therefore, in this embodiment, the width d of the partition opening 210 along the second direction is 10nm to 50nm.

[0110] Reference Figure 13 and Figure 14 , Figure 13 For based on Figure 11 Top view, Figure 14 for Figure 13 Based on the cross-sectional view along the AA direction, a partition structure 220 is formed in the partition opening 210.

[0111] The isolation structure 220 is used to insulate the gate structures 200 from each other in the second direction, so that the electrical connection of each transistor in the SRAM device meets the design requirements.

[0112] In this embodiment, the partition structure 220 is formed by chemical vapor deposition.

[0113] The chemical vapor deposition process is simple and easy to operate, and has good filling capacity, which can form the high-quality partition structure 220.

[0114] Accordingly, in this embodiment, the width of the partition structure 220 along the second direction is 10 nm to 50 nm.

[0115] The material of the isolation structure 220 has high hardness and density, thereby reducing the probability of the isolation structure 220 being damaged during the formation of the semiconductor structure, and thus ensuring the isolation performance of the isolation structure 220.

[0116] For example, during the formation of the semiconductor structure, after the gate structure is formed, a portion of the gate structure may be removed according to process requirements. By making the material of the isolation structure 220 have high hardness and density, the probability of the isolation structure 220 being damaged during the removal of the gate structure can be effectively reduced, thereby improving the integrity of the isolation structure 220.

[0117] Therefore, the material of the partition structure 220 includes a nitrogen-containing dielectric material. In this embodiment, the material of the partition structure 220 is silicon nitride. In other embodiments, depending on actual process requirements, the material of the partition structure can also be an oxygen-containing dielectric material, including silicon oxide.

[0118] It should be noted that this embodiment uses the gate structure 200 as a device gate structure for illustration. In other embodiments, the gate structure can also be a pseudo-gate structure. Accordingly, after forming the pseudo-gate structure, a source / drain doped layer is formed; after forming the source / drain doped layer, before removing the pseudo-gate structure, the pseudo-gate structure located at the junction of the first sub-cell region and the second sub-cell region is removed to form a partition opening. The partition opening is used to divide the pseudo-gate structure in the second direction; a partition structure is formed in the partition opening; after forming the partition structure, the pseudo-gate structure is removed to form a gate opening; and a device gate structure is formed in the gate opening.

[0119] refer to Figure 15 , Figure 15 For based on Figure 13 According to the top view, after forming the partition structure 220, the forming method further includes: forming a shared plug 500 on top of the gate structure 200 of the pull-up transistor region 100U; in the same memory cell region 100S, the shared plug 500 in the first sub-cell region 100A extends into the pull-up transistor region 100U of the second sub-cell region 100B and is connected to the source / drain doped layer 300 between adjacent gate structures 200; the shared plug 500 in the second sub-cell region 100B extends into the pull-up transistor region 100U of the first sub-cell region 100A and is connected to the source / drain doped layer 300 between adjacent gate structures 200.

[0120] In the memory cell region 100S, the pull-up transistors and pull-down transistors in the first sub-cell region 100A constitute a first inverter, and the pull-up transistors and pull-down transistors in the second sub-cell region 100B constitute a second inverter. The input terminal of the first inverter and the output terminal of the second inverter are connected to form a latch, and the input terminal of the second inverter and the output terminal of the first inverter are connected to form a latch. That is, the gate structure 200 of the pull-up transistor region 100U in the first sub-cell region 100A and the source / drain doped layer 300 of the pull-up transistor region 100U in the second sub-cell region 100B are electrically connected through a shared plug 500.

[0121] Figure 16 and Figure 17 This is the mask plate of the present invention. Figure 1 A schematic diagram of the embodiment, Figure 17 for Figure 16 A schematic diagram of the mask layout for any memory cell region.

[0122] Reference Figure 16 and Figure 17 The mask layout includes multiple memory cell regions 102S. Each memory cell region 102S includes a centrally symmetrical first sub-cell region 102A and a second sub-cell region 102B. Both the first sub-cell region 102A and the second sub-cell region 102B include a transmission gate transistor region 102G, a pull-down transistor region 102D, and a pull-up transistor region 102U.

[0123] In this embodiment, the mask layout is used to form an SRAM device, which includes a plurality of memory cell regions 102S.

[0124] In an SRAM device, multiple memory cell regions 102S are arranged along a first direction (e.g., ...). Figure 16 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 16 The storage cells 102S are arranged in a matrix (as shown in the Y direction). In the matrix arrangement of the multiple storage cell areas 102S, the first direction is parallel to the column direction of the multiple storage cell areas 102S, and the second direction is parallel to the row direction of the multiple storage cell areas 102S.

[0125] As an example, Figure 16 The diagram shows a 2×2 matrix arrangement of memory cell regions 102S, meaning there are four memory cell regions 102S. However, the number of memory cell regions 102S contained in an SRAM device is not limited to four.

[0126] Specifically, the transmission gate transistor region 102G and the pull-down transistor region 102D are arranged adjacent to each other in the first direction, and the transmission gate transistor region 102G and the pull-down transistor region 102D are arranged adjacent to the pull-up transistor region 102U in the second direction.

[0127] The transmission gate transistor region 102G is used to form a transmission gate transistor, the pull-down transistor region 102D is used to form a pull-down transistor, and the pull-up transistor region 102U is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0128] Specifically, refer to Figure 17 The mask pattern includes: a first layer (not shown), including a fin pattern 112, the fin pattern 112 extending along a first direction and arranged parallel to a second direction, the second direction being perpendicular to the first direction.

[0129] The fin pattern 112 is used to form a fin, which is used to provide a channel for a transistor.

[0130] In this embodiment, along the first direction, the fins of the pull-up transistors 102U in adjacent memory cell regions 102S are disconnected from each other. Therefore, in the pull-up transistor transmission region 102U, the end of the fin pattern 112 located on the side of the transmission gate transistor region 102G is recessed relative to the end of the fin pattern 112 in the transmission gate transistor region 102G, effectively preventing the fins of the pull-up transistors 102U in adjacent memory cell regions 102S from contacting each other in the first direction.

[0131] In this embodiment, the mask layout further includes a second layer (not shown), located above the first layer. The second layer includes a gate pattern 202, which is orthogonal to the fin pattern 112. The gate pattern 202 extends along a second direction and is arranged parallel to the first direction.

[0132] The gate pattern 202 is used to form a gate structure.

[0133] In this embodiment, the second plate layer is located above the first plate layer, so in the semiconductor process, the gate structure is formed after the fins are formed.

[0134] In semiconductor manufacturing, the gate structure spans the fins in its region and covers part of the top and sidewalls of the fins. Therefore, the gate pattern 202 is orthogonal to the fin pattern 112 in its region. Specifically, when there are multiple fin patterns 112 in the region, one gate pattern 202 is orthogonal to multiple fin patterns 112.

[0135] In this embodiment, the mask layout further includes a third layer (not shown), located above the second layer. The third layer includes a gate segment pattern 222 located at the junction of the first sub-cell region 100A and the second sub-cell region 100B. The gate segment pattern 222 is orthogonal to the gate pattern 202.

[0136] The gate segment pattern 222 is used to define the cut-off position of the gate structure.

[0137] In the mask layout provided in this embodiment, the gate segment pattern 222 is located at the boundary between the first sub-cell region 102A and the second sub-cell region 102B. Therefore, the gate segment patterns 222 are all arranged along the boundary line between the first sub-cell region 102A and the second sub-cell region 102B. Compared to the scheme where the gate segment patterns are located at the boundary between the transmission gate transistor region and the pull-up transistor region of the first sub-cell region, and at the boundary between the transmission gate transistor region and the pull-up transistor region of the second sub-cell region, in this embodiment, for memory cell regions 102S in the same column, the gate segment patterns 222 are all located on the same extension line. Therefore, when forming the isolation opening, it can be formed in the same step using the same photomask, simplifying the process flow, saving process costs, and improving process efficiency.

[0138] In this embodiment, in the first direction, the gate segment pattern 222 spans across each of the memory cell regions 102S located in the same column.

[0139] The gate segment pattern 222 spans across each of the memory cell regions 102S located in the same column, thereby increasing the size of the gate segment pattern 222 in the first direction. This is beneficial for obtaining a larger process window when forming the isolation opening, thereby reducing the process difficulty of forming the isolation opening and forming a high-quality isolation structure. At the same time, in the first direction, it is beneficial for simplifying the process flow of forming the isolation opening in the same column. By using a single integrated isolation opening, multiple gate structures arranged along the first direction can be divided.

[0140] In this embodiment, the third layer is located above the second layer. Therefore, in the semiconductor process, after the gate structure is formed, the gate is cut off.

[0141] In this embodiment, the mask layout further includes a fourth layer (not shown), located above the first layer and below the second layer. The fourth layer includes source / drain patterns 302, which are located on the fin patterns 112 on both sides of the gate pattern 202.

[0142] The source / drain pattern 302 is used to form the source / drain doped layer.

[0143] In this embodiment, the fourth layer is located above the first layer and below the second layer. Therefore, in the semiconductor process, the source and drain doped layers are formed after the fins are formed and before the gate structure is formed.

[0144] In this embodiment, in the memory cell region 102S, in the second direction, the source-drain patterns 302 of the adjacent pull-up transistor region 102U are located on both sides of the gate slicing pattern 222.

[0145] In this embodiment, in the first direction, the gate segment pattern 222 spans across each of the memory cell regions 102S located in the same column. Therefore, in the second direction, the source and drain patterns 302 of adjacent pull-up transistor regions 102U are located on both sides of the gate segment pattern 222. Thus, in the semiconductor process, the formed isolation structure can further isolate the source and drain doped layers of adjacent pull-up transistor regions 102U, enhancing the isolation effect between the source and drain doped layers of adjacent pull-up transistor regions 102U.

[0146] In this embodiment, the mask layout further includes a fifth layer (not shown), located above the third layer. The fifth layer includes a shared plug pattern 502, which is located above the gate pattern 202 of the pull-up transistor region 102U. In the same memory cell region 102S, the shared plug pattern 502 in the first sub-cell region 102A extends into the pull-up transistor region 102U of the second sub-cell region 102B and is located above the source-drain pattern 302 between adjacent gate patterns 202. The shared plug pattern 502 in the second sub-cell region 102B extends into the pull-up transistor region 102U of the first sub-cell region 102A and is located above the source-drain pattern 302 between adjacent gate patterns 202.

[0147] The shared plug pattern 502 is used to form a shared plug. The gate structure of the pull-up transistor region 102U in the first sub-unit region 102A and the source / drain doped layer of the pull-up transistor region 102U in the second sub-unit region 102B are electrically connected through the shared plug. The gate structure of the pull-up transistor region 102U in the second sub-unit region 102B and the source / drain doped layer of the pull-up transistor region 102U in the first sub-unit region 102A are electrically connected through the shared plug.

[0148] In this embodiment, the fifth layer is located above the third layer. Therefore, in the semiconductor process, after the gate is cut off, a shared plug is formed.

[0149] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a substrate and a plurality of fins protruding from the substrate, the fins extending along a first direction and arranged parallel to a second direction, the second direction being perpendicular to the first direction, the substrate including a plurality of memory cell regions, the memory cell regions including adjacent and centrally symmetrical first sub-cell regions and second sub-cell regions, the first sub-cell regions and the second sub-cell regions each including a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region; A gate structure is located on the substrate and spans the plurality of fins along the second direction, the gate structure including a gate dielectric layer covering a portion of the sidewalls and a portion of the top of the fins, and a gate electrode layer located on the gate dielectric layer; A partition structure is located at the junction of the first sub-cell region and the second sub-cell region, and extends through the gate structure at the junction of the first sub-cell region and the second sub-cell region. The partition structure divides the gate structure in the second direction, wherein for memory cell regions in the same column, the partition structure is located on the same extension line.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an interlayer dielectric layer located on the substrate on the side of the gate structure and covering the sidewall of the gate structure; The partition structure extends along the first direction and penetrates the interlayer dielectric layer on both sides of the gate structure. In the first direction, the partition structures located in the same column are an integral structure.

3. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes: source and drain doped layers located within the fins on both sides of the gate structure; In the memory cell region, in the second direction, the source and drain doped layers adjacent to the pull-up transistor regions are located on both sides of the partition structure.

4. The semiconductor structure as described in claim 3, characterized in that, The semiconductor structure further includes: a shared plug located on top of the gate structure of the pull-up transistor region. In the same memory cell region, the shared plug in the first sub-cell region extends into the pull-up transistor of the second sub-cell region and is connected to the source / drain doped layer between adjacent gate structures. The shared plug in the second sub-cell region extends into the pull-up transistor region of the first sub-cell region and is connected to the source / drain doped layer between adjacent gate structures.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the partition structure includes a nitrogen-containing dielectric material or an oxygen-containing dielectric material. The nitrogen-containing dielectric material includes silicon nitride, and the oxygen-containing dielectric material includes silicon oxide.

6. The semiconductor structure as described in claim 1, characterized in that, Along the second direction, the width of the partition structure is 10 nm to 50 nm.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3, and the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a plurality of fins protruding from the substrate, the fins extending along a first direction and arranged parallel to a second direction perpendicular to the first direction, the substrate including a plurality of memory cell regions, the memory cell regions including adjacent and centrally symmetrical first sub-cell regions and second sub-cell regions, each of the first sub-cell regions and the second sub-cell region including a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region, in the memory cell regions, a gate structure is formed on the substrate, the gate structure traversing the fins along the second direction and covering a portion of the top and a portion of the sidewalls of the fins; The gate structure located at the junction of the first sub-cell region and the second sub-cell region is removed to form a partition opening, which is used to divide the gate structure in a second direction; A partition structure is formed in the partition opening, wherein for storage cell areas in the same column, the partition structures are all located on the same extension line.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the substrate, an interlayer dielectric layer is also formed on the substrate on the side of the gate structure, and the interlayer dielectric layer covers the sidewall of the gate structure; In the step of removing the gate structure located at the junction of the first sub-cell region and the second sub-cell region to form the isolation opening, at the junction of the first sub-cell region and the second sub-cell region, the interlayer dielectric layer located at the junction of the first sub-cell region and the second sub-cell region is also removed. The isolation opening extends along the first direction and penetrates the interlayer dielectric layers on both sides of the gate structure. In the first direction, the isolation openings located in the same column are connected.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, an active drain doped layer is also formed in the fins on both sides of the gate structure; In the step of forming the isolation opening, in the memory cell region, in the second direction, the source and drain doped layers of the adjacent pull-up transistor regions are respectively located on both sides of the isolation opening.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the isolation structure, the forming method further includes: forming a shared plug on top of the gate structure of the pull-up transistor region; in the same memory cell region, the shared plug in the first sub-cell region extends into the pull-up transistor region of the second sub-cell region and is connected to the source / drain doped layer between adjacent gate structures; the shared plug in the second sub-cell region extends into the pull-up transistor region of the first sub-cell region and is connected to the source / drain doped layer between adjacent gate structures.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The partition opening is formed using the same photomask in the same process.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the partition opening, a dry etching process is used to form the partition opening.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the partition structure, the partition structure is formed using a chemical vapor deposition process.

15. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the partition structure, the material of the partition structure includes a nitrogen-containing dielectric material or an oxygen-containing dielectric material, wherein the nitrogen-containing dielectric material includes silicon nitride, and the oxygen-containing dielectric material includes silicon oxide.

16. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the substrate, the gate structure includes a device gate structure or a pseudo-gate structure.

17. A photomask layout, characterized in that, include: Multiple memory cell regions, each memory cell region including a centrally symmetrical first sub-cell region and a second sub-cell region, each of the first sub-cell region and the second sub-cell region including a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region; The first layer includes fin graphics that extend along a first direction and are arranged parallel to a second direction, the second direction being perpendicular to the first direction; The second layer is located above the first layer. The second layer includes a gate pattern, which is orthogonal to the fin pattern. The gate pattern extends along a second direction and is arranged parallel to the first direction. The third layer is located above the second layer. The third layer includes a gate segment pattern located at the junction of the first sub-cell region and the second sub-cell region. The gate segment pattern is orthogonal to the gate pattern.

18. The mask layout as described in claim 17, characterized in that, In the first direction, the gate segment pattern spans across each of the memory cell regions located in the same column.

19. The mask layout as described in claim 18, characterized in that, The mask layout further includes: a fourth layer, located above the first layer and below the second layer, the fourth layer including source and drain patterns, the source and drain patterns being located on the fin patterns on both sides of the gate pattern; In the memory cell region, in the second direction, the source and drain patterns of the adjacent pull-up transistor regions are located on both sides of the gate slicing pattern.

20. The mask layout as described in claim 19, characterized in that, The mask layout further includes a fifth layer, located above the third layer. The fifth layer includes a shared plug pattern located above the gate pattern of the pull-up transistor region. Within the same memory cell region, the shared plug pattern in the first sub-cell region extends into the pull-up transistor region of the second sub-cell region and is located above the source-drain pattern between adjacent gate patterns. The shared plug pattern in the second sub-cell region extends into the pull-up transistor region of the first sub-cell region and is located above the source-drain pattern between adjacent gate patterns.

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