C-shaped trench portion semiconductor device with side wall and manufacturing method thereof and electronic device

Abstract

Disclosed are a C-shaped channel section semiconductor device with side walls and a manufacturing method thereof, and an electronic device including the semiconductor device. According to embodiments, the semiconductor device can include: a channel section on a substrate, the channel section including a curved nanosheet or nanowire in a C-shaped cross section; a first source / drain section and a second source / drain section at upper and lower ends of the channel section, respectively, with respect to the substrate; a first gate stack and a second gate stack at opposite sides of the channel section; a first side wall between the first gate stack and the first source / drain section and between the first gate stack and the second source / drain section, respectively; and a second side wall between the second gate stack and the first source / drain section and between the second gate stack and the second source / drain section, respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and more particularly, to a semiconductor device with gate sidewall and C-shaped nanosheet or nanowire channel and a manufacturing method thereof and an electronic device including the same. BACKGROUND

[0002] With the continuous miniaturization of semiconductor devices, various structures of devices such as fin field effect transistor (FinFET), multi-bridge channel field effect transistor (MBCFET), etc. have been proposed. However, the improvement space of these devices in increasing integration density and enhancing device performance due to the limitation of device structure is still unable to meet the requirements. In addition, due to the process fluctuation of photolithography and etching, etc., it is difficult to control the thickness or diameter of the nanosheet or nanowire for vertical nanosheet or nanowire devices such as metal oxide semiconductor field effect transistor (MOSFET).

[0003] In addition, in horizontal type devices, the sidewall can be provided on the opposite sides of the gate stack in the lateral direction (i.e., the gate stack respectively faces the two sides of the source / drain region opposite to each other in the lateral direction). Due to the limitation of the conventional sidewall formation process, in vertical type devices, it is difficult to form the sidewall on the opposite sides of the gate stack in the vertical direction (i.e., the gate stack respectively faces the two sides of the source / drain region opposite to each other in the vertical direction). SUMMARY

[0004] Therefore, the purpose of the present disclosure is at least partially to provide a semiconductor device with gate sidewall and C-shaped nanosheet or nanowire channel and a manufacturing method thereof and an electronic device including the same.

[0005] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a channel portion on a substrate, the channel portion comprising a curved nanosheet or nanowire with a C-shaped cross section; a first source / drain portion and a second source / drain portion respectively at the upper and lower ends of the channel portion relative to the substrate; a first gate stack and a second gate stack on opposite sides of the channel portion; a first sidewall respectively between the first gate stack and the first source / drain portion and between the first gate stack and the second source / drain portion; and a second sidewall respectively between the second gate stack and the first source / drain portion and between the second gate stack and the second source / drain portion.

[0006] According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a stack of a first material layer, a second material layer, and a third material layer on a substrate; patterning the stack into a ridge-shaped structure including a first side and a second side opposite to each other in a first direction, and a third side and a fourth side opposite to each other in a second direction intersecting the first direction; laterally recessing sidewalls of the second material layer with respect to sidewalls of the first material layer and the third material layer at the third side and the fourth side, thereby defining a second recess; forming a channel layer on a surface of the second material layer exposed by the second recess; forming a second position retaining layer in a remaining space of the second recess and a first sidewall on upper and lower surfaces of the second position retaining layer; forming a source / drain portion in the first material layer and the third material layer; forming an opening in the ridge-shaped structure along the first direction, thereby dividing the ridge-shaped structure into two portions opposite to each other in the second direction; removing the second material layer through the opening; forming a third position retaining layer in a space released due to the removal of the second material layer and a second sidewall on upper and lower surfaces of the third position retaining layer; forming an isolation layer on the substrate; removing the second position retaining layer and the third position retaining layer; and forming a first gate stack and a second gate stack on the isolation layer on opposite sides of the channel layer in the second direction.

[0007] According to another aspect of the present disclosure, there is provided an electronic device including the above semiconductor device.

[0008] According to embodiments of the present disclosure, (gate) sidewalls are introduced in vertical devices having C-shaped nanosheet or nanowire channel portions, thereby allowing to increase the electrical separation distance between the gate stack, in particular the conductor layer therein, and the source / drain regions, and thus to suppress the increase of parasitic capacitance, in particular in case the conductor layer thickness is increased to reduce the electrical resistance. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 25 Some stages in a flow of manufacturing a semiconductor device according to embodiments of the present disclosure are schematically illustrated;

[0011] Figures 26(a) to 32(b) Some stages in a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure are schematically illustrated, in which:

[0012] Figure 5(a) 、 8(a), 21(a), 22, 23(a), 24(a), 25, 26(a), 27(a) are plan views in which the positions of the AA' line, the CC' line from which the cross-sectional view is taken in FIG. 5(a), the position of the BB' line from which the cross-sectional view is taken in FIG. 8(a), and the position of the EE' line from which the cross-sectional view is taken in FIG. 27(a) are shown;

[0013] Figures 1 to 4 , 5(b), 8(b), 9 to 15, 16(a), 16(b), 17, 18, 19(a), 20, 21(b), 23(b), 24(b), 26(b), 27(b), 28(a), 29 to 31, 32(a) are cross-sectional views along the AA' line;

[0014] FIG. 8(c) is a cross-sectional view along the BB' line;

[0015] Figure 5(c) , 6 , 7, 8(d), 26(c), 27(c) are cross-sectional views along the CC' line;

[0016] Figure 19(b) , 21(c) , 23(c), 28(b), 32(b) are cross-sectional views taken along the DD' line, in which the position of the DD' line is shown in FIG. 19(a);

[0017] FIG. 27(d) is a cross-sectional view along the EE' line.

[0018] Throughout the drawings, the same or similar reference numerals are used to represent the same or similar components. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0020] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These drawings are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and certain details can be omitted. The shapes of various regions, layers, and the relative size and positional relationship therebetween shown in the drawings are merely exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0021] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, it can be directly on the other layer / element, or there can be intervening layers / elements therebetween. Also, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0022] According to embodiments of the present disclosure, a vertical type semiconductor device is provided, having an active region disposed vertically (e.g., along a direction substantially perpendicular to a surface of a substrate) on the substrate. The channel portion can be a curved nanosheet or nanowire having a C-shape in cross-section (e.g., perpendicular to the surface of the substrate), and thus such a device can be referred to as a C-Channel FET (CCFET). As described below, the nanosheet or nanowire can be formed by epitaxial growth, and thus can be a monolithic piece and can have a substantially uniform thickness or diameter.

[0023] The semiconductor device can further include source / drain portions disposed on and under the channel portion, respectively. The source / drain portions can have a dimension in a lateral direction relative to the substrate that is greater than a dimension of the channel portion in the corresponding direction, to ensure that the channel portion is connected to the source / drain portions on both ends. The source / drain portions can have a certain doping. For example, for a p-type device, the source / drain portions can have p-type doping; for an n-type device, the source / drain portions can have n-type doping. The channel portion can have a certain doping to adjust a threshold voltage of the device. Alternatively, the semiconductor device can be a junctionless device, in which the channel portion and the source / drain portions can have doping of the same conductivity type. Alternatively, the semiconductor device can be a tunneling type device, in which the source / drain portions on both ends of the channel portion can have doping types opposite to each other.

[0024] The source / drain portions can be disposed in respective semiconductor layers. For example, the source / drain portions can be doped regions in the respective semiconductor layers. The source / drain portions can be a portion or all of the respective semiconductor layers. In the case where the source / drain portions are a portion of the respective semiconductor layers, there can be a doping concentration interface between the source / drain portions and the remaining portions of the respective semiconductor layers. As described below, the source / drain portions can be formed by diffusion doping. In this case, the doping concentration interface can be substantially along a vertical direction relative to the substrate.

[0025] The channel portion can include a single-crystalline semiconductor material. Of course, the source / drain portions or the semiconductor layers in which they are formed can also include a single-crystalline semiconductor material. For example, they can all be formed by epitaxial growth.

[0026] The semiconductor device can further include a first gate stack and a second gate stack on opposite sides of the channel portion. The first gate stack and the second gate stack can be separated from each other and thus can take different configurations and / or apply different biases to optimize device performance. Alternatively, the first gate stack and the second gate stack can be connected to each other (and can form one body) to form a perimeter around the channel portion. Thus, the semiconductor device according to embodiments of the present disclosure can be a surround gate device. According to embodiments of the present disclosure, the gate stack can be self-aligned to the channel portion. For example, at least a portion of the gate stack proximate to the channel portion can be substantially coplanar with the channel portion, e.g., the portion of the gate stack and the upper and / or lower surfaces of the channel portion can be substantially coplanar with each other.

[0027] According to embodiments of the present disclosure, a sidewall can be provided between the gate stack and the source / drain portion. The sidewall can increase the spacing or electrical isolation distance between the gate stack, particularly the conductor layer therein, and the source / drain portion, and thus can reduce parasitic capacitance. The sidewall generally does not extend onto the surface of the gate stack facing the channel portion to avoid affecting the control of the channel region in the channel portion by the gate stack.

[0028] As described below, the sidewall can be formed in a self-aligned manner. Specifically, the sidewall can be self-aligned to the upper and lower ends of the channel portion, respectively. Self-alignment refers to the relative positions between structures that are substantially unaffected by process fluctuations, particularly photolithography fluctuations. Such self-aligned structures are detectable. For example, in an integrated circuit (IC) there can be multiple such devices, and if the structures are self-aligned, the relative positions of the sidewall with respect to the ends of the channel portion can remain substantially the same across the devices; whereas if the structures are not self-aligned, there can be process fluctuations in the relative positions across the devices. Similar to the sidewall in a horizontal device that extends substantially in the vertical direction, the sidewall according to embodiments of the present disclosure can extend in the lateral direction.

[0029] Such a semiconductor device can be fabricated, for example, as follows.

[0030] According to embodiments, a stack of a first material layer, a second material layer, and a third material layer can be provided on a substrate. The first material layer can define the location of the lower end source / drain portion, the second material layer can define the location of the gate stack, and the third material layer can define the location of the upper end source / drain portion. The first material layer can be provided by the substrate, e.g., an upper portion of the substrate, and the second material layer and the third material layer can be formed on the first material layer in sequence, e.g., by epitaxial growth. Alternatively, the first material layer, the second material layer, and the third material layer can be formed on the substrate in sequence, e.g., by epitaxial growth. The first material layer and the third material layer can be in-situ doped during epitaxial growth to form the source / drain portions therein.

[0031] The stack can be patterned into a ridge structure. The ridge structure can include first and second sides opposite each other in a first direction and third and fourth sides opposite each other in a second direction that intersects (e.g., is perpendicular to) the first direction. For example, the ridge structure can be quadrilateral, such as rectangular or square, in plan view. The channel portion can be formed on a pair of opposite sidewalls (e.g., the third and fourth sides) of the ridge structure.

[0032] A masking material can be formed on the first and second sides of the ridge structure. In this way, subsequent processing can not affect the first and second sides of the ridge structure, so that gate stacks can be formed on the third and fourth sides of the ridge structure that are separated from each other. Alternatively, to subsequently form gate stacks around the channel portion, spaces for forming the gate stacks can be defined on the first and second sides of the ridge structure. For example, the sidewalls of the second material layer can be laterally recessed relative to the sidewalls of the first and third material layers on the first and second sides of the ridge structure, thereby defining first recesses. The first recesses can have curved surfaces that are recessed toward the interior of the ridge structure. First position-retaining layers can be formed in the first recesses.

[0033] Likewise, the sidewalls of the second material layer can be laterally recessed relative to the sidewalls of the first and third material layers on the third and fourth sides of the ridge structure, thereby defining second recesses to define spaces for the gate stacks. The second recesses can have curved surfaces that are recessed toward the interior of the ridge structure. The channel portion can be formed on the surfaces of the second recesses. For example, a first active layer can be formed by epitaxial growth on the exposed surfaces of the ridge structure, and portions of the first active layer on the surfaces of the second recesses can serve as the channel portion (also referred to as a “channel layer”). One device can be formed based on the first active layer on the sidewalls of the third and fourth sides of the ridge structure, respectively. Thus, two devices opposite each other can be formed based on a single ridge structure. Second position-retaining layers can be formed in the second recesses on the surfaces where the channel layer is formed.

[0034] After defining the second recesses and before forming the first active layer, the exposed surfaces of the ridge structure can also be etched back by an amount, e.g., approximately the thickness of the first active layer to be formed. This can help ensure that the gate stacks subsequently formed on opposite sides of the channel portion have substantially equal gate lengths.

[0035] Source / drain portions can be formed in the first and third material layers. For example, the source / drain portions can be formed by doping the first and third material layers (particularly where they are not doped when formed). Such doping can be achieved by a solid-phase dopant source layer.

[0036] An opening can be formed in the ridge structure to separate the active regions of the two devices. The opening can also extend along the first direction, thereby dividing the ridge structure into two parts opposite in the second direction, each having a respective channel layer. Through the opening, the second material layer can be removed, and a third position retaining layer can be formed in the space released by the removal of the second material layer.

[0037] According to embodiments of the present disclosure, when forming each of the first, second, and third position retaining layers, a sidewall is also formed on the respective upper and lower surfaces thereof. For example, the sidewall position defining layer can be formed in a substantially conformal manner, and then the respective position retaining layer is formed. The sidewall position defining layer (on the upper and lower surfaces of the respective position retaining layer) is selectively etched to release a space, and a sidewall is formed in the space thus released by filling a sidewall material such as a dielectric, with the respective position retaining layer as a mask.

[0038] The second and third position retaining layers (and the first position retaining layer, if present) can be replaced by a gate stack through a replacement gate process, thereby forming a gate stack that overlaps the channel portion. The sidewalls originally on the respective upper and lower surfaces of the second and third position retaining layers (and the first position retaining layer, if present) can be interposed between the gate stack and the source / drain portions, forming gate sidewalls.

[0039] According to embodiments of the present disclosure, the thickness of the nanosheet or nanowire serving as the channel portion and the gate length are primarily determined by epitaxial growth, rather than by etching or lithography, and thus can have good control of the channel size / thickness and gate length.

[0040] The present disclosure can take various forms, some examples of which will be described below. In the following description, the selection of various materials is involved. The selection of materials is considered not only in terms of their functionality (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation), but also in terms of etching selectivity. In the following description, the required etching selectivity can or can not be indicated. It will be apparent to those skilled in the art that when the following refers to etching a certain material layer, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity with respect to other layers exposed to the same etching recipe.

[0041] Figures 1 to 25 Some stages in a flow of fabricating a semiconductor device according to embodiments of the present disclosure are schematically shown.

[0042] As Figure 1As shown, a substrate 1001 (the upper portion of which can constitute the first material layer described above) is provided. The substrate 1001 can be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, etc. In the following description, a bulk Si substrate is used as an example for convenience of illustration. Here, a silicon wafer is provided as the substrate 1001.

[0043] In the substrate 1001, a well region can be formed. If a p-type device is to be formed, the well region can be an n-type well; if an n-type device is to be formed, the well region can be a p-type well. The well region can be formed, for example, by implanting a dopant of the corresponding conductivity type (p-type dopant such as B or In, or n-type dopant such as As or P) into the substrate 1001 and then performing a thermal anneal. There are various ways to provide such a well region in the art, which will not be described here.

[0044] On the substrate 1001, a second material layer 1003 and a third material layer 1005 can be formed, for example, by epitaxial growth. The second material layer 1003 can be used to define the location of the gate stack, with a thickness of about 20 nm to 50 nm, for example. The third material layer 1005 can be used to define the location of the upper source / drain portions, with a thickness of about 20 nm to 200 nm, for example.

[0045] The substrate 1001 and adjacent ones of the layers described above formed thereon can have etch selectivity with respect to each other. For example, in the case where the substrate 1001 is a silicon wafer, the second material layer 1003 can include SiGe (e.g., with a percentage of Ge atoms of about 10% to 30%), and the third material layer 1005 can include Si.

[0046] According to embodiments, a spacer pattern transfer technique is used in the following patterning. To form the spacers, a mandrel can be formed. For example, as shown in FIG. 10A, a layer 1011 for the mandrel can be formed on the third material layer 1005, for example, by deposition. The layer 1011 for the mandrel can include amorphous silicon or polysilicon, for example, with a thickness of about 50 nm to 150 nm. In addition, for better etch control, an etch stop layer 1009 can be formed first, for example, by deposition. The etch stop layer 1009 can include an oxide (e.g., silicon oxide), for example, with a thickness of about 1 nm to 10 nm. Figure 2

[0047] On the layer 1011 for the mandrel, a hard mask layer 1013 can be formed, for example, by deposition. The hard mask layer 1013 can include nitride (e.g., silicon nitride), for example, with a thickness of about 30 nm to 100 nm.

[0048] ​The layer 1011 for the dummy pattern can be patterned to the dummy pattern.

[0049] For example, as shown in FIG. 10(a), a photoresist 1007 can be formed on the hard mask layer 1013 and patterned by photolithography to a strip shape extending in the first direction (i.e., the direction perpendicular to the plane of the paper). Figure 3 Figure 3 The photoresist 1007 can be used as an etch mask to selectively etch the hard mask layer 1013 and the layer 1011 for the dummy pattern in sequence by, for example, reactive ion etching (RIE), transferring the pattern of the photoresist to the hard mask layer 1013 and the layer 1011 for the dummy pattern. The etching can stop at the etch stop layer 1009. Thereafter, the photoresist 1007 can be removed.

[0050] As shown in FIG. 10(b), a sidewall 1017 can be formed on the sidewalls of the dummy pattern 1011 on opposite sides in the second direction (i.e., the horizontal direction in the plane of the paper) intersecting (e.g., perpendicular to) the first direction. Figure 4 Figure 4 For example, a layer of nitride with a thickness of about 10 nm to 100 nm can be deposited in a substantially conformal manner, and then anisotropic etching such as RIE can be performed on the deposited nitride layer in the vertical direction (which can stop at the etch stop layer 1009) to remove the horizontally extending portion thereof and leave the vertically extending portion thereof, thereby obtaining the sidewall 1017. The sidewall 1017 can then be used to define the location of the active region of the device.

[0051] The dummy pattern formed as described above and the sidewall 1017 formed on the sidewalls thereof extend in the first direction. Their extent in the first direction can be defined, and thus the extent of the active region of the device in the first direction can be defined.

[0052] As shown in FIG. 10(c), a photoresist 1015 can be formed on the structure shown in FIG. 10(b) and patterned by photolithography to a strip shape occupying a certain extent in the first direction, for example, extending along the second direction perpendicular to the first direction. Figures 5(a) to 5(c) Figure 4 The photoresist 1015 can be used as an etch mask to selectively etch the underlying layers in sequence by, for example, RIE in the vertical direction. The etching can proceed into the substrate 1001, in particular the well region therein, thereby forming a recess in the substrate 1001. An isolation, for example, a shallow trench isolation (STI), can then be formed in the recess. Thereafter, the photoresist 1015 can be removed.

[0053] As shown in FIG. 5(c), the sidewalls of the second material layer 1003 in the first direction are now exposed to the outside.

[0054] According to embodiments of the present disclosure, in order to form the gate stack surrounding the channel portion, space for the gate stack can be left at both ends of the second material layer in the first direction.​​​

[0055] To this end, as shown in Figure 6 , the second material layer 1003 can be selectively etched so that its sidewall in the first direction is relatively recessed. To better control the amount of etching, atomic layer etching (ALE) can be used. For example, hydrogen (H) and / or helium (He) can be used to modify the channel layer 1003 (here, SiGe), and then the modified layer can be removed by wet etching or groups such as NH3, NF3, etc. This process can be repeated until the desired etching depth is achieved, for example, about 5-20 nm. Depending on the characteristics of the etching, such as the etching selectivity of the second material layer 1003 relative to the substrate 1001 and the third material layer 1005, the sidewall of the second material layer 1003 after etching can assume different shapes. In Figure 6 , the sidewall of the second material layer 1003 after etching is shown as a C-shaped inwardly recessed. However, the present disclosure is not limited thereto. For example, when the etching selectivity is good, the sidewall of the second material layer 1003 after etching can be close to vertical. Here, the etching can be isotropic, especially when a larger amount of etching is required.

[0056] In the recess thus formed, (part of) the gate stack will be subsequently formed. According to embodiments of the present disclosure, a side wall can be formed. Generally speaking, the side wall can be formed on opposite sides (in the case of a vertical device, upper and lower sides) of the gate stack respectively facing the source / drain regions, but is not expected to be formed on the side of the gate stack facing the channel region. The formation space of the side wall can be defined by the position-defining layer formed in the recess in combination with the position-retaining layer.

[0057] For example, as shown in Figure 7 , the side wall position-defining layer 1019 can be formed in the recess by epitaxial growth or deposition. The side wall position-defining layer 1019 can be formed in a substantially conformal manner so as to extend along the surface of the structure. Taking into account the etching selectivity in subsequent processing, the side wall position-defining layer 1019 can comprise, for example, SiGe, and have a thickness of, for example, about 2-10 nm. In the recess in which the side wall position-defining layer 1019 is formed, a first position-retaining layer 1021 can be formed. For example, a dielectric material such as SiC can be deposited on the substrate to fill the recess, and then the deposited dielectric material can be etched back, such as by vertical direction RIE. In this way, the dielectric material outside the range defined by the hard mask layer 1013 and the side wall 1017 can be removed, and the dielectric material remains in the recess to form the first position-retaining layer 1021. In addition, during the etch-back process, the side wall position-defining layer 1019 formed on other surfaces outside the recess can also be removed (or, even if not removed, does not affect the subsequent process, so the side wall position-defining layer 1019 is shown in the drawings as being formed only in the recess).

[0058] Then, as Figures 8(a) to 8(d) As shown, the first position holding layer 1021 can be used as a mask to selectively etch back the sidewall position defining layer 1019. The back etching of the sidewall position defining layer 1019 releases space on the upper and lower sides of the first position holding layer 1021, leaving a portion of the sidewall position defining layer 1019 facing the trench region (in this example, the portion extending on the surface of the second material layer 1003). To ensure process margin, the remaining sidewall position defining layer 1019, in addition to the portion extending on the surface of the second material layer 1013, can extend slightly to the upper and lower surfaces of the first position holding layer 1021. Since the etching on the upper and lower sides is performed substantially equally, the lengths of the sidewall position defining layer 1019 extending on the upper and lower surfaces of the first position holding layer 1021 can be approximately the same. Here, ALE (Alternating Edge Etching) can be used to better control the etching amount.

[0059] Sidewalls can be formed in the space released by the etchback of the sidewall position-defining layer 1019. For example, a thin sidewall material layer can be formed by deposition such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Considering etching selectivity (e.g., relative to the first position-holding layer 1021), the sidewall material layer may include nitrides. The sidewall material layer can be formed in a generally conformal manner, and the deposition thickness is such that the deposited sidewall material layer fills the spaces above and below the first position-holding layer 1021. Then, the deposited sidewall material layer can be anisotropically etched, such as by re-etching (RIE). RIE can be performed vertically, and the etching depth can be greater than the deposition thickness, thereby removing the portion of the sidewall material layer outside the recess while retaining the portion within the recess, thus forming sidewall 1023.

[0060] The portions of the sidewall 1023 on the upper and lower sides of the first position retaining layer 1021 occupy the space where the original sidewall position defining layer 1019 was located (therefore, the thickness is substantially the same as the thickness of the sidewall position defining layer 1019, and they can be substantially coplanar, for example, the upper surface is coplanar and / or the lower surface is coplanar), and therefore can be self-aligned with the sidewall position defining layer 1019. In addition, the sidewall position defining layer 1019 can be self-aligned with the second material layer 1003 (and therefore can be self-aligned with the channel area formed in the second material layer 1003), so the portions of the sidewall 1023 on the upper and lower sides of the first position retaining layer 1021 can be self-aligned with the upper and lower ends of the channel area.

[0061] According to embodiments of the present disclosure, a protective layer 1025 can also be formed on the substrate 1001. For example, the protective layer 1025 can be formed by depositing an oxide layer on the substrate 1001 and further etching back after planarizing the deposited oxide layer, such as chemical mechanical polishing (CMP) (the CMP can stop on the hard mask layer 1013). Here, the protective layer 1025 can be in the recesses of the substrate 1001 and have a top surface lower than the top surface of the substrate 1001. In addition, during the etching back, the portions of the etch stop layer 1009 (which is also oxide in this example) exposed outside can also be etched. According to other embodiments, the operation of forming the protective layer 1025 can be performed before the operation of selectively etching the second material layer 1003 to recess it, or before the operation of etching back the side wall position defining layer 1019.

[0062] The protective layer 1025 can protect the surface of the substrate 1001. For example, in this example, the range of the active region in the first direction has been defined. Subsequently, the range of the active region in the second direction will be defined. The protective layer 1025 can avoid affecting the surface of the substrate currently exposed outside in the recesses (see Figure 5(c) and 7 ) when the range in the second direction is defined. In addition, in the case of forming different types of well regions in the substrate 1001, the protective layer 1025 can protect the pn junction between different types of well regions from being damaged by etching (e.g., etching back when forming the first position maintaining layer 1021).

[0063] As shown in Figure 9 , the upper portion (first material layer) of the substrate 1001, the second material layer 1003, and the third material layer 1005 can be patterned into ridge structures (in fact, the range of the ridge structures in the first direction has been defined by the above-mentioned processing) using the hard mask layer 1013 and the side wall 1017. For example, the hard mask layer 1013 and the side wall 1017 can be used as etching masks, and the pattern can be transferred to the underlying layers by, for example, vertical direction RIE, to selectively etch each layer in turn. Thus, the upper portion of the substrate 1001, the second material layer 1003, and the third material layer 1005 can form ridge structures. As mentioned above, due to the presence of the protective layer 1025, the etching can not affect the portions of the substrate 1001 on both sides of the ridge structures in the first direction.

[0064] Here, the etching can enter the well region of the substrate 1001. The degree to which the etching enters the substrate 1001 can be substantially the same or similar to the degree to which the etching enters the substrate 1001 described above in connection with Figures 5(a) to 5(c) . Similarly, recesses are formed in the substrate 1001, and protective layers can also be formed in these recesses (see Figure 10The protective layer 3 surrounds the outer periphery of the ridge structure together with the previous protective layer (indicated as 1025 together). In this way, similar processing conditions can be achieved around the ridge structure, i.e. both the substrate 1001 has a recess formed therein, and the recess has a protective layer 1025 formed therein.

[0065] Similarly, in order to form the gate stack around the channel portion, space for the gate stack can be left at both ends of the second material layer in the second direction. For example, as shown in Figure 10 the second material layer 1003 can be selectively etched so that its sidewall in the second direction is relatively recessed (space for the gate stack can be defined). In order to better control the amount of etching, ALE can be used. For example, the amount of etching can be about 10-40 nm. As described above, the sidewall of the second material layer 1003 after etching can present a C shape that is recessed inwardly. Here, the etching can be isotropic, especially when a larger amount of etching is required. Generally, the C-shaped sidewall of the second material layer 1003 has a larger curvature at both upper and lower ends, and a smaller curvature at the waist or middle part.

[0066] The first active layer can be formed on the sidewall of the ridge structure so as to subsequently define the channel portion. In order to make the gate length (e.g. in the direction perpendicular to the substrate surface) of the gate stack formed on both sides of the C-shaped channel portion remain substantially equal, as shown in Figure 11 the ridge structure (particularly, the exposed surface of the first material layer, the second material layer and the third material layer) can be etched back so that its outer peripheral sidewall is relatively recessed. In order to control the etching depth, ALE can be used. The etching depth can be substantially equal to the thickness of the first active layer to be subsequently grown, e.g. about 5-15 nm.

[0067] Then, as shown in Figure 12 the first active layer 1027 can be formed on the sidewall of the ridge structure by, for example, selective epitaxial growth. Due to the selective epitaxial growth, the surface of the first position maintaining layer 1021 can not have the first active layer 1027 formed thereon. The first active layer 1027 can subsequently define the channel portion, with a thickness of, for example, about 3-15 nm. Since the channel portion (although it can present a C shape) mainly extends in the vertical direction, the first active layer 1027 (particularly, the part thereof on the sidewall of the second material layer) can also be referred to as a (vertical) channel layer. According to embodiments of the present disclosure, the thickness of the first active layer 1027 (which is subsequently used as the channel portion) can be determined by the epitaxial growth process, and thus the thickness of the channel portion can be better controlled. The first active layer 1027 can be doped in situ when epitaxially grown, so as to adjust the threshold voltage of the device.

[0068] In Figure 12In this embodiment, the sidewall of the portion of the first active layer 1027 on the sidewall of the first material layer and the third material layer is shown as substantially flush with the sidewall of the sidewall 1017. This can be achieved by controlling the etch-back amount and the epitaxial growth thickness to be substantially the same. However, the present disclosure is not limited thereto. For example, the sidewall of the portion of the first active layer 1027 on the sidewall of the first material layer and the third material layer can be recessed with respect to the sidewall of the sidewall 1017, or even possibly protruding.

[0069] Here, performing the above etch-back can etch the upper end and the lower end of the recessed portion upward and downward, respectively, such that after growing the first active layer 1027, the height t1 of the recessed portion can be substantially the same as the thickness t2 of the second material layer 1003. In this way, the gate stacks subsequently formed on the left and right sides of the first active layer 1027 can have substantially equal gate lengths. However, the present disclosure is not limited thereto. According to embodiments of the present disclosure, the gate lengths on the outer sides of the first active layer 1027 can also be changed by adjusting the etch-back amount, so as to change the ratio of the gate lengths on the two sides, in order to optimize the impact of the different morphologies on the left and right sides of the C-shaped channel portion on the performance of the device.

[0070] The material of the first active layer 1027 can be appropriately selected according to the performance requirements of the device according to the design. For example, the first active layer 1027 can include various semiconductor materials, such as Si, Ge, SiGe, InP, GaAs, InGaAs, etc. In this example, the first active layer 1027 can include the same material as the first material layer and the third material layer, such as Si.

[0071] In Figure 12 In this example, the ridge structure can have substantially the same features (e.g., material, size, doping characteristics, etc.) on the first active layer 1027 on the opposite sides in the second direction, and can be symmetrically arranged on the opposite sides of the second material layer. However, the present disclosure is not limited thereto. As described below, two devices opposite to each other can be formed by a single ridge structure. According to the performance requirements of the two devices according to the design, the first active layer 1027 on the opposite sides of the ridge structure can have different features, such as being different in at least one of thickness, material, and doping characteristics, etc. This can be achieved by shielding one device region when growing the first active layer in the other device region.

[0072] Due to the recessing of the second material layer 1003, a gap is formed outside the portion of the first active layer 1027 corresponding to the second material layer 1003. In this gap, a gate stack can be subsequently formed.

[0073] Similar to the process described above in combination Figure 7 with the above description, a sidewall can be formed in the gap. For example, as Figure 13As shown, a sidewall position defining layer 1029 and a second position holding layer 1031 can be formed in the gap, and sidewalls 1033 are formed above and below the second position holding layer 1031. The sidewall position defining layer 1029 and the sidewall position defining layer 1019 can have substantially the same characteristics, such as the same material and substantially the same thickness, and similarly, the sidewalls 1023 and 1033 can have substantially the same characteristics, such as the same material and substantially the same thickness. The sidewall 1033 can extend in a first direction to connect with the previously formed sidewall 1023, so that an interface can exist between them. Furthermore, the first position holding layer 1021 and the second position holding layer 1031 can comprise the same material, so that they can subsequently be removed together in an alternative gate process using the same etching formulation.

[0074] After that, source / drain doping can be performed.

[0075] like Figure 14 As shown, it can be achieved, for example, by deposition, in Figure 13 A solid-state doped source layer 1035 is formed on the structure shown. The solid-state doped source layer 1035 can be formed in a generally conformal manner. For example, the solid-state doped source layer 1035 can be an oxide containing dopant with a thickness of about 1 nm to 5 nm. The dopant contained in the solid-state doped source layer 1035 can be used to dope the source / drain (and optionally, the exposed surface of the substrate 1001), and therefore can have the same conductivity type as the desired source / drain. For example, for p-type devices, the solid-state doped source layer 1035 can contain p-type dopant such as B or In; for n-type devices, the solid-state doped source layer 1035 can contain n-type dopant such as P or As. The concentration of the dopant in the solid-state doped source layer 1035 can be about 0.1% to 5%.

[0076] In this example, before forming the solid-state doped source layer 1035, the protective layer 1025 can be selectively etched, for example, by a re-etching process (RIE), to expose the surface of the substrate 1001. In this way, the exposed surface of the substrate 1001 can also be doped to form the respective contact regions of the source / drain S / D portions at the lower ends of the two devices.

[0077] like Figure 15 As shown, the dopant in the solid-state dopant source layer 1035 can be driven into the first and third material layers through annealing to form source / drain S / D portions (and optionally, driven into the exposed surface of the substrate 1001 to form respective contact regions of the source / drain S / D portions at the lower ends of the two devices). Afterwards, the solid-state dopant source layer 1035 can be removed.

[0078] Since the first material layer and the third material layer can have the same material, and the solid phase dopant source layer 1035 can be formed on their surfaces in a substantially conformal manner, the drive-in of dopants from the solid phase dopant source layer 1035 into the first material layer and the third material layer can be substantially the same. Therefore, the (doping concentration) interface of the source / drain portion S / D (with the inner portion of the first material layer, the third material layer) can be substantially parallel to the surfaces of the first material layer and the third material layer, i.e., can be in the vertical direction, and can be aligned with each other.

[0079] In this example, the first material layer is provided by the upper portion of the substrate 1001. However, the present disclosure is not limited thereto. For example, the first material layer can also be an epitaxial layer on the substrate 1001. In this case, the first material layer and the third material layer can be doped in situ during epitaxy, instead of using a solid phase dopant source layer.

[0080] In the trench around the ridge structure, an isolation layer 1037 can be formed, as shown in FIG. 16(a). The method of forming the isolation layer can be similar to the method of forming the protective layer 1025 as described above, and will not be described again here.

[0081] To reduce the capacitance between the gate and the source / drain, the overlap between the gate and the source / drain can be further reduced. For example, as shown in FIG. 16(b), after the solid phase dopant source layer 1035 is removed, the source / drain portion S / D can be further recessed in the lateral direction by, for example, selectively etching the first active layer 1027 formed on the sidewalls of the first material layer and the third material layer, and even further selectively etching the first material layer and the third material layer, so that the overlap between the source / drain portion S / D and the first position maintaining layer 1021, the second position maintaining layer 1031 (which later define the position of the gate stack) is reduced. In the space released below the hard mask layer 1013 and the sidewall 1017 due to the recessing of the source / drain portion S / D, a dielectric 1037' such as nitride oxide or oxide can be filled. The filling can be achieved by deposition (and planarization) followed by etch-back. During etch-back, a certain thickness of the dielectric 1037' is left on the surface of the substrate 1001 to form an isolation portion.

[0082] In the following, for the sake of convenience, the case shown in FIG. 16(a) is still taken as an example for description.

[0083] Next, the definition of the active region can be completed using the sidewall 1017.

[0084] As Figure 17As shown, the hard mask layer 1013 can be removed to expose the mandrel pattern 1011 by selective etching such as RIE or planarization processing such as CMP. In the process of removing the hard mask layer 1013, the height of the sidewall 1017, which is also nitride in this example, can be reduced. Then, the mandrel pattern 1011 can be removed by selective etching such as wet etching with TMAH solution or dry etching with RIE. In this way, a pair of sidewalls 1017 (height reduced, top end profile can also be changed) are left on the ridge structure extending opposite to each other.

[0085] The sidewalls 1017 can be used as etching masks to selectively etch the etching stop layer 1009, the third material layer 1005, the second material layer 1003 and the upper portion of the substrate 1001 in turn by, for example, RIE in the vertical direction. The etching can be performed into the well region of the substrate 1001. In this way, the third material layer 1005, the second material layer 1003 and the upper portion of the substrate 1001 form a pair of stacks corresponding to the sidewalls 1017 in the space surrounded by the isolation layer 1037 to define the active region.

[0086] Of course, the formation of the stacks for defining the active region is not limited to the sidewall pattern transfer technique, and can also be performed by photolithography using photoresist or the like.

[0087] Here, the second material layer 1003 for defining the gate stack position includes a semiconductor material for the purpose of epitaxial growth. To facilitate the subsequent replacement gate process, the second material layer 1003 can be replaced with a dielectric material to form a third position retaining layer.

[0088] For example, as shown in FIG. 10, the second material layer 1003 can be replaced with a dielectric material 1004 by, for example, wet etching with TMAH solution or dry etching with RIE. In this way, the dielectric material 1004 is formed on the third material layer 1005 and the upper portion of the substrate 1001 to define the active region. Figure 18As shown, the second material layer 1003 (SiGe in this example) can be removed by selective etching relative to the first active layer 1027, the substrate 1001, and the third material layer 1005 (all Si in this example). This creates a void on the side of the first active layer 1027 opposite to the second position holding layer 1031 (released due to the removal of the second material layer 1003). Similarly, sidewalls can be formed in this void. For example, a sidewall position defining layer 1039 and a third position holding layer 1041 can be formed in this void, with sidewalls 1043 formed above and below the third position holding layer 1041. The sidewall position defining layer 1039 can have substantially the same characteristics as the sidewall position defining layers 1019 and 1029, such as the same material and substantially the same thickness, and similarly, the sidewalls 1043 can have substantially the same characteristics as the sidewalls 1023 and 1033, such as the same material and substantially the same thickness. Sidewall 1043 may extend in the first direction to engage with previously formed sidewall 1023, thus allowing an interface to exist between them. Additionally, the third position holding layer 1041 may comprise the same material as the first position holding layer 1021 and the second position holding layer 1031, so that they can subsequently be removed together with the same etching formulation in an alternative gate process.

[0089] Furthermore, no isolation layer has been formed between the pair of stacks (active regions) corresponding to sidewall 1017. For example... Figure 19(a) and 19(b) As shown, the isolation layer 1045 can be formed on the substrate 1001 by, for example, deposition (and planarization) followed by etching back. For example, the isolation layer 1045 may comprise an oxide and is therefore shown as integral with the preceding isolation layer 1037. The top surface of the isolation layer 1045 may be close to, for example, not lower than (preferably slightly higher than) the top surface of the first material layer (i.e., the top surface of the substrate 1001) or the bottom surface of the second material layer (i.e., the lower surface of the sidewalls formed on the bottom surfaces of the first position holding layer 1021, the second position holding layer 1031, and the third position holding layer 1041), and not higher than the top surface of the second material layer (i.e., the upper surface of the sidewalls formed on the top surfaces of the first position holding layer 1021, the second position holding layer 1031, and the third position holding layer 1041) or the bottom surface of the third material layer. This can reduce the overlap between the gate stack and the source / drain portions, particularly the lower source / drain portions.

[0090] As shown in Figure 19(b), the first position holding layer 1021, the second position holding layer 1031, and the third position holding layer 1041 (which together define the position of the gate stack) surround a portion of the first active layer 1027. This portion of the first active layer 1027 can be used as a channel. It can be seen that the channel is a C-shaped curved nanosheet (when the nanosheet is narrow, for example, when the vertical dimension in the plane of the paper in Figure 19(b) is small, it can become a nanowire). Due to the high etching selectivity of the second material layer 1003 (SiGe) relative to the first active layer 1025 (Si), the thickness of the channel (in the case of nanowires, either coarse or diameter) is essentially determined by the selective growth process of the first active layer 1025. This has a significant advantage over techniques that use only etching or photolithography to determine the thickness, as epitaxial growth processes offer much better process control than etching or photolithography.

[0091] Here, a sidewall position limiting layer 1029 is provided between the second position holding layer 1031 and the first active layer 1027, and a sidewall position limiting layer 1039 is provided between the third position holding layer 1041 and the first active layer 1027. Additionally, regarding the sidewall position limiting layer 1019 formed on the surface of the second material layer 1003 (see, for example, FIG. 8(d); in this example, SiGe), in combination as described above... Figure 18 When the second material layer 1003 (in this example, SiGe) is removed, it can be removed together.

[0092] According to another embodiment of this disclosure, to reduce capacitance, the overlap between the gate and the first and third material layers (wherein the active / drain portions are formed) can be further reduced. For example, as Figure 20 As shown, after forming the third position holding layer 1041 as described above, the exposed surfaces of the first and third material layers can be further recessed by selective etching. This reduces the overlap between the first and third material layers and the third position holding layer 1041 (which subsequently defines the location of the gate stack). Subsequently, the isolation layer 1045' can be formed similarly. During the formation of the isolation layer 1045', the dielectric material of the isolation layer 1045' also fills the voids formed below the sidewall 1017 due to the recess of the third material layer.

[0093] exist Figure 20 The example shows a reference process performed in addition to the reduction overlap process described with reference to Figure 16(b). Figure 20 The structure obtained by the described process of reducing overlap is such that the outer periphery of the source / drain S / D is surrounded by a dielectric material. However, this disclosure is not limited thereto. For example, the process of reducing overlap described with reference to FIG16(b) is similar to that described in FIG16(b). Figure 20The described process of reducing overlap can be performed alternatively or both.

[0094] In the following description, still referring to the case shown in Figure 19(a) and 19(b) is described by way of example.

[0095] Next, a replacement gate process can be performed to form gate stacks.

[0096] As shown in Figures 21(a) to 21(c) , the first, second and third position preserving layers 1021, 1031 and 1041 can be removed by selective etching, and the side wall position defining layers 1029, 1039 exposed thereby can also be removed. Thus, space for the gate stacks is released, i.e., the space originally occupied by the first, second and third position preserving layers 1021, 1031 and 1041 and the side wall position defining layers 1029, 1039.

[0097] The gate stacks can be formed on the isolation layer 1045. For example, a gate dielectric layer 1047 can be formed by deposition in a substantially conformal manner, and a gate conductor layer 1049 can be formed on the gate dielectric layer 1047. The gate conductor layer 1049 can fill the space between the source regions. The gate conductor layer 1049 can be planarized, e.g., by CMP, which can stop on the side walls 1017. Then, the gate conductor layer 1049 can be etched back so that its top surface is lower than the upper surface of the side walls formed on the top surfaces of the first, second and third position preserving layers 1021, 1031 and 1041 (or the top surface of the second material layer or the bottom surface of the third material layer), to reduce the capacitance between the source / drain regions and the gate stacks. In this way, the ends of the gate stacks formed are embedded in the space released by the removal of the first, second and third position preserving layers 1021, 1031 and 1041 (and the side wall position defining layers 1029, 1039), surrounding the channel regions.

[0098] For example, the gate dielectric layer 1047 can include a high-k gate dielectric such as HfO2, with a thickness of about 1 nm to 5 nm. Before forming the high-k gate dielectric, an interface layer can also be formed, e.g., an oxide formed by an oxidation process or deposition such as ALD, with a thickness of about 0.3 nm to 1.5 nm. The gate conductor layer 1039 can include a work function adjusting metal such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), etc., and a gate conductive metal such as tungsten (W), etc.

[0099] At this point, the respective gate stacks of the two devices are connected to each other as one. The gate conductor layer 1049 can be disconnected between the two devices by, e.g., lithography, according to the device design, while the gate contact pads can also be patterned.

[0100] As shown in FIG. 23(a), a photoresist 1051 can be formed and patterned to mask the area where the landing pad for the gate contact is to be formed, and to expose other areas. Then, as shown in FIG. 23(b), the photoresist 1051 (as well as the sidewall 1017) can be used as a mask to selectively etch the gate conductor layer 1049, e.g., by RIE, which can be performed vertically and stopped on the gate dielectric layer 1047. After that, the photoresist 1051 can be removed. Figure 22 Figures 23(a) to 23(c)

[0101] Thus, the gate conductor layer 1049 can be substantially left and self-aligned under the sidewall 1017, except for a portion protruding on one side (the upper side in FIG. 23(a)) of the sidewall 1017 to serve as the landing pad. The gate conductor layer 1049 is separated between the two opposite devices respectively under the opposite sidewalls 1017, thereby defining the gate stack for the two devices respectively in combination with the gate dielectric layer 1047.

[0102] In this example, the landing pads for the two devices are on the same side of the sidewall 1017. However, the present disclosure is not limited thereto. For example, the landing pads for the two devices can be on different sides of the sidewall 1017.

[0103] So far, the fabrication of the device base structure is completed. Subsequently, various contacts, interconnect structures, etc. can be fabricated.

[0104] For example, as shown in FIG. 24(a) and FIG. 24(b), a dielectric layer 1053 can be formed on the substrate, e.g., by deposition followed by planarization. Then, a contact hole can be formed and filled with a conductive material such as metal to form a contact 1055. The contact 1055 can include a contact to the upper end source / drain portion through the sidewall 1017 and the etch stop layer 1009, a contact to the contact region of the lower end source / drain portion through the dielectric layer 1053 and the isolation layer 1045, and a contact to the landing pad of the gate conductor layer 1049 through the dielectric layer 1053. As shown in FIG. 24(c) and FIG. 24(d), the contacts to the contact regions of the lower end source / drain portions of the two devices can be on opposite sides (the left and right sides in the figures) of the active region. Figure 24(a) 24(b) Figure 24(a) 24(b)

[0105] According to other embodiments of the present disclosure, the contacts to the contact regions of the lower end source / drain portions can be on opposite sides of the active region of the corresponding device as the contacts to the landing pads of the gate conductor layer of the corresponding device, as shown in FIG. 25(a) and FIG. 25(b). Figure 25

[0106] In the above embodiments, a surround gate device is formed. However, the present disclosure is not limited thereto. For example, two gate stacks separated from each other can be formed on opposite sides of the channel layer.​​​​​​​

[0107] Figures 26(a) to 32(b) The illustration schematically depicts some stages in the process of manufacturing a semiconductor device according to another embodiment of this disclosure. The differences between this embodiment and the embodiments described above will be primarily described below.

[0108] As described above Figures 1 to 3 The second material layer 1003 and the third material layer 1005 can be sequentially formed on the substrate 1001, and an etch stop layer 1009, a core pattern 1011 and a hard mask layer 1013 patterned as strips extending along the first direction can be formed on the third material layer 1005.

[0109] Unlike the embodiment described above, where sidewalls are formed directly on the sidewalls of the continuous core pattern 1011 (and hard mask layer 1013) in the first direction, this embodiment allows for the prior definition of the range of the active region of the device in the first direction.

[0110] For example, such as Figures 26(a) to 26(c) As shown, it can be done as follows Figure 3 Photoresist 1015' is formed on the structure shown (photoresist 1007 removed) and patterned by photolithography to occupy a certain area in a first direction, for example, as a strip extending along a second direction. Here, a plurality (e.g., 3) of adjacent active device regions in the first direction are shown, and correspondingly, a plurality (e.g., 3) of strip shapes of photoresist 1015' are shown (see FIG. 26(a), where only a portion of the strip shapes on the upper and lower sides are shown due to image limitations). The photoresist 1015' can be used as an etching mask to selectively etch the underlying layer sequentially by, for example, a vertical RIE. Etching can be performed into the substrate 1001, particularly the well regions therein, thereby forming a groove in the substrate 1001. The spacing between adjacent active device regions in the first direction, or the width of the groove between active device regions, is shown as W in the figure.

[0111] Then, as Figures 27(a) to 27(d) As shown, it can be combined, for example, as described above. Figure 4 As described above, sidewall 1017' is formed. In this embodiment, the thickness of the nitride deposited in the sidewall formation process can be greater than W / 2, so that the nitride can fill the groove and be retained during the anisotropic etching in the sidewall formation process. Thus, the sidewall 1017' formed in this way, in addition to the above-described combination, Figure 4In addition to the portions shown on the sidewalls of the mandrel pattern 1011 (and the hard mask layer 1013) extending in the first direction, there are also portions extending in the second direction (i.e., the portions filling into the recesses). The portions extending in the second direction can form a shield layer shielding the device active regions on opposite sides of the device active regions in the first direction from the subsequent processes, and can also serve as an isolation between adjacent device active regions in the first direction.

[0112] After that, the processes in the above embodiments can be substantially followed, except that there is no need to treat the opposite ends in the first direction. For example, as mentioned above in connection with Figures 9 to 20 the first active layer 1027 can be formed, and the second position retaining layer 1031 and the third position retaining layer 1041 can be formed on opposite sides of the first active layer 1027 in the second direction, respectively, with the sidewall 1033 formed on and under the second position retaining layer 1031 by means of the sidewall position defining layer 1029, and the sidewall 1043 formed on and under the third position retaining layer 1041 by means of the sidewall position defining layer 1039, resulting in a structure as shown in Figure 28(a) and 28(b) In this embodiment, the first position retaining layer 1021 on opposite sides of the active region in the first direction (there are the shield layers, i.e., the material of the sidewall 1017', on the two sides) is not formed.

[0113] In addition, the sidewall 1033 and the sidewall 1043 can be formed differently from each other, e.g., with different thicknesses and / or different materials, since they are formed in different steps, respectively. For example, the sidewall position defining layer 1029 and the sidewall position defining layer 1039 can be grown with different thicknesses, respectively, so that the sidewall 1033 and the sidewall 1043 formed therefrom can have different thicknesses.

[0114] As shown in FIG. 28(b), the second position retaining layer 1031 and the third position retaining layer 1041 are on opposite sides of the first active layer 1027 in the second direction, respectively, and define the positions of the gate stacks. The portions of the first active layer 1027 overlapping with the second position retaining layer 1031 and the third position retaining layer 1041 (or, the gate stacks) can serve as channel portions. In addition, in the first direction, the portions of the sidewall 1017' extending in the second direction can serve as isolation between device active regions.

[0115] The replacement gate process can also be performed.

[0116] As Figure 29As shown, the second and third position retaining layers 1031, 1041 can be removed by selective etching, and the side wall position defining layers 1029, 1039 exposed thereby can also be removed. The space for the gate stack, i.e., the space originally occupied by the second and third position retaining layers 1031, 1041 and the side wall position defining layers 1029, 1039, is thus freed. The gate stack (gate dielectric layer 1047 and first gate conductor layer 1049a) can be formed on the isolation layer 1045. The formation of the gate stack can be seen in the above description in connection with Figures 21(a) to 21(c) As shown, the second and third position retaining layers 1031, 1041 can be removed by selective etching, and the side wall position defining layers 1029, 1039 exposed thereby can also be removed. The space for the gate stack, i.e., the space originally occupied by the second and third position retaining layers 1031, 1041 and the side wall position defining layers 1029, 1039, is thus freed. The gate stack (gate dielectric layer 1047 and first gate conductor layer 1049a) can be formed on the isolation layer 1045. The formation of the gate stack can be seen in the above description in connection with

[0117] For the portions of the gate stack on opposite sides of the first active layer 1027 (which can also be referred to as first and second gate stacks, respectively), they can take the same configuration (e.g., have the same gate dielectric and gate conductor layers), or can take different configurations (e.g., have different gate dielectric and / or gate conductor layers) to optimize device performance.

[0118] For example, as shown in Figure 30 the gate stack on one side of the first active layer 1027 (e.g., the first gate stack) can be masked by the photoresist 1057, while the gate stack on the other side (e.g., the second gate stack) is exposed. The gate conductor layer (and optionally, the gate dielectric layer) of the exposed gate stack can be removed by selective etching. The photoresist 1057 can then be removed.

[0119] As shown in Figure 31 a second gate conductor layer 1049b can be additionally formed in the second gate stack by depositing and then etching back additional gate conductor material. The etching back of the additional gate conductor material is such that the additional gate conductor material at the first gate stack is removed, while remaining at the second gate stack. In the case where the gate dielectric layer 1047 at the second gate stack is also removed, an additional gate dielectric layer can also be formed.

[0120] Similarly, the gate conductor layer can also be broken between different devices according to device design, while the contact pads of the gate contacts can also be patterned.

[0121] For example, as shown in Figure 32(a) and 32(b)As shown, the first gate conductor layer 1049a and the second gate conductor layer 1049b can be patterned to extend mainly under the sidewall 1017' (the space originally occupied by the second position retaining layer 1031 and the third position retaining layer 1041) and have a protruding portion to serve as a landing pad for a gate contact.

[0122] Subsequently, various contacts, interconnection structures, etc. can be fabricated as described above, which will not be repeated here.

[0123] The semiconductor device according to the embodiments of the present disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such a semiconductor device, and an electronic device can be constructed therefrom. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device. The electronic device can further include a display screen cooperating with the integrated circuit, and a wireless transceiver cooperating with the integrated circuit, etc. Such electronic devices are, for example, a smart phone, a personal computer (PC), a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, a car electronic device, a communication device, or an Internet of Things (IoT) device, etc.

[0124] According to the embodiments of the present disclosure, a method for manufacturing a system on a chip (SoC) is also provided. The method can include the above-mentioned method. Specifically, a plurality of devices can be integrated on a chip, at least some of which are manufactured according to the method of the present disclosure.

[0125] In the above description, the technical details of patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0126] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a channel portion on a substrate, the channel portion comprising a curved nanosheet or nanowire having a C-shaped cross-section; a first source / drain portion and a second source / drain portion at opposite ends of the channel portion, respectively, relative to the substrate; a first gate stack and a second gate stack on opposite sides of the channel portion, the first gate stack and the second gate stack each comprising a gate dielectric layer and a gate conductor layer; a first sidewall between the gate dielectric layer of the first gate stack and the first source / drain portion and between the gate dielectric layer of the first gate stack and the second source / drain portion, respectively; and a second sidewall between the gate dielectric layer of the second gate stack and the first source / drain portion and between the gate dielectric layer of the second gate stack and the second source / drain portion, respectively.

2. The semiconductor device of claim 1, wherein, The first sidewall and the second sidewall have different thicknesses from each other.

3. The semiconductor device according to claim 1 or 2, wherein The first sidewall and the second sidewall comprise different dielectrics from each other.

4. The semiconductor device of claim 1, wherein, The first gate stack and the second gate stack form a gate stack around a periphery of the channel portion.

5. The semiconductor device of claim 4, wherein, The first sidewall and the second sidewall form a sidewall around the periphery of the channel portion.

6. The semiconductor device of claim 5, further comprising: a third sidewall and a fourth sidewall on opposite sides of the channel portion in a first direction, wherein the first sidewall and the second sidewall are on opposite sides in a second direction that intersects the first direction, wherein the first sidewall interfaces with the third sidewall and the fourth sidewall, respectively, and an interface exists at the interface, and the second sidewall interfaces with the third sidewall and the fourth sidewall, respectively, and an interface exists at the interface.

7. The semiconductor device of claim 6, wherein: portions of the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall on the gate stack are substantially coplanar, and portions of the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall under the gate stack are substantially coplanar.

8. The semiconductor device of claim 1, wherein, The first sidewall and the second sidewall are self-aligned to the opposite ends of the channel portion.

9. The semiconductor device of claim 1, wherein, The curved nanosheet or nanowire comprises a first sidewall and a second sidewall in the C-shape that open toward the same direction in a cross-section perpendicular to a substrate surface, the first sidewall and the second sidewall extending between source / drain portions at the opposite ends of the channel portion, the first gate stack overlapping the first sidewall and the second gate stack overlapping the second sidewall.

10. The semiconductor device of claim 9, wherein, The curved nanosheet or nanowire has a substantially uniform thickness or diameter.

11. The semiconductor device of claim 1, further comprising: an active layer extending substantially vertically, comprising a middle portion extending between an upper portion and a lower portion, the middle portion forming the curved nanosheet or nanowire; a first semiconductor layer on a sidewall of the upper portion of the active layer; and a second semiconductor layer on a sidewall of the lower portion of the active layer, wherein the first source / drain portion and the second source / drain portion comprise doped regions in the first semiconductor layer and the second semiconductor layer.

12. The semiconductor device of claim 11, wherein, The first semiconductor layer extends from a sidewall of an upper portion of the active layer toward a side away from the opening of the C-shape, and the second semiconductor layer extends from a sidewall of a lower portion of the active layer toward a side away from the opening of the C-shape.

13. The semiconductor device of claim 1, wherein, At least a portion of each of the first gate stack and the second gate stack near the channel portion is substantially coplanar with the channel portion.

14. The semiconductor device of claim 1, wherein, The channel portion and / or the source / drain portion comprises a single-crystal semiconductor material.

15. The semiconductor device of claim 1, wherein, There are a plurality of the semiconductor devices on the substrate, wherein the C-shapes of at least a pair of semiconductor devices face away from each other.

16. The semiconductor device of claim 1, wherein, The gate length of the first gate stack and the gate length of the second gate stack are substantially equal.

17. The semiconductor device of claim 1, wherein, The first sidewall extends laterally on the upper and lower surfaces of the first gate stack as a whole, and the second sidewall extends laterally on the upper and lower surfaces of the second gate stack as a whole.

18. The semiconductor device of claim 17, wherein, The first sidewall extends laterally beyond the first source / drain portion and the second source / drain portion in a direction away from the channel portion, and the second sidewall extends laterally beyond the first source / drain portion and the second source / drain portion in a direction away from the channel portion.

19. A method of manufacturing a semiconductor device, comprising: providing a stack of a first material layer, a second material layer, and a third material layer on a substrate; patterning the stack into a ridge-shaped structure, the ridge-shaped structure including a first side and a second side opposite to each other in a first direction and a third side and a fourth side opposite to each other in a second direction intersecting the first direction; on the third side and the fourth side, laterally recessing sidewalls of the second material layer relative to sidewalls of the first material layer and the third material layer, thereby defining second recesses; forming a channel layer on surfaces of the second material layer exposed by the second recesses; forming a second position-retaining layer in the second recesses and first sidewalls on upper and lower surfaces of the second position-retaining layer; forming source / drain portions in the first material layer and the third material layer; forming an opening in the ridge-shaped structure along the first direction, thereby dividing the ridge-shaped structure into two portions opposite to each other in the second direction; removing the second material layer through the opening; forming a third position-retaining layer in a space released due to the removal of the second material layer and second sidewalls on upper and lower surfaces of the third position-retaining layer; forming an isolation layer on the substrate; removing the second position-retaining layer and the third position-retaining layer; and forming a first gate stack and a second gate stack on the isolation layer on opposite sides of the channel layer in the second direction, each of the first gate stack and the second gate stack including a gate dielectric layer and a gate conductor layer, wherein the first sidewalls are between the gate dielectric layer of the first gate stack and the source / drain portions, and the second sidewalls are between the gate dielectric layer of the second gate stack and the source / drain portions.

20. The method of claim 19, wherein, The first sidewall and the second sidewall are formed to have different thicknesses.

21. The method of claim 19 or 20, wherein, Different dielectrics are used to form the first sidewall and the second sidewall.

22. The method of claim 19, further comprising: forming a masking material on the first side and the second side to mask the first side and the second side of the ridge-shaped structure.

23. The method of claim 19, further comprising: laterally recessing sidewalls of the second material layer relative to sidewalls of the first material layer and the third material layer on the first side and the second side to define a first recess; forming a first location retaining layer in the first recess and forming a third sidewall and a fourth sidewall on upper and lower surfaces of the first location retaining layer on the first side and the second side, respectively, wherein removing the second location retaining layer and the third location retaining layer further comprises removing the first location retaining layer, wherein the gate dielectric layer and the gate conductor layer enter spaces released due to removal of the first location retaining layer, the second location retaining layer, and the third location retaining layer.

24. The method of claim 23, wherein, forming the first location retaining layer, the second location retaining layer, and the third location retaining layer in each of the first recess, the second recess, and the space comprises: forming a sidewall location defining layer in a substantially conformal manner; in a respective one of the first recess, the second recess, and the space, forming a respective location retaining layer and selectively etching the sidewall location defining layer with the respective location retaining layer as a mask to release a space at upper and lower surfaces of the respective location retaining layer; and forming a respective sidewall in the released space, wherein removing the first location retaining layer, the second location retaining layer, and the third location retaining layer further comprises removing the sidewall location defining layer.

25. The method of claim 19, wherein, the first material layer is an upper portion of the substrate or an epitaxial layer on the substrate.

26. The method of claim 19, wherein, laterally recessing sidewalls of the second material layer comprises isotropic etching.

27. The method of claim 19, wherein, forming the channel layer comprises selective epitaxial growth.

28. The method of claim 19, wherein, the first sidewall extends laterally in its entirety on upper and lower surfaces of the second location retaining layer, and the second sidewall extends laterally in its entirety on upper and lower surfaces of the third location retaining layer.

29. The method of claim 19, further comprising: laterally recessing the source / drain portion such that the first sidewall extends laterally beyond the source / drain portion in a direction away from the channel layer, and the second sidewall extends laterally beyond the source / drain portion in a direction away from the channel layer.

30. An electronic device comprising the semiconductor device of any one of claims 1 to 18.

31. The electronic device of claim 30, comprising a personal computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, an automotive electronic device, a communication device, or an Internet of Things device.

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