A method, apparatus, and medium for SerDes problem detection

Abstract

The application relates to the technical field of data processing, and discloses a SerDes problem detection method and device and a medium. In the case that a SerDes link state meets a preset condition, a detection instruction is sent to a target chip; it is judged whether an error alarm is read from the target chip; if yes, the problem point is located according to the error alarm; if no, it is judged whether there is a problem in the SerDes physical link, and if yes, it is confirmed that the problem point is a physical link connection error. According to the technical scheme, when the SerDes has a problem, the processor sends a test instruction to the target chip, so that the target chip detects internally according to the instruction; when internal error information is detected, the processor realizes the location of the problem point by reading the error alarm. If it is not a chip internal problem, it is judged whether the SerDes problem is caused by a physical link connection error, so that the location of the problem is realized.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a SerDes problem detection method, apparatus, and medium. Background Technology

[0002] SerDes is short for Serializer / DeSerializer. It is a mainstream time-division multiplexing (TDM) point-to-point (P2P) serial communication technology. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through a medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiving end. This point-to-point serial communication technology fully utilizes the channel capacity of the transmission medium, reduces the required transmission channels and the number of device pins, increases signal transmission speed, and thus significantly reduces communication costs.

[0003] SerDes single-lane speeds can reach 30Gbps. In typical applications, we usually instantiate SerDes at Gigabit speeds. Therefore, the stability of SerDes operation is crucial. A problem in any part of the process can lead to data transmission errors. When SerDes malfunctions, we should quickly and accurately identify the problem. To ensure normal system operation, the entire system should be able to automatically diagnose the problem and self-heal when SerDes malfunctions.

[0004] Therefore, it is evident that how to detect SerDes problems is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a SerDes problem detection method, apparatus, and medium to detect SerDes problems, thereby avoiding data transmission errors and ensuring the reliability of link operation and the timeliness of error handling.

[0006] To address the aforementioned technical problems, this application provides a SerDes problem detection method, comprising:

[0007] If the SerDes link status is found to meet the preset conditions, a detection command is sent to the target chip;

[0008] Determine whether an error alarm is read from the target chip;

[0009] If so, locate the problem point based on the error alarm;

[0010] If not, then determine if there is a problem with the SerDes physical link. If there is, then confirm that the problem is a physical link connection error.

[0011] Preferably, the error alarm includes clock alarm and internal error message alarm.

[0012] Preferably, the clock alarm includes: clock loss alarm and clock frequency offset alarm;

[0013] Correspondingly, the clock loss alarm is: the target chip uses a preset clock to sample and detect the SerDes reference clock;

[0014] If no level change is detected within the preset time, a clock loss alarm will be issued;

[0015] Correspondingly, the clock frequency offset alarm is: the SerDes reference clock is downclocked by a preset factor;

[0016] The SerDes reference clock is sampled using the preset clock.

[0017] The high-level sampling point in the clock of the counting sampling;

[0018] The SerDes reference clock frequency is calculated based on the magnitude relationship between the sampling clock and the preset clock.

[0019] If the SerDes reference clock frequency does not match the standard frequency, a clock frequency deviation alarm will be issued.

[0020] Preferably, the internal error information alarm includes: the target chip determining whether the internal error information alarm is a false alarm;

[0021] If so, then the aforementioned internal error message alarm will not be reported;

[0022] If not, the internal error alarm will be reported after clock domain synchronization.

[0023] Preferably, determining whether there is a problem with the SerDes physical link includes:

[0024] Switch the data transmission link to the self-generated packet link;

[0025] Add PRBS codes to the sent messages;

[0026] Determine whether the PRBS codes in the sent and received messages are consistent;

[0027] If there is a discrepancy, it is confirmed that there is a problem with the SerDes physical link.

[0028] Preferably, in the event of a clock alarm being detected, the following additional steps are also included:

[0029] Reset the clock chip on the target chip and reset and restart SerDes;

[0030] Determine if the clock alarm is read again;

[0031] If so, the location of the problem will be determined based on the error alarm.

[0032] Preferably, it also includes

[0033] If the problem located by the internal error information alarm is that the CDR is out of lock, then the CDR is reset.

[0034] If the problem is identified as buffer overflow based on the internal error information alarm, then SerDes will be reset.

[0035] To address the aforementioned technical problems, this application also provides a SerDes problem detection device, comprising:

[0036] The sending module is used to send a detection command to the target chip when the SerDes link status is detected to meet the preset conditions;

[0037] The processing module is used to determine whether an error alarm is read from the target chip; if so, it locates the problem point based on the error alarm; if not, it determines whether there is a problem with the SerDes physical link; if so, it confirms that the problem point is a physical link connection error.

[0038] To address the aforementioned technical problems, this application also provides another SerDes problem detection device, including a memory for storing computer programs;

[0039] A processor, used to implement the steps of the SerDes problem detection method as described above when executing the computer program.

[0040] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the SerDes problem detection method described above.

[0041] The SerDes problem detection method provided in this application sends a detection command to the target chip when the SerDes link status meets preset conditions; it then determines whether an error alarm is read from the target chip; if so, it locates the problem point based on the error alarm; otherwise, it determines whether there is a problem with the SerDes physical link, and if so, confirms that the problem point is a physical link connection error. Using this technical solution, when a SerDes problem occurs, the processor sends a test command to the target chip, causing the target chip to perform internal detection according to the command. When internal error information is detected, the processor locates the problem point by reading the error alarm. If it is not an internal chip problem, it determines whether the SerDes problem is caused by a physical link connection error. Using the technical solution provided in this application, when the processor detects a SerDes problem, it detects the problem internally within the target chip; if no internal problem is found, it detects a problem with the physical connection link, thereby achieving SerDes problem detection and avoiding data output errors.

[0042] Furthermore, the SerDes problem detection device and medium provided in this application correspond to the SerDes problem detection method described above, and have the same effect. Attached Figure Description

[0043] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a SerDes architecture diagram;

[0045] Figure 2 A flowchart of a SerDes problem detection method provided in this application embodiment;

[0046] Figure 3 A SerDes application overall architecture diagram provided in this application embodiment;

[0047] Figure 4 A structural diagram of a SerDes problem detection device provided in an embodiment of this application;

[0048] Figure 5 This is a structural diagram of another SerDes problem detection device provided in an embodiment of this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0050] There are two ways to increase the transmission bandwidth of an interface: increasing the clock frequency and increasing the data bit width. As the frequency and data bit width increase, synchronous switching noise (SSN) becomes the main bottleneck for improving transmission bandwidth. One way to solve SSN is to use differential signaling instead of single-ended signaling. Differential signaling can effectively solve the SSN problem, but at the cost of using more chip pins. However, using differential signaling still cannot solve the data clock skew problem. The large bit width of the differential signal, coupled with strict timing constraints, poses a significant challenge to parallel interfaces.

[0051] The clock frequency of the source-synchronous interface has reached a bottleneck. Due to the non-ideal characteristics of the channel, further increasing the frequency will severely damage the signal, necessitating the use of equalization and data clock phase detection techniques. This is the technology employed by SerDes.

[0052] Figure 1 Here is a SerDes architecture diagram, such as Figure 1 As shown, SerDes is short for SERializer / DESerializer. The serializer is also called the SerDes transmitter (TX), and the deserializer is called the receiver (RX). SerDes is a mainstream time-division multiplexing (TDM) point-to-point (P2P) serial communication technology. At the transmitter, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through a medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiver. This point-to-point serial communication technology fully utilizes the channel capacity of the transmission medium, reduces the required transmission channels and the number of device pins, and increases signal transmission speed, thereby significantly reducing communication costs. SerDes does not transmit clock signals, which is its most distinctive feature. SerDes integrates a CDR (Clock Data Recovery) circuit at the receiver, using the CDR to extract the clock from the edge information of the data and find the optimal sampling position.

[0053] SerDes single-lane speeds can reach 30Gbps. In typical applications, we usually instantiate SerDes at Gigabit speeds. Therefore, the stability of SerDes operation is crucial. A problem in any part of the process can lead to data transmission errors. When SerDes malfunctions, we should quickly and accurately identify the problem. To ensure normal system operation, the entire system should be able to automatically diagnose the problem and self-heal when SerDes malfunctions.

[0054] Therefore, it is evident that how to detect SerDes problems is a problem that urgently needs to be solved by those skilled in the art.

[0055] The core of this application is to provide a SerDes problem detection method, apparatus, and medium to detect SerDes problems, thereby avoiding data transmission errors and ensuring the reliability of link operation and the timeliness of error handling.

[0056] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Figure 2 A flowchart of a SerDes problem detection method provided in this application embodiment is shown below. Figure 1 As shown, the method includes:

[0058] S10: If the SerDes link status is found to meet the preset conditions, a detection command is sent to the target chip.

[0059] S11: Determine whether an error alarm is read from the target chip; if yes, proceed to step S12; if no, proceed to step S13.

[0060] S12: Locate the problem based on the error alarm.

[0061] S13: Determine if there is a problem with the SerDes physical link. If so, confirm that the problem is a physical link connection error.

[0062] First, it should be noted that the execution entity of the SerDes problem detection method in this embodiment can be a SerDes problem detection device or a central processing unit (CPU), which implements the entire system's computation, control, information processing, and program execution. To facilitate understanding of this solution, the following explanation will be based on specific SerDes usage scenarios. Figure 3 A SerDes application overall architecture diagram provided for embodiments of this application, such as... Figure 3As shown, in this system, the communication channels between target chip A and chip B are the SerDes channel. The CPU controls target chip A through the local bus, and information from inside target chip A is also reported to the CPU through the local bus. The local bus is also known as the CPU bus, and based on the difference in the high and low address line order, it can be divided into Motorola CPU bus and Intel CPU bus.

[0063] The preset condition in this embodiment refers to the situation where the SerDes link will generate an error report or the link will directly go down. In specific implementation, when a problem occurs in SerDes, the SerDes link will generate an error report or the link will directly go down. When the CPU detects this situation, it sends a detection command to target chip A. Target chip A can then perform internal detection according to the command. After detecting an internal problem, it will report the corresponding error alarm to the hreg module. The CPU can locate the problem point by reading the alarm in the hreg module. If the problem is not internal to the chip, it is necessary to check whether there is a problem with the physical link of SerDes, and determine whether the physical link connection between chip A and chip B is incorrect.

[0064] In this embodiment, the target chip A detects internal problems by including clock detection and internal error information detection. Correspondingly, the error alarms include clock alarms and internal error information alarms. Specifically, as shown... Figure 3 As shown, target chip A includes a CLK_DET module and a Buffer_det module. The CLK_DET module is the clock detection module, used to detect the reference clock of SerDes. It mainly includes two functions: the first part is to detect the presence or absence of the reference clock, and the second part is to perform qualitative detection of the reference clock frequency. Reference clock loss and excessive reference clock frequency deviation are both causes of SerDes malfunction. Correspondingly, clock alarms include: clock loss alarm and clock frequency deviation alarm; specifically, the clock loss alarm is triggered when the target chip samples the SerDes reference clock using a preset clock; if no level change is detected within a preset time, a clock loss alarm is issued.

[0065] The clock frequency deviation alarm is triggered as follows: the SerDes reference clock is downclocked by a preset factor; the SerDes reference clock is sampled using the preset clock; the high-level sampling points in the sampled clock are counted; the SerDes reference clock frequency is calculated based on the relationship between the sampled clock and the preset clock; if the SerDes reference clock frequency does not match the standard frequency, a clock frequency deviation alarm is issued.

[0066] This module uses a separate 100MHz reference clock. When detecting the presence or absence of the SerDes reference clock, it samples the SerDes reference clock using the 100MHz clock. If a level change is detected within 100ms, the SerDes reference clock is considered present. When performing frequency offset testing on the SerDes reference clock, the reference clock is first divided by a factor of 100. Then, the 100MHz clock is used to sample the down-clocked clock. The high-level sampling points of the down-clocked clock are counted, allowing the approximate relationship between the down-clocked clock and the 100MHz clock to be calculated. Based on this relationship, the down-clocked clock frequency is qualitatively calculated, then multiplied by 100 to obtain the reference clock frequency, thus enabling the detection of clock frequency offset.

[0067] The Buffer_det module primarily handles and reports alarms generated internally by SerDes. Another reason for SerDes malfunction is internal FIFO overflow or CDR lock loss, which generates corresponding alarms. The Buffer_det module processes these alarms. During processing, the module first performs false alarm screening; if a alarm is a false alarm, it is not reported. Then, it synchronizes the alarm signal in the clock domain and reports it to the hreg module. The CPU reads the alarm information from hreg via the local bus. Internal error alarms include: the target chip determines whether the internal error alarm is a false alarm; if so, it does not report it; if not, it synchronizes the internal error alarm in the clock domain before reporting it.

[0068] Correspondingly, if the problem is located by the internal error message alarm and the CDR is out of lock, then the CDR is reset; if the problem is located by the internal error message alarm and the buffer overflows, then the SerDes is reset.

[0069] The SerDes problem detection method provided in this application sends a detection command to the target chip when the SerDes link status meets preset conditions; it then determines whether an error alarm is read from the target chip; if so, it locates the problem point based on the error alarm; otherwise, it determines whether there is a problem with the SerDes physical link, and if so, confirms that the problem point is a physical link connection error. Using this technical solution, when a SerDes problem occurs, the processor sends a test command to the target chip, causing the target chip to perform internal detection according to the command. When internal error information is detected, the processor locates the problem point by reading the error alarm. If it is not an internal chip problem, it determines whether the SerDes problem is caused by a physical link connection error. Using the technical solution provided in this application, when the processor detects a SerDes problem, it detects the problem internally within the target chip. If no internal problem is found, it detects a problem with the physical connection link, thereby achieving SerDes problem detection, avoiding data output errors, and ensuring the reliability of link operation and the timeliness of error handling.

[0070] The target chip A also includes the Pkt_gen module, which is a sub-packet sending module. Its function is to generate the required packets according to the configuration. In specific implementations, the number and length of packets can be configured via the CPU. Simultaneously, this module can also work with chip loopback to send and receive packets, comparing the sent and received packets to determine if there are any problems with the link.

[0071] Additionally, this module can be configured to send PRBS codes specifically for testing SerDes links. PRBS verification is the reverse process of PRBS generation. Specifically, the transceiver receiver first stores one clock cycle of received data (parallel data), encodes the stored data using PRBS, and compares the encoded data with the latest received data. If they match, the PRBS verification is successful.

[0072] Specifically, determining if there is a problem with the SerDes physical link includes: switching the data transmission link to the self-sending packet link; adding PRBS codes to the sent packets; checking if the PRBS codes in the sent and received packets are consistent; if they are inconsistent, then a problem with the SerDes physical link is confirmed. Furthermore, the CPU can also print physical link error alarms to remind maintenance personnel to manually check whether there are physical errors in the connection path.

[0073] Understandably, in practice, normal data processing takes place in the Data_proc module. Pkt_gen and Data_proc are mutually exclusive on the data path. When a problem occurs, the data path switches to the Pkt_gen module to test the link connection.

[0074] In this embodiment, when a problem occurs in SerDes, the CPU detects an error in the link or the link goes down directly. It then activates the CLK_det module to detect the SerDes clock. If clock loss or excessive clock frequency deviation is detected, the clock chip on the board is reset. 200ms after the clock chip reset, SerDes is reset and restarted, and a reference clock fault error log is recorded. If the clock is normal, the next step of detection is performed. The CPU reads the internal error information of SerDes reported by Buffer_det. If a CDR lockout is found, the CDR is reset. If a buffer overflow is found, SerDes is reset, and the SerDes fault is recorded in the error log. If neither a reference clock error nor an error is reported by buffer_det, the CPU switches the data link from normal data processing to the self-transmitting packet module, configures the outer loop of the peer chip, and the self-transmitting packet module prints PRBS codes on the link. If a PRBS detection error occurs, the CPU prints a physical link error alarm, requiring maintenance personnel to manually check whether a physical error has occurred in the connection path.

[0075] The SerDes problem detection method has been described in detail in the above embodiments. This application also provides embodiments corresponding to the SerDes problem detection device. It should be noted that this application describes the embodiments of the device part from two perspectives: one is based on the functional modules, and the other is based on the hardware.

[0076] Figure 4 A structural diagram of a SerDes problem detection device provided in an embodiment of this application is shown below. Figure 4 As shown, the device includes:

[0077] The sending module 10 is used to send a detection command to the target chip when the SerDes link status is detected to meet the preset conditions;

[0078] Processing module 11 is used to determine whether an error alarm is read from the target chip; if so, it locates the problem based on the error alarm; if not, it determines whether there is a problem with the SerDes physical link; if so, it confirms that the problem is a physical link connection error.

[0079] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0080] It should be noted that, Figure 4 The structure shown does not constitute a limitation on the SerDes problem detection device. In other embodiments, the SerDes problem detection device may include more or fewer modules. For example, it may also include a configuration module for configuring the number and length of messages generated by the target chip A.

[0081] The SerDes problem detection device provided in this application sends a detection command to the target chip when the SerDes link status meets preset conditions; it then determines whether an error alarm is read from the target chip; if so, it locates the problem point based on the error alarm; otherwise, it determines whether there is a problem with the SerDes physical link, and if so, confirms that the problem point is a physical link connection error. Using this technical solution, when a SerDes problem occurs, the processor sends a test command to the target chip, causing the target chip to perform internal detection according to the command. When internal error information is detected, the processor locates the problem point by reading the error alarm. If it is not an internal chip problem, it determines whether the SerDes problem is caused by a physical link connection error. Using the technical solution provided in this application, when the processor detects a SerDes problem, it detects the problem internally within the target chip; if no internal problem is found, it detects a problem with the physical connection link, thereby achieving the detection of SerDes problems and avoiding data output errors.

[0082] Figure 5 A structural diagram of another SerDes problem detection device provided in the embodiments of this application is shown below. Figure 5 As shown, the device includes: a memory 20 for storing computer programs;

[0083] The processor 21 is used to implement the steps of the SerDes problem detection method as described in the above embodiment when executing a computer program.

[0084] The SerDes problem detection device provided in this embodiment can include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0085] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0086] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the SerDes problem detection method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, error alarms.

[0087] In some embodiments, the SerDes problem detection device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0088] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on the SerDes problem detection device and may include more or fewer components than shown.

[0089] The SerDes problem detection device provided in this application includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: when the SerDes link status is detected to meet the preset conditions, a detection command is sent to the target chip; it is determined whether an error alarm is read from the target chip; if so, the problem location is located according to the error alarm; if not, it is determined whether there is a problem with the SerDes physical link; if so, the problem location is confirmed to be a physical link connection error.

[0090] The SerDes problem detection device provided in this application sends a detection command to the target chip when the SerDes link status meets preset conditions; it then determines whether an error alarm is read from the target chip; if so, it locates the problem point based on the error alarm; otherwise, it determines whether there is a problem with the SerDes physical link, and if so, confirms that the problem point is a physical link connection error. Using this technical solution, when a SerDes problem occurs, the processor sends a test command to the target chip, causing the target chip to perform internal detection according to the command. When internal error information is detected, the processor locates the problem point by reading the error alarm. If it is not an internal chip problem, it determines whether the SerDes problem is caused by a physical link connection error. Using the technical solution provided in this application, when the processor detects a SerDes problem, it detects the problem internally within the target chip; if no internal problem is found, it detects a problem with the physical connection link, thereby achieving the detection of SerDes problems and avoiding data output errors.

[0091] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiments.

[0092] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0093] The computer-readable storage medium provided in this application, when detecting that the SerDes link status meets preset conditions, sends a detection command to the target chip; determines whether an error alarm is read from the target chip; if so, it locates the problem point based on the error alarm; if not, it determines whether there is a problem with the SerDes physical link; if so, it confirms that the problem point is a physical link connection error. Using this technical solution, when a problem occurs in SerDes, the processor sends a test command to the target chip, causing the target chip to perform internal detection according to the command. When internal error information is detected, the processor locates the problem point by reading the error alarm. If it is not an internal chip problem, it determines whether the SerDes problem is caused by a physical link connection error. Using the technical solution provided in this application, when the processor detects a SerDes problem, it detects the problem internally in the target chip; if no internal problem is found, it detects a problem with the physical connection link, thereby realizing the detection of SerDes problems and avoiding data output errors.

[0094] The SerDes problem detection method, apparatus, and medium provided in this application have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0095] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A SerDes problem detection method, characterized in that, include: If the SerDes link status is found to meet the preset conditions, a detection command is sent to the target chip; The preset conditions refer to situations where the SerDes link will generate error messages or the link will go directly down. Determine whether an error alarm is read from the target chip; the error alarm includes clock alarm and internal error message alarm; the internal error message alarm includes CDR lockout and buffer overflow; If so, locate the problem point based on the error alarm; If not, determine if there is a problem with the SerDes physical link. If there is, confirm that the problem is a physical link connection error. The internal error message alarms include: The target chip determines whether the internal error message alarm is a false alarm; If so, then the aforementioned internal error message alarm will not be reported; If not, the internal error alarm will be reported after clock domain synchronization; The determination of whether there is a problem with the SerDes physical link includes: Switch the data transmission link to the self-generated packet link; Add PRBS codes to the sent messages; Determine whether the PRBS codes in the sent and received messages are consistent; If there is a discrepancy, it is confirmed that there is a problem with the SerDes physical link.

2. The SerDes problem detection method according to claim 1, characterized in that, The clock alarms include: clock loss alarm and clock frequency deviation alarm; The clock loss alarm is as follows: the target chip uses a preset clock to sample and detect the SerDes reference clock; If no level change is detected within the preset time, a clock loss alarm will be issued; The clock frequency offset alarm is: the SerDes reference clock is downclocked by a preset factor; The SerDes reference clock is sampled using the preset clock. The high-level sampling point in the clock of the counting sampling; The SerDes reference clock frequency is calculated based on the magnitude relationship between the sampling clock and the preset clock. If the SerDes reference clock frequency does not match the standard frequency, a clock frequency deviation alarm will be issued.

3. The SerDes problem detection method according to claim 1, characterized in that, In the event of a clock alarm being detected, the following is also included: Reset the clock chip on the target chip and reset and restart SerDes; Determine if the clock alarm is read again; If so, the location of the problem will be determined based on the error alarm.

4. The SerDes problem detection method according to claim 1, characterized in that, Also includes If the problem located by the internal error information alarm is that the CDR is out of lock, then the CDR is reset. If the problem is identified as buffer overflow based on the internal error information alarm, then SerDes will be reset.

5. A SerDes problem detection device, characterized in that, include: The sending module is used to send a detection command to the target chip when the SerDes link status is detected to meet the preset conditions; The preset conditions refer to situations where the SerDes link will generate error messages or the link will go directly down. The processing module is used to determine whether an error alarm is read from the target chip; if so, it locates the problem based on the error alarm. If not, determine if there is a problem with the SerDes physical link. If there is, confirm that the problem is a physical link connection error. The error alarms include clock alarms and internal error message alarms; internal error message alarms include CDR lockout and buffer overflow; The internal error message alarms include: The target chip determines whether the internal error message alarm is a false alarm; If so, then the aforementioned internal error message alarm will not be reported; If not, the internal error alarm will be reported after clock domain synchronization; The determination of whether there is a problem with the SerDes physical link includes: Switch the data transmission link to the self-generated packet link; Add PRBS codes to the sent messages; Determine whether the PRBS codes in the sent and received messages are consistent; If there is a discrepancy, it is confirmed that there is a problem with the SerDes physical link.

6. A SerDes problem detection device, characterized in that, Includes memory used to store computer programs; A processor, configured to implement the steps of the SerDes problem detection method as described in any one of claims 1 to 4 when executing the computer program.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the SerDes problem detection method as described in any one of claims 1 to 4.

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