An air gap preparation method, a dynamic random access memory, and an electronic device

Abstract

The present invention discloses a method for preparing an air gap, a dynamic random access memory, and an electronic device, including: depositing a first capping layer on the upper end surface of a node contact layer, the top of a first bit line spacer layer, the top of a second bit line spacer layer, the top of an oxide layer, and the upper end surface of an insulating layer; etching downward to remove the part above the horizontal line where the top of the oxide layer is located; forming a first oxide layer on the etched plane; etching to remove the first oxide layer part on the top of the oxide layer on the first side of each bit line, the top of the first bit line spacer layer on the first side, and the top of the second bit line spacer layer on the first side, and retaining the first oxide layer part on the top of the oxide layer on the second side of each bit line, the top of the first bit line spacer layer on the second side, and the top of the second bit line spacer layer on the second side, and determining the retained first oxide layer part as an oxide layer pattern; depositing a second capping layer at the position of the removed first oxide layer part; and removing the oxide layer pattern and the oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor production, and in particular to an air gap preparation method, a dynamic random access memory and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) consists of multiple storage cells. Each storage cell consists of a storage capacitor, a transistor, a bit line, and a word line. The voltage V BL The capacitance C of the bit line BL Inversely proportional, in order to increase the voltage V BL value, it is necessary to reduce the capacitance C BL The parasitic capacitance formed between the bit line and the storage capacitor accounts for C BL More than 60 percent of the bit line capacitance is usually achieved by improving the parasitic capacitance by improving the relative dielectric constant and replacing the oxide layer on the sidewall of the bit line with air.

[0003] In the prior art, when preparing the air gap, after metal deposition on the top of the oxide layer, the oxide layer is directly etched downward from the top of the deposited metal to form an air gap at the position of the oxide layer, and the oxide layer is replaced by the air gap. However, during the deposition process, a layer of titanium nitride is generated at the contact surface with the deposited metal including the top of the oxide layer, which is easy to cause the landing pad to bridge during the etching process, and if the etching is excessive, it is easy to cause the landing pad to shrink. Summary of the invention

[0004] In order to solve the problem that the method of preparing air gaps in the existing dynamic random access memory is prone to causing ground pad bridging and ground pad reduction, the embodiments of the present invention provide an air gap preparation method, a dynamic random access memory and an electronic device.

[0005] In a first aspect, an embodiment of the present invention provides an air gap preparation method, which is applied to a dynamic random access memory, wherein the dynamic random access memory includes a semiconductor substrate with bit lines and word lines, a first bit line spacer layer arranged on the sidewalls of both sides of the bit line, an oxide layer arranged on the sidewalls of the first bit line spacer layer, and an insulating layer arranged on the top of the bit line, a node contact layer is arranged on the surface of the semiconductor substrate, and the dynamic random access memory further includes a second bit line spacer layer, and the oxide layer is located between the first bit line spacer layer and the second bit line spacer layer. The method includes:

[0006] Depositing a first covering layer on the upper end surface of the node contact layer, the top of the first bit line spacer layer, the top of the second bit line spacer layer, the top of the oxide layer and the upper end surface of the insulating layer, and forming a thin film layer on the lower end surface of the first covering layer;

[0007] After the first covering layer is ground until it is flush with the upper end surface of the thin film layer on the top of the insulating layer, the portion above the horizontal line where the top of the oxide layer is located is removed downward by etching to expose the top of the oxide layer;

[0008] forming a first oxide layer on the etched plane;

[0009] Etching the first oxide layer to remove the first oxide layer portion at the top of the oxide layer on the first side of each bit line, the top of the first bit line spacer on the first side, and the top of the second bit line spacer on the first side, and retaining the first oxide layer portion at the top of the oxide layer on the second side of each bit line, the top of the first bit line spacer on the second side, and the top of the second bit line spacer on the second side, and determining the retained first oxide layer portion as an oxide layer pattern;

[0010] Depositing a second covering layer at the position where the first oxide layer portion is removed, wherein the upper surface of the second covering layer is flush with the upper end surface of the oxide layer pattern;

[0011] The oxide layer pattern and the oxide layer are removed to form an air space at the oxide layer position.

[0012] In a possible implementation manner, a bit line contact is provided between the semiconductor substrate and the bit line, and an active region and an isolation structure between adjacent active regions are provided on the semiconductor substrate.

[0013] In a possible implementation manner, the first covering layer and the second covering layer finally formed together constitute a floor cushion.

[0014] In a possible implementation manner, a wet etching process is used to remove the oxide layer pattern and the oxide layer.

[0015] In a possible implementation manner, etching the first oxide layer specifically includes:

[0016] A hard mask is formed on the upper surface of the first oxide layer, and after a third covering layer is deposited on the upper surface of the hard mask, the first oxide layer is etched.

[0017] In a possible implementation manner, the step of making the upper surface of the second covering layer flush with the upper end surface of the oxide layer pattern comprises:

[0018] The upper surface of the second covering layer is polished to the same level as the upper end surface of the oxide layer pattern by a chemical mechanical polishing process.

[0019] In a possible implementation manner, the first oxide layer and the oxide layer are made of the same material.

[0020] In a possible implementation manner, the first oxide layer is made of silicon oxide.

[0021] In a possible implementation manner, the first covering layer and the second covering layer are both made of tungsten.

[0022] In a possible implementation manner, the third covering layer is made of silicon oxynitride.

[0023] In a possible implementation manner, etching downward from the top of the first covering layer to remove a portion above a horizontal line where the top of the oxide layer is located specifically includes:

[0024] A dry etching process is adopted to etch downward from the top of the first covering layer to remove the portion above the horizontal line where the top of the oxide layer is located.

[0025] In a second aspect, an embodiment of the present invention provides a dynamic random access memory, which is a semiconductor structure prepared by the air gap preparation method provided by an embodiment of the present invention.

[0026] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the dynamic random access memory provided by an embodiment of the present invention.

[0027] The air gap preparation method provided by the embodiment of the present invention is applied to a dynamic random access memory. The dynamic random access memory structure includes a semiconductor substrate with a bit line and a word line, a first bit line spacer layer arranged on the side walls of both sides of the bit line, an oxide layer arranged on the side walls of the first bit line spacer layer, and an insulating layer arranged on the top of the bit line. A node contact layer is arranged on the surface of the semiconductor substrate. The dynamic random access memory also includes a second bit line spacer layer. The oxide layer is located between the first bit line spacer layer and the second bit line spacer layer. When preparing the air gap, a first covering layer is deposited on the upper surface of the node contact layer, the top of the first bit line spacer layer, the top of the second bit line spacer layer, the top of the oxide layer, and the upper end surface of the insulating layer at the top of the bit line. A thin film layer is generated on the lower end surface of the first covering layer. After the first covering layer is ground to be flush with the upper end surface of the thin film layer at the top of the insulating layer, the portion above the horizontal line with the position of the top of the oxide layer as the horizontal line is removed downwardly to expose the top of the oxide layer. Then, a first oxide layer is formed on the plane exposed after etching. The first oxide layer is etched to remove one of the first and second bit line spaces. The first oxide layer portion on the top of the oxide layer on the side of each bit line is removed, the first oxide layer portion on the top of the oxide layer on the other side of each bit line is retained, and the retained first oxide layer portion on the top of the oxide layer on the other side of each bit line is determined as an oxide layer pattern, and then, a second covering layer is deposited at the position of the removed first oxide layer portion, so that the upper surface of the second covering layer is flush with the upper end surface of the oxide layer pattern, so as to fill the position where the first oxide layer portion is removed with the second covering layer, and the oxide layer pattern and the oxide layer are removed together to form an air gap at the oxide layer position to replace the oxide layer. In the embodiment of the present invention, an oxide layer pattern is formed on the top of the first bit line spacer layer, the top of the oxide layer, and the top of the second bit line spacer layer on one side of each bit line, and a second covering layer is deposited between the oxide layer patterns, so that the finally formed second covering layer and the first covering layer together constitute a landing pad, and the oxide layer pattern separates adjacent landing pads, thereby avoiding the problem of short circuit caused by bridging of landing pads generated when making air gaps, and avoiding the problem of reduction of landing pads because the width of the landing pads can be reduced at the same time.

[0028] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0030] Figure 1A cross-sectional view of a dynamic random access memory structure corresponding to metal deposition on top of the oxide layer before removing the oxide layer in the dynamic random access memory;

[0031] Figure 2 It is a cross-sectional view of a dynamic random access memory structure corresponding to the removal of the oxide layer in the prior art;

[0032] Figure 3 A schematic diagram of an implementation flow of an air gap preparation method provided in an embodiment of the present invention;

[0033] Figure 4 A cross-sectional view of the initial structure of a dynamic random access memory in an embodiment of the present invention;

[0034] Figures 5 to 11 A cross-sectional view of a dynamic random access memory structure corresponding to each step of the air gap preparation method provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In the existing dynamic random access memory, when preparing air gaps on both sides of the bit line, metal is deposited on the top of the oxide layer, and then etching is performed directly from the top of the deposited metal downward to form a landing pad, and then the oxide layer is removed to form an air gap at the position of the oxide layer, and the oxide layer is replaced by the air gap. However, during the deposition process, the deposited metal (the metal can be tungsten, such as tungsten) on the top of the oxide layer is formed. Figure 1 A layer of titanium nitride (such as Figure 1 11), before removing the oxide layer (such as Figure 1 In the prior art, after etching downward directly from the upper end of the deposited metal to form a landing pad, the oxide layer is removed to form an air gap to replace the oxide layer, such as Figure 2 As shown, after the etching is completed, the titanium nitride is still in contact with the top of the oxide layer on one side of the bit line, which can easily cause the landing pad 101 to bridge (such as Figure 2 LP Bridge position indicated in FIG. 1 ), and excessive etching may easily cause the landing pad 101 to shrink (eg Figure 2 In order to solve the above problems, the embodiments of the present invention provide an air gap preparation method, a dynamic random access memory and an electronic device.

[0036] The preferred embodiments of the present invention are described below in conjunction with the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other if there is no conflict.

[0037] like Figure 3As shown, it is a schematic diagram of the implementation process of the air gap preparation method provided in an embodiment of the present invention. The air gap preparation method is applied to a dynamic random access memory. In an embodiment of the present invention, before preparing the air gap, the initial structure cross-section of the dynamic random access memory is as shown in FIG. Figure 4 As shown, the dynamic random access memory includes a semiconductor substrate 20 with a bit line 21 and a word line (wherein the word line is not shown in the cross-sectional view), a first bit line spacer 22 arranged on the sidewalls of both sides of the bit line 21, an oxide layer 23 arranged on the sidewalls of the first bit line spacer 22, and an insulating layer 24 arranged on the top of the bit line 21. A node contact layer 25 is arranged on the surface of the semiconductor substrate 20. The dynamic random access memory also includes a second bit line spacer 26. The oxide layer 23 is located between the first bit line spacer 22 and the second bit line spacer 26. A bit line contact (Bit Line Contact, BLC) 27 is arranged between the semiconductor substrate 20 and the bit line 21. An active region (Active Area, AA) 28, an isolation structure 29 located between adjacent active areas 28 is also provided in the semiconductor substrate 20, wherein the material of the semiconductor substrate 20 can be silicon, the material of the first bit line spacer 22 and the second bit line spacer 26 can be nitride, such as silicon nitride, the material of the oxide layer 23 is oxide, such as silicon oxide, and the structure composed of the first bit line spacer 22, the oxide layer 23, and the second bit line spacer 26 can be called a NON structure; the insulating layer 24 is an insulating material, which is used to protect the bit line 21 located thereunder; the node contact layer 25 can realize the electrical connection between the landing pad and the active area 28, which includes polysilicon. The material of the bit line contact 27 is a conductive material, which is used to contact and conduct with the bit line 21; the isolation structure 29 is used to isolate multiple active areas 28 in the semiconductor substrate 20.

[0038] The air gap preparation method may include the following steps:

[0039] S11, depositing a first covering layer on the upper end surface of the node contact layer, the top of the first bit line spacer layer, the top of the second bit line spacer layer, the top of the oxide layer and the upper end surface of the insulating layer, and forming a thin film layer on the lower end surface of the first covering layer.

[0040] When implementing it, Figure 5As shown, a first covering layer 210 is deposited on the upper end surface of the node contact layer 25, the top of the first bit line spacer layer 22, the top of the second bit line spacer layer 26, the top of the oxide layer 23 and the upper end surface of the insulating layer 24. The material of the first covering layer 210 can be but is not limited to metal tungsten. After the deposition is completed, a thin film layer is generated on the lower end surface of the first covering layer 210, that is, a thin film layer is formed at the contact position between the first covering layer 210 and the upper end surface of the node contact layer 25, the top of the first bit line spacer layer 22, the top of the second bit line spacer layer 26, the top of the oxide layer 23 and the upper end surface of the top of the insulating layer 24, namely: titanium nitride film 211.

[0041] S12, after grinding the first covering layer until it is flush with the upper end surface of the thin film layer on the top of the insulating layer, etching downward to remove the portion above the horizontal line where the top of the oxide layer is located, so as to expose the top of the oxide layer.

[0042] In specific implementation, the first cover layer can be ground from top to bottom by chemical mechanical grinding process until it is flush with the upper end surface of the titanium nitride film 211 on the top of the insulating layer 24. After grinding, the structure is as follows: Figure 6 As shown; then, the portion above the horizontal line where the top of the oxide layer 23 is located is etched downward, that is, the portion of the insulating layer 24 and the first covering layer 210 and the titanium nitride film 211 above the horizontal line where the top of the oxide layer 23 is located are removed to expose the top of the oxide layer 23. The structure after etching is as shown Figure 7 As shown, in this step, the etching can be performed by using, but not limited to, a dry etching process. Figure 7 It can be seen that after the etching is completed, the titanium nitride film 211 between the oxide layers 23 on both sides of each bit line 21 is removed, while the titanium nitride film 211 between the adjacent oxide layers 23 in the oxide layers 23 on the side walls of every two adjacent bit lines 21 is retained.

[0043] S13, forming a first oxide layer on the etched plane.

[0044] When implementing it, Figure 8 As shown, a first oxide layer 212 is formed on the plane exposed after etching, that is, taking the horizontal line at the top of the oxide layer 23 as a reference, the first oxide layer 212 is formed above the horizontal line, that is: taking the horizontal line at the top of the oxide layer 23 as a reference, the first oxide layer 212 is formed on the top of the oxide layer 23, the upper end surface of the remaining part of the first cover layer 210, the top of the first bit line spacer 22, the top of the second bit line spacer 26 and the upper end surface of the remaining part of the insulating layer 24. In the embodiment of the present invention, the material of the first oxide layer 212 is oxide, and the material of the first oxide layer 212 can be the same as that of the oxide layer 23, such as silicon oxide; the material of the first oxide layer 212 can also be other types of oxides different from the material of the oxide layer 23, and the embodiment of the present invention is not limited to this.

[0045] S14, etching the first oxide layer to remove the first oxide layer portion on the first side of each bit line, the first bit line spacer layer top on the first side, and the second bit line spacer layer top on the first side, retaining the first oxide layer portion on the second side of each bit line, the first bit line spacer layer top on the second side, and the second bit line spacer layer top on the second side, and determining the retained first oxide layer portion as an oxide layer pattern.

[0046] In a specific implementation, when etching the first oxide layer 212, the etching method is as follows: Fig. 9A As shown, a hard mask (HM) 213 is formed on the upper surface of the first oxide layer 212, and after the third covering layer 214 is deposited on the upper surface of the hard mask 213, a target pattern to be etched is exposed on the third covering layer 214 through a photoresist 214-1, and then the third covering layer 214 and the hard mask 213 are etched through an etching process until the first oxide layer 212 is etched according to the exposed target pattern. The material of the third covering layer 214 can be silicon oxynitride SiON.

[0047] The etching results are as follows Fig. 9B As shown, the first oxide layer 212 portion at the top of the oxide layer 23 on the first side of each bit line 21, the top of the first bit line spacer 22 on the first side, and the top of the second bit line spacer 26 on the first side is removed by etching, and the first oxide layer 212 portion at the top of the oxide layer 23 on the second side of each bit line 21, the top of the first bit line spacer 22 on the second side, and the top of the second bit line spacer 26 on the second side is retained, and the retained first oxide layer 212 portion is determined as an oxide layer pattern 212-1, that is, for each bit line 21, the first oxide layer 212 (i.e., the oxide layer pattern 212-1) is retained on the top of the NON structure (i.e., the first bit line spacer 22, the oxide layer 23, the second bit line spacer 26) on one side thereof to protect the oxide layer 23.

[0048] S15, depositing a second covering layer at the position where the first oxide layer portion is removed, wherein the upper surface of the second covering layer is flush with the upper end surface of the oxide layer pattern.

[0049] When implementing it, Fig.10 As shown, Fig. 9B The second covering layer 215 is deposited at the position of the first oxide layer 212 removed in the process. The material of the second covering layer 215 can be the same as that of the first covering layer 210, that is, both can be metal tungsten. The first covering layer 210 and the second covering layer 215 formed finally together constitute a landing pad.

[0050] During implementation, the upper surface of the second covering layer 215 can be made flush with the upper end surface of the oxide layer pattern 212-1 by:

[0051] The upper surface of the second cover layer 215 is polished to the same level as the upper end surface of the oxide layer pattern 212 - 1 by chemical mechanical polishing (CMP).

[0052] S16, removing the oxide layer pattern and the oxide layer to form an air gap at the oxide layer position.

[0053] In a specific implementation, the oxide layer pattern 212-1 and the oxide layer 23 are etched from top to bottom to remove the oxide layer pattern 212-1 and the multiple oxide layers 23. In the implementation process, the oxide layer pattern 212-1 and the oxide layer 23 can be removed by a wet etching process, which is not limited in the embodiment of the present invention. Fig.11 As shown, after etching is completed, the oxide layer 23 is replaced by the air gap 216. The final structure ensures that the width of the landing pad is reduced and the adjacent landing pads are separated, avoiding the problem of landing pad bridging and landing pad reduction during the process of making the air gap.

[0054] The air gap preparation method provided by the embodiment of the present invention is applied to a dynamic random access memory. The dynamic random access memory structure includes a semiconductor substrate with a bit line and a word line, a first bit line spacer layer arranged on the side walls of both sides of the bit line, an oxide layer arranged on the side walls of the first bit line spacer layer, and an insulating layer arranged on the top of the bit line. A node contact layer is arranged on the surface of the semiconductor substrate. The dynamic random access memory also includes a second bit line spacer layer. The oxide layer is located between the first bit line spacer layer and the second bit line spacer layer. When preparing the air gap, a first covering layer is deposited on the upper surface of the node contact layer, the top of the first bit line spacer layer, the top of the second bit line spacer layer, the top of the oxide layer, and the upper end surface of the insulating layer at the top of the bit line. A thin film layer is generated on the lower end surface of the first covering layer. After the first covering layer is ground to be flush with the upper end surface of the thin film layer at the top of the insulating layer, the portion above the horizontal line with the position of the top of the oxide layer as the horizontal line is removed downwardly to expose the top of the oxide layer. Then, a first oxide layer is formed on the plane exposed after etching. The first oxide layer is etched to remove one of the first and second bit line spaces. The first oxide layer portion on the top of the oxide layer on the side of each bit line is removed, the first oxide layer portion on the top of the oxide layer on the other side of each bit line is retained, and the retained first oxide layer portion on the top of the oxide layer on the other side of each bit line is determined as an oxide layer pattern, and then, a second covering layer is deposited at the position of the removed first oxide layer portion, so that the upper surface of the second covering layer is flush with the upper end surface of the oxide layer pattern, so as to fill the position where the first oxide layer portion is removed with the second covering layer, and the oxide layer pattern and the oxide layer are removed together to form an air gap at the oxide layer position to replace the oxide layer. In the embodiment of the present invention, an oxide layer pattern is formed on the top of the first bit line spacer layer, the top of the oxide layer, and the top of the second bit line spacer layer on one side of each bit line, and a second covering layer is deposited between the oxide layer patterns, so that the finally formed second covering layer and the first covering layer together constitute a landing pad, and the oxide layer pattern separates adjacent landing pads, thereby avoiding the problem of short circuit caused by bridging of landing pads generated when making air gaps, and avoiding the problem of reduction of landing pads because the width of the landing pads can be reduced at the same time.

[0055] Based on the same inventive concept, an embodiment of the present invention further provides a dynamic random access memory, which is a semiconductor structure prepared by the above-mentioned air gap preparation method provided by an embodiment of the present invention. Fig.11 .

[0056] Based on the same technical concept, an embodiment of the present invention further provides an electronic device, including the above-mentioned dynamic random access memory provided by an embodiment of the present invention.

[0057] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for preparing an air gap, It is characterized in that Applied to a dynamic random access memory, the dynamic random access memory comprises a semiconductor substrate with bit lines and word lines, a first bit line spacer layer arranged on the sidewalls of both sides of the bit line, an oxide layer arranged on the sidewalls of the first bit line spacer layer, and an insulating layer arranged on the top of the bit line, a node contact layer is arranged on the surface of the semiconductor substrate, the dynamic random access memory further comprises a second bit line spacer layer, the oxide layer is located between the first bit line spacer layer and the second bit line spacer layer, and the method comprises: Depositing a first covering layer on the upper end surface of the node contact layer, the top of the first bit line spacer layer, the top of the second bit line spacer layer, the top of the oxide layer and the upper end surface of the insulating layer, and forming a thin film layer on the lower end surface of the first covering layer; After the first covering layer is ground until it is flush with the upper end surface of the thin film layer on the top of the insulating layer, the portion above the horizontal line where the top of the oxide layer is located is removed downward by etching to expose the top of the oxide layer; forming a first oxide layer on the etched plane; Etching the first oxide layer to remove the first oxide layer portion at the top of the oxide layer on the first side of each bit line, the top of the first bit line spacer on the first side, and the top of the second bit line spacer on the first side, and retaining the first oxide layer portion at the top of the oxide layer on the second side of each bit line, the top of the first bit line spacer on the second side, and the top of the second bit line spacer on the second side, and determining the retained first oxide layer portion as an oxide layer pattern; Depositing a second covering layer at the position where the first oxide layer portion is removed, wherein the upper surface of the second covering layer is flush with the upper end surface of the oxide layer pattern; The oxide layer pattern and the oxide layer are removed to form an air space at the oxide layer position.

2. The method according to claim 1, It is characterized in that A bit line contact is arranged between the semiconductor substrate and the bit line, and an active region and an isolation structure between adjacent active regions are arranged on the semiconductor substrate.

3. The method according to claim 1, It is characterized in that The first covering layer and the second covering layer finally formed together constitute a floor pad.

4. The method according to claim 1, It is characterized in that The oxide layer pattern and the oxide layer are removed by a wet etching process.

5. The method according to claim 1, It is characterized in that Etching the first oxide layer specifically includes: A hard mask is formed on the upper surface of the first oxide layer, and after a third covering layer is deposited on the upper surface of the hard mask, the first oxide layer is etched.

6. The method according to claim 1, It is characterized in that The step of making the upper surface of the second covering layer flush with the upper end surface of the oxide layer pattern comprises: The upper surface of the second covering layer is polished to the same level as the upper end surface of the oxide layer pattern by a chemical mechanical polishing process.

7. The method according to claim 1, It is characterized in that The first oxide layer and the oxide layer are made of the same material.

8. The method according to claim 1, It is characterized in that The first oxide layer is made of silicon oxide.

9. The method according to claim 1, It is characterized in that The first covering layer and the second covering layer are both made of tungsten.

10. The method according to claim 5, It is characterized in that The third covering layer is made of silicon oxynitride.

11. The method according to claim 1, It is characterized in that Etching downward from the top of the first covering layer to remove the portion above the horizontal line where the top of the oxide layer is located specifically includes: A dry etching process is adopted to etch downward from the top of the first covering layer to remove the portion above the horizontal line where the top of the oxide layer is located.

12. A dynamic random access memory, It is characterized in that The dynamic random access memory is a semiconductor structure prepared by the air gap preparation method according to any one of claims 1 to 11.

13. An electronic device, It is characterized in that Comprising the dynamic random access memory as claimed in claim 12.

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