Low power consumption full differential multiple harmonic IQ zero intermediate frequency mixing circuit

Abstract

The application discloses a low-power consumption full-differential multiple harmonic IQ zero intermediate frequency mixing circuit, which comprises a quadrature all-pass filter QAF, a phase-shifting driver based on current vector synthesis, an mth harmonic frequency mixer I_MIXER based on a frequency multiplication structure and an mth harmonic frequency mixer Q_MIXER based on a frequency multiplication structure. The input local oscillator differential signal is changed into a quadrature IQ differential signal through the quadrature all-pass filter, then the driver module is used to realize the amplification signal and phase-shifting functions, generate and amplify the differential signal with the required phase, and then the differential signal is injected into the IQ mixer, and the mixer is used to realize the frequency multiplication function through the circuit structure based on the frequency multiplier and the state class B bias state of the adjusting transistor, so that the local oscillator signal is multiplied and mixed with the input RF signal. The application saves the power consumption of the frequency multiplier, effectively reduces the power consumption of the local oscillator signal link, and optimizes the linearity and noise of the mixer.

Description

Technical Field

[0001] This invention relates to the field of radar sensing radio frequency transceivers, specifically to a low-power fully differential multiple harmonic IQ zero intermediate frequency mixer circuit. Background Technology

[0002] Radar sensing RF transceivers are typically multi-transmitter / receiver (MDR) architectures, which poses a significant challenge to the local oscillator (LO) signal link. This is because the LO signal generated by the frequency synthesizer needs to be multiplied and then transmitted to the transmitting and receiving front-end circuits via drivers and transmission lines. The LO signal link chip area often accounts for a quarter of the total chip area. Due to the low gain of the frequency multiplier and the losses of long-distance transmission lines, the power consumption of the LO signal link is often very high, and this power consumption increases accordingly with the increase of the LO signal frequency. Furthermore, its output swing may limit the bandwidth of the entire chip. In applications where radar needs to operate continuously, low power consumption during RF transceiver operation is desirable. As the most power-consuming part of the entire chip, reducing the power consumption of the LO signal link is of paramount importance. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes a low-power fully differential multiple harmonic IQ zero-IF mixer circuit with harmonic order m (m≥2). This mixer circuit converts the input local oscillator differential signal into orthogonal IQ differential signals through an orthogonal all-pass filter. Then, a driver module amplifies the signal and performs phase shifting, generating and amplifying the differential signal of the desired phase, which is then injected into the IQ mixer. The mixer, through its frequency multiplier-based circuit structure and by adjusting the transistor in a Class B bias state (a characteristic of Class B transistors is that the positive and negative channels are usually off unless a signal is input; that is, when a positive signal arrives, only the positive channel works, while the negative channel is off, and the two channels do not work simultaneously; conversely, when a negative signal arrives, only the negative channel works, while the positive channel is off), multiplies the local oscillator signal and mixes it with the input RF signal, down-converting to obtain the desired zero-IF signal. This structure is equivalent to reducing the required local oscillator signal frequency to 1 / m of its original value, thereby reducing the requirements for local oscillator generation and transmission links, and lowering the overall chip power consumption. The m-th harmonic mixer in this circuit simultaneously performs the mixing function of controlling the transistor's on / off state through the local oscillator signal, and the m-th harmonic multiplication function by adjusting the transistor's bias state. Its RF gain is mainly achieved by current synthesis rather than by the transistor's small m-th transconductance conversion. Its gain change is small, and the lost RF gain can be compensated by the analog circuit transimpedance amplifier, achieving stable gain control and high linearity performance.

[0004] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0005] A low-power fully differential multiple harmonic IQ zero intermediate frequency mixer circuit includes an orthogonal all-pass filter QAF, a phase-shifting driver based on current vector synthesis, an m-th harmonic mixer I_MIXER based on a frequency multiplication structure, and an m-th harmonic mixer Q_MIXER based on a frequency multiplication structure.

[0006] The connection relationship of the aforementioned mixer circuit is as follows:

[0007] Input port IP is connected to the INP terminal of the quadrature full-pass filter QAF; input port IN is connected to the INN terminal of the quadrature full-pass filter QAF; the OIP terminal of the quadrature full-pass filter QAF is connected to the LOIP terminal of the phase shift driver; the OQN terminal of the quadrature full-pass filter QAF is connected to the LOQN terminal of the phase shift driver; the OQP terminal of the quadrature full-pass filter QAF is connected to the LOQP terminal of the phase shift driver; the OIN terminal of the quadrature full-pass filter QAF is connected to the LOIN terminal of the phase shift driver.

[0008] The LO_0 port of the phase shift driver is connected to the LO_IP1 port of the mixer I_MIXER; the LO_π / m port of the phase shift driver is connected to the LO_IP2 port of the mixer I_MIXER; the LO_2π / m port of the phase shift driver is connected to the LO_IP3 port of the mixer I_MIXER; the LO_3π / m port of the phase shift driver is connected to the LO_IP4 port of the mixer I_MIXER; and so on, the LO_(2m-2)π / m port of the phase shift driver is connected to the LO_IP2m-1 port of the mixer I_MIXER; the LO_(2m-1)π / m port of the phase shift driver is connected to the LO_IP2m port of the mixer I_MIXER.

[0009] The LO_π / 2m port of the phase shift driver is connected to the LO_IP1 port of the mixer Q_MIXER; the LO_3π / 2m port of the phase shift driver is connected to the LO_IP2 port of the mixer Q_MIXER; the LO_5π / 2m port of the phase shift driver is connected to the LO_IP3 port of the mixer Q_MIXER; the LO_7π / 2m port of the phase shift driver is connected to the LO_IP4 port of the mixer Q_MIXER; and so on, the LO_(4m-3)π / 2m port of the phase shift driver is connected to the LO_IP2m-1 port of the mixer Q_MIXER; the LO_(4m-1)π / 2m port of the phase shift driver is connected to the LO_IP2m port of the mixer Q_MIXER.

[0010] The input port RFIP is connected to the RF_IP port of mixer I_MIXER and the RF_IP port of mixer Q_MIXER; the input port RFIN is connected to the RF_IN port of mixer I_MIXER and the RF_IN port of mixer Q_MIXER; the IF_OP port of mixer I_MIXER is connected to the output port OIP; the IF_ON port of mixer I_MIXER is connected to the output port OIN; the IF_OP port of mixer Q_MIXER is connected to the output port OQP; and the IF_ON port of mixer Q_MIXER is connected to the output port OQN.

[0011] The aforementioned quadrature all-pass filter (QAF) includes adjustable resistor arrays R1, R2, R3, and R4, adjustable capacitor arrays C1 and C2, inductors L1 and L2, with the following connection relationships:

[0012] Input port INP is connected to one end of adjustable resistor array R1 and one end of adjustable capacitor array C1; input port INN is connected to one end of adjustable resistor array R2 and one end of adjustable capacitor array C2; the other end of adjustable resistor array R1 is connected to one end of inductor L1; the other end of adjustable resistor array R2 is connected to one end of inductor L2; output port OIP is connected to the other end of adjustable capacitor array C1 and one end of adjustable resistor array R3; output port OQN is connected to the other end of adjustable resistor array R3 and the other end of inductor L2; output port OIN is connected to one end of adjustable resistor array R4 and the other end of adjustable capacitor array C2; output port OQP is connected to the other end of adjustable resistor array R4 and the other end of inductor L1.

[0013] The current-synthesized phase-shift driver described above uses the input quadrature differential signals and the current vector synthesis of the amplifier circuit to obtain multiple pairs of differential signals with the same amplitude but different phases, which are then input into a mixer based on a frequency multiplier structure. The number of amplifier circuits and the size of the amplifier tubes required for phase-shift drivers in different harmonic mixing circuits vary. The phase-shift drivers used in second-harmonic mixing circuits and third-harmonic mixing circuits will be used as examples for illustration.

[0014] When m=2, the phase-shifting driver used in the second harmonic mixer circuit consists of transformers xfmr1, xfmr2, xfmr3, xfmr4, transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, current sources I1, I2, I3, and I4. Four of the transformers have essentially the same dimensions and performance. Transistors M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20 all have dimensions of W / L, with a gate width of W and a gate length of L. Transistors M1, M2, M3, M4, M5, M6, M7, and M8 have dimensions of [missing information]. The connection relationships are as follows:

[0015] The bias port VB is connected to the center tap of the secondary coil of transformer XFMR1, transformer XFMR2, transformer XFMR3, and transformer XFMR4; the bias port VC is connected to the gates of transistors M9, M10, M11, M12, M15, M16, M19, and M20; the input port LOIP is connected to the gates of transistors M1, M8, and M13; the input port LOIN is connected to the gates of transistors M3, M6, and M4. The gate of transistor M14 is connected to the gate of transistor M2, the gate of transistor M5, and the gate of transistor M17; the gate of transistor M4, the gate of transistor M7, and the gate of transistor M18 is connected to the gate of transistor M1; ground VSS is connected to the source of transistor M1, the source of transistor M2, the source of transistor M3, the source of transistor M4, the source of transistor M5, the source of transistor M6, the source of transistor M7, the source of transistor M8, the source of transistor M13, the source of transistor M14, the source of transistor M17, and the source of transistor M18; the drain of transistor M1 is connected to the drain of transistor M2 and the source of transistor M9; the drain of transistor M3... The drain of transistor M4 is connected to the drain of transistor M10, and the source of transistor M11 is connected to the drain of transistor M6, and the source of transistor M12; the drain of transistor M13 is connected to the source of transistor M15; the drain of transistor M14 is connected to the source of transistor M16; the drain of transistor M17 is connected to the source of transistor M19; the drain of transistor M18 is connected to the source of transistor M20; the drain of transistor M9 is connected to one end of the primary coil of transformer XFMR1; the drain of transistor M10 is connected to the other end of the primary coil of transformer XFMR1; the center tap of the primary coil of transformer XFMR1. One end of transistor M11 is connected to one end of current source I1; the other end of current source I1 is connected to power supply VDD; the drain of transistor M11 is connected to one end of the primary coil of transformer XFMR2; the drain of transistor M12 is connected to the other end of the primary coil of transformer XFMR2; the middle tap of the primary coil of transformer XFMR2 is connected to one end of current source I2; the other end of current source I2 is connected to the power supply voltage VDD; the drain of transistor M15 is connected to one end of the primary coil of transformer XFMR3; the drain of transistor M16 is connected to the other end of the primary coil of transformer XFMR3; the middle tap of the primary coil of transformer XFMR3 is connected to one end of current source I3; the other end of current source I3 is connected to the power supply voltage VDD.The drain of transistor M19 is connected to one end of the primary coil of transformer XFMR4; the drain of transistor M20 is connected to the other end of the primary coil of transformer XFMR4; the center tap of the primary coil of transformer XFMR4 is connected to one end of current source I4; the other end of current source I4 is connected to the supply voltage VDD; the two ends of the secondary coil of transformer XFMR1 are connected to the output ports LO_45° and LO_225° respectively; the two ends of the secondary coil of transformer XFMR2 are connected to the output ports LO_135° and LO_315° respectively; the two ends of the secondary coil of transformer XFMR3 are connected to the output ports LO_0° and LO_180° respectively; the two ends of the secondary coil of transformer XFMR4 are connected to the output ports LO_90° and LO_270° respectively.

[0016] When m=3, the phase-shifting driver used in the third harmonic mixer circuit consists of transformers xfmr1, xfmr2, xfmr3, xfmr4, xfmr5, xfmr6, transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, and current sources I1, I2, I3, I4, I5, and I6. The six transformers are basically identical in size and performance. Transistors M5, M6, M11, M12, M13, M14, M15, M16, M17, M18, M27, M28, M29, M30, M31, and M32 all have a size of W / L. Transistors M2, M4, M7, M9, M19, M21, M24, and M26 have a size of W / 2L. Transistors M1, M3, M8, M10, M20, M22, M23, and M25 have a size of [missing information - likely a size value]. The connection relationships are as follows:

[0017] The bias port VB is connected to the middle tap of the secondary coil of transformers XFMR1, XFMR2, XFMR3, XFMR4, XFMR5, and XFMR6; the bias port VC is connected to the gates of transistors M11, M12, M13, M14, M15, M16, M27, M28, M29, M30, and M31, and the crystal... The gate of the M32 transistor is connected; the two ends of the secondary coil of transformer XFMR1 are connected to the output ports LO_30° and LO_210° respectively; the two ends of the secondary coil of transformer XFMR2 are connected to the output ports LO_90° and LO_270° respectively; the two ends of the secondary coil of transformer XFMR3 are connected to the output ports LO_150° and LO_330° respectively; the two ends of the secondary coil of transformer XFMR4 are connected to the output ports LO_0° and LO_180° respectively; the two ends of the secondary coil of transformer XFMR5 are connected to the output ports LO_60° and LO_240° respectively; the two ends of the secondary coil of transformer XFMR6 are connected to the output ports LO_120° and LO_300° respectively; ground VSS is connected to the sources of transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M17, M18, M19, M20, M21, M22, M23, M24, M25, and M26, respectively; the input port LOIP is connected to the gates of transistors M1, M10, M17, and M19. The gate of transistor M26 is connected to the gate of transistor M3, transistor M8, transistor M18, transistor M21, and transistor M24; the input port LOQP is connected to the gate of transistor M2, transistor M5, transistor M7, transistor M20, and transistor M23; the input port LOQN is connected to the gate of transistor M4, transistor M6, transistor M9, transistor M22, and transistor M25; the source of transistor M11 is connected to the drain of transistor M1 and the drain of transistor M2; the source of transistor M12 is connected to the drain of transistor M3 and the drain of transistor M4.The two ends of the primary coil of transformer XFMR1 are connected to the drains of transistors M11 and M12, respectively; the middle tap of the primary coil of transformer XFMR1 is connected to one end of current source I1; the other end of current source I1 is connected to power supply VDD; the source of transistor M13 is connected to the drain of transistor M5; the source of transistor M14 is connected to the drain of transistor M6; the two ends of the primary coil of transformer XFMR2 are connected to the drains of transistors M13 and M14, respectively; the middle tap of the primary coil of transformer XFMR2 is connected to one end of current source I2. The other end of current source I2 is connected to power supply VDD; the source of transistor M15 is connected to the drain of transistor M7 and the drain of transistor M8; the source of transistor M16 is connected to the drain of transistor M9 and the drain of transistor M10; the two ends of the primary coil of transformer XFMR3 are connected to the drain of transistor M15 and the drain of transistor M16, respectively; the middle tap of the primary coil of transformer XFMR3 is connected to one end of current source I3; the other end of current source I3 is connected to power supply VDD; the source of transistor M27 is connected to the drain of transistor M17; the source of transistor M28 is connected to the crystal... The drain of transistor M18 is connected to the ground; the two ends of the primary coil of transformer XFMR4 are connected to the drains of transistors M27 and M28 respectively; the middle tap of the primary coil of transformer XFMR4 is connected to one end of current source I4; the other end of current source I4 is connected to power supply VDD; the source of transistor M29 is connected to the drain of transistor M19 and the drain of transistor M20; the source of transistor M30 is connected to the drain of transistors M21 and M22; the two ends of the primary coil of transformer XFMR5 are connected to the drains of transistors M29 and M30 respectively. The primary coil of transformer XFMR5 has its center tap connected to one end of current source I5; the other end of current source I5 is connected to power supply VDD; the source of transistor M31 is connected to the drain of transistors M23 and M24; the source of transistor M32 is connected to the drain of transistors M25 and M26; the two ends of the primary coil of transformer XFMR6 are connected to the drains of transistors M31 and M32 respectively; the center tap of the primary coil of transformer XFMR6 is connected to one end of current source I6; the other end of current source I6 is connected to power supply VDD.

[0018] Based on the structural features of phase-shifting drivers used in second-harmonic mixing circuits and third-harmonic mixing circuits, by analogy, a phase-shifting driver (m≥2) used in an m-th harmonic mixing circuit consists of 2m amplifier circuits. It utilizes two pairs of orthogonal differential input signals and, through the current vector synthesis principle of the amplifier circuits, changes the size of the amplifier tubes to obtain multiple pairs of differential signals with the same amplitude but different phases, which are then output to the cascaded mixer.

[0019] The m-th harmonic mixer (m≥2) based on the frequency multiplication structure can be divided into two types: active and passive.

[0020] An m-th order active harmonic mixer based on a frequency multiplication structure includes transistors M1, M2...Mm, Mm+1, Mm+2, Mm+3...M2m, M2m+1, M2m+2...M3m, M3m+1, M3m+2...M4m, adjustable resistor arrays R1, R2, R3, and R4, adjustable capacitor arrays C1 and C2, an operational amplifier (opamp), and a signal input module. The signal input module has four ports: input ports A and B, and output ports C and D. The adjustable resistor arrays R3 and R4, the adjustable capacitor arrays C1 and C2, and the operational amplifier (opamp) form a transgroup amplifier (TIA). The connection relationships of this mixer are as follows:

[0021] Input port RF_IP is connected to port A of the signal input module; input port RF_IN is connected to port B of the signal input module; the source of transistor M1, the source of transistor M2...the source of transistor M2m is connected to output port C of the signal input module; the source of transistor M2m+1, the source of transistor M2m+2...the source of transistor M4m is connected to output port D of the signal input module; input port LO_IP1 is connected to the gate of transistor M1 and the gate of transistor M3m+1; input port LO_IP3 is connected to the crystal... The gates of transistors M2 and M3m+2 are connected; and so on. The odd-numbered input port LO_IP2m-1 is connected to the gates of transistors Mm and M4m; the input port LO_IP2 is connected to the gates of transistors Mm+1 and M2m+1; the input port LO_IP4 is connected to the gates of transistors Mm+2 and M2m+2; and so on. The even-numbered input port LO_IP2m is connected to the gates of transistors M2m and M3m; adjustable resistor. One end of resistor R1 is connected to the drain of transistor M1, the drain of transistor M2, ..., the drain of transistor Mm, the drain of transistor M2m+1, the drain of transistor M2m+2, ..., the drain of transistor M3m, as well as one end of the adjustable resistor array R3, one end of the adjustable capacitor array C1, and the IP terminal of the operational amplifier opamp; one end of the adjustable resistor array R2 is connected to the drain of transistor Mm+1, the drain of transistor Mm+2, ..., the drain of transistor M2m, the drain of transistor M3m+1, the drain of transistor M3m+2, ..., the drain of transistor M4m The drain is connected to one end of the adjustable resistor array R4, one end of the adjustable capacitor array C2, and the IN terminal of the operational amplifier opamp; the power supply VDD is connected to the other end of the adjustable resistor array R1 and the other end of the adjustable resistor array R2; the output port IF_ON is connected to the ON terminal of the operational amplifier opamp, the other end of the adjustable resistor array R3, and the other end of the adjustable capacitor array C1; the output port IF_OP is connected to the OP terminal of the operational amplifier opamp, the other end of the adjustable resistor array R4, and the other end of the adjustable capacitor array C2.

[0022] The signal input module commonly takes several forms, including common source transistor voltage-to-current conversion structure, transformer coupling structure, and capacitor coupling structure according to the circuit structure. According to the DC bias, it can also be divided into two forms: with current source and without current source. The current source can be an adjustable resistor or a transistor current mirror, including but not limited to these structures.

[0023] Taking the three structures with current sources as examples, the common-source transistor voltage-to-current conversion structure includes transistor Ms1, transistor Ms2, and current source I1. Their connection relationship is as follows: the A port of the signal input module is connected to the gate of transistor Ms1; the B port of the signal input module is connected to the gate of transistor Ms2; the sources of transistors Ms1 and Ms2 are connected to one end of current source I1; the other end of current source I1 is connected to ground VSS; the drain of transistor Ms1 is connected to the C port of the signal input module; and the drain of transistor Ms2 is connected to the D port of the signal input module.

[0024] The transformer coupling structure includes a transformer xfmr, a current source I2, and a current source I3. The connection relationship is as follows: one end of current source I2 and one end of current source I3 are connected to ground VSS; the other end of current source I2 is connected to one end of the secondary coil of transformer xfmr and the C port of the input signal module; the other end of current source I3 is connected to the other end of the secondary coil of transformer xfmr and the D port of the input signal module; the A and B ports of the signal input module are respectively connected to the two ends of the primary coil of transformer xfmr.

[0025] The capacitive coupling structure includes capacitor C3, capacitor C4, current source I4, and current source I5; their connection relationship is as follows: one end of current source I4, one end of current source I5, and ground VSS are connected; port A of the signal input module is connected to one end of capacitor C3; port B of the signal input module is connected to one end of capacitor C4; port C of the signal input module is connected to the other end of current source I4 and the other end of capacitor C3; port D of the signal input module is connected to the other end of current source I5 and the other end of capacitor C4.

[0026] The m-th harmonic mixer (m≥2) based on a frequency multiplier structure can be divided into active and passive structures. The passive m-th harmonic mixer based on a frequency multiplier includes transistors M1, M2…Mm, Mm+1, Mm+2…M2m, M2m+1, M2m+2…M3m, M3m+1, M3m+2…M4m, adjustable resistor array R3, adjustable resistor array R4, adjustable capacitor array C1, adjustable capacitor array C2, operational amplifier (opamp), and a signal input module. The signal input module has four ports: input ports A and B, and output ports C and D. Their connections are as follows:

[0027] Input port RF_IP is connected to port A of the signal input module; input port RF_IN is connected to port B of the signal input module; the source of transistor M1, the source of transistor M2 up to the source of transistor M2m are connected to port C of the signal input module; the source of transistor M2m+1, the source of transistor M2m+2 up to the source of transistor M4m are connected to port D of the signal input module; input port LO_IP1 is connected to the gate of transistor M1 and the gate of transistor M3m+1; input port LO_IP3 is connected to... The gates of transistors M2 and M3m+2 are connected; and so on. The odd-numbered input port LO_IP2m-1 is connected to the gates of transistors Mm and M4m; the input port LO_IP2 is connected to the gates of transistors Mm+1 and M2m+1; the input port LO_IP4 is connected to the gates of transistors Mm+2 and M2m+2; and so on. The even-numbered input port LO_IP2m is connected to the gates of transistors M2m and M3m. Connect the following terminals: one end of resistor R1 to the drain of transistor M1, the drain of transistor M2 up to the drain of transistor Mm, the drain of transistor M2m+1, the drain of transistor M2m+2 up to the drain of transistor M3m, one end of adjustable resistor array R3, one end of adjustable capacitor array C1, and the IP terminal of operational amplifier opamp; one end of resistor R2 to the drain of transistor Mm+1, the drain of transistor Mm+2 up to the drain of transistor M2m, the drain of transistor M3m+1, the drain of transistor M3m+2 up to the crystal. The drain of transistor M4m, one end of adjustable resistor array R4, one end of adjustable capacitor array C2, and the IN terminal of operational amplifier opamp are connected; port VCM is connected to the other end of resistor R1 and the other end of resistor R2; output port IF_ON is connected to the ON terminal of operational amplifier opamp, the other end of adjustable resistor array R3, and the other end of adjustable capacitor array C1; output port IF_OP is connected to the OP terminal of operational amplifier opamp, the other end of adjustable resistor array R4, and the other end of adjustable capacitor array C2.

[0028] There are several common forms of signal input modules, which, based on circuit structure, include two types: transformer-coupled and capacitor-coupled, but are not limited to these two structures. A transformer-coupled signal input module contains only one transformer (xfmr). The connection is as follows: the two ends of the primary coil of the transformer (xfmr) are connected to terminals A and B of the signal input module, respectively; the two ends of the secondary coil of the transformer (xfmr) are connected to terminals C and D of the signal input module, respectively.

[0029] The signal input module with capacitive coupling structure includes capacitors C3 and C4. The connection relationship is as follows: one end of capacitor C3 is connected to terminal A of the signal input module; the other end of capacitor C3 is connected to terminal C of the signal input module; one end of capacitor C4 is connected to terminal B of the signal input module; and the other end of capacitor C4 is connected to terminal D of the signal input module.

[0030] The beneficial effects of this invention are:

[0031] The fully differential m-th harmonic IQ zero intermediate frequency mixer circuit of the present invention (m≥2) is equivalent to combining a frequency multiplier and a mixer, saving the power consumption of the frequency multiplier. At the same time, the required local oscillator signal frequency becomes 1 / m of the original, which can effectively reduce the power consumption of the local oscillator signal link. Furthermore, because the mixer it contains removes the transconductance stage in the Gilbert unit, it optimizes the linearity and noise of the mixer. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a fully differential subharmonic IQ mixer circuit.

[0033] Figure 2 This is a schematic diagram of the circuit structure of a quadrature all-pass filter (QAF).

[0034] Figure 3 This is a schematic diagram of the circuit structure of a phase-shifting driver used in a second harmonic mixer circuit.

[0035] Figure 4 This is a schematic diagram of the circuit structure of a phase-shifting driver used in a third harmonic mixer circuit.

[0036] Figure 5 This is a schematic diagram of the circuit structure of an active mixer based on an m-fold frequency multiplication structure;

[0037] Figure 6 This is a schematic diagram of the circuit structure of a passive mixer based on an m-fold frequency multiplication structure. Detailed Implementation

[0038] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. The objectives and effects of the present invention will become clearer as a result. The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0039] A high-linearity, low-power fully differential m-th harmonic IQ zero-IF mixer circuit (m≥2) is disclosed. The mixer circuit includes an orthogonal all-pass filter QAF, a phase-shift driver based on current vector synthesis, and m-th harmonic mixers I_MIXER and Q_MIXER based on a frequency multiplication structure. The connection relationship of the mixer circuit is as follows: Figure 1 As shown:

[0040] Input port IP is connected to the INP terminal of the quadrature full-pass filter QAF; input port IN is connected to the INN terminal of the quadrature full-pass filter QAF; the OIP terminal of the quadrature full-pass filter QAF is connected to the LOIP terminal of the phase shift driver; the OQN terminal of the quadrature full-pass filter QAF is connected to the LOQN terminal of the phase shift driver; the OQP terminal of the quadrature full-pass filter QAF is connected to the LOQP terminal of the phase shift driver; the OIN terminal of the quadrature full-pass filter QAF is connected to the LOIN terminal of the phase shift driver.

[0041] The LO_0 port of the phase shift driver is connected to the LO_IP1 port of the mixer I_MIXER; the LO_π / m port of the phase shift driver is connected to the LO_IP2 port of the mixer I_MIXER; the LO_2π / m port of the phase shift driver is connected to the LO_IP3 port of the mixer I_MIXER; the LO_3π / m port of the phase shift driver is connected to the LO_IP4 port of the mixer I_MIXER; and so on, the LO_(2m-2)π / m port of the phase shift driver is connected to the LO_IP2m-1 port of the mixer I_MIXER; the LO_(2m-1)π / m port of the phase shift driver is connected to the LO_IP2m port of the mixer I_MIXER.

[0042] The LO_π / 2m port of the phase shift driver is connected to the LO_IP1 port of the mixer Q_MIXER; the LO_3π / 2m port of the phase shift driver is connected to the LO_IP2 port of the mixer Q_MIXER; the LO_5π / 2m port of the phase shift driver is connected to the LO_IP3 port of the mixer Q_MIXER; the LO_7π / 2m port of the phase shift driver is connected to the LO_IP4 port of the mixer Q_MIXER; and so on, the LO_(4m-3)π / 2m port of the phase shift driver is connected to the LO_IP2m-1 port of the mixer Q_MIXER; the LO_(4m-1)π / 2m port of the phase shift driver is connected to the LO_IP2m port of the mixer Q_MIXER.

[0043] The input port RFIP is connected to the RF_IP port of mixer I_MIXER and the RF_IP port of mixer Q_MIXER; the input port RFIN is connected to the RF_IN port of mixer I_MIXER and the RF_IN port of mixer Q_MIXER; the IF_OP port of mixer I_MIXER is connected to the output port OIP; the IF_ON port of mixer I_MIXER is connected to the output port OIN; the IF_OP port of mixer Q_MIXER is connected to the output port OQP; and the IF_ON port of mixer Q_MIXER is connected to the output port OQN.

[0044] Figure 2 The aforementioned orthogonal all-pass filter (QAF) includes adjustable resistor arrays R1, R2, R3, and R4, adjustable capacitor arrays C1 and C2, inductors L1 and L2. R1 and R2 are used to compensate for R4 and R3, respectively, and define the real part of the impedance between the OIP and OIN output ports and between the OQP and OQN output ports as 100 ohms. Its connection relationship is as follows:

[0045] Input port INP is connected to terminal a of adjustable resistor array R1 and adjustable capacitor array C1; input port INN is connected to terminal a of adjustable resistor array R2 and adjustable capacitor array C2; terminal b of adjustable resistor array R1 is connected to terminal a of inductor L1; terminal b of adjustable resistor array R2 is connected to terminal a of inductor L2; output port OIP is connected to terminal b of adjustable capacitor array C1 and terminal a of adjustable resistor array R3; output port OQN is connected to terminal b of adjustable resistor array R3 and terminal b of inductor L2; output port OIN is connected to terminal a of adjustable resistor array R4 and terminal b of adjustable capacitor array C2; output port OQP is connected to terminal b of adjustable resistor array R4 and terminal b of inductor L1.

[0046] The current-synthesized phase-shift driver is characterized by using the current vector synthesis of an amplifier circuit to obtain multiple pairs of differential signals with the same amplitude but different phases from the input quadrature differential signals, which are then input into a mixer based on a frequency multiplier structure. The number of amplifier circuits and the size of the amplifier tubes required for phase-shift drivers in different harmonic mixing circuits vary. The phase-shift drivers used in second-harmonic mixing circuits and third-harmonic mixing circuits are used as examples for illustration.

[0047] Figure 3 This is a schematic diagram of a phase-shift driver circuit used in a second harmonic mixer circuit. It consists of transformers xfmr1, xfmr2, xfmr3, and xfmr4; transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20; and current sources I1, I2, I3, and I4. Transformers xfmr1, xfmr2, xfmr3, and xfmr4 have essentially the same dimensions and performance. Transistors M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20 all have a W / L ratio, with a gate width of W and a gate length of L. The dimensions of transistors M1, M2, M3, M4, M5, M6, M7, and M8 are as follows: After current synthesis, the phase-shifted gain is ensured to remain consistent with the gain of the direct drive, minimizing the amplitude difference of the output quadrature differential signal. The connection relationship is as follows:

[0048] The bias port VB is connected to the f terminals of transformers xfmr1, xfmr2, xfmr3, and xfmr4; the bias port VC is connected to the g terminals of transistors M9, M10, M11, M12, M15, M16, M19, and M20; the input port LOIP is connected to the g terminals of transistors M1, M8, and M13; the input port LOIN is connected to the g terminals of transistors M3, M6, and M14; the input port LOQP is connected to the g terminals of transistors M2 and M3. The gate (g) terminal of transistor M5 is connected to the gate (g) terminal of transistor M17; the input port LOQN is connected to the gate (g) terminals of transistors M4, M7, and M18; ground VSS is connected to the source (s) terminals of transistors M1, M2, M3, M4, M5, M6, M7, M8, M13, M14, M17, and M18; the drain (d) terminal of transistor M1 is connected to the drain (d) terminal of transistor M2 and the source (s) terminal of transistor M9; the drain (d) terminal of transistor M3 is connected to the drain (d) terminal of transistor M4 and the source (s) terminal of transistor M10; the drain (d) terminal of transistor M5 is connected to the crystal... The drain (d) terminal of transistor M6 is connected to the source (s) terminal of transistor M11; the drain (d) terminal of transistor M7 is connected to the drain (d) terminal of transistor M8 and the source (s) terminal of transistor M12; the drain (d) terminal of transistor M13 is connected to the source (s) terminal of transistor M15; the drain (d) terminal of transistor M14 is connected to the source (s) terminal of transistor M16; the drain (d) terminal of transistor M17 is connected to the source (s) terminal of transistor M19; the drain (d) terminal of transistor M18 is connected to the source (s) terminal of transistor M20; the drain (d) terminal of transistor M9 is connected to the a terminal of transformer xfmr1; the drain (d) terminal of transistor M10 is connected to the b terminal of transformer xfmr1; the emitter (e) terminal of transformer xfmr1 is connected to the a terminal of current source I1; the b terminal of current source I1 is connected to power supply VDD; the drain (d) terminal of transistor M11 is connected to the a terminal of transformer xfmr2; The d-terminal of transistor M12 is connected to the b-terminal of transformer XFMR2; the e-terminal of transformer XFMR2 is connected to the a-terminal of current source I2; the b-terminal of current source I2 is connected to the supply voltage VDD; the d-terminal of transistor M15 is connected to the a-terminal of transformer XFMR3; the d-terminal of transistor M16 is connected to the b-terminal of transformer XFMR3; the e-terminal of transformer XFMR3 is connected to the a-terminal of current source I3; the b-terminal of current source I3 is connected to the supply voltage VDD; the d-terminal of transistor M19 is connected to the a-terminal of transformer XFMR4; the d-terminal of transistor M20 is connected to the b-terminal of transformer XFMR4; the e-terminal of transformer XFMR4 is connected to the a-terminal of current source I4; the b-terminal of current source I4 is connected to the supply voltage VDD.The collector (C) terminal of transformer XFMR1 is connected to the output port LO_45°; the collector (D) terminal of transformer XFMR1 is connected to the output port LO_225°; the collector (C) terminal of transformer XFMR2 is connected to the output port LO_135°; the collector (D) terminal of transformer XFMR1 is connected to the output port LO_315°; the collector (C) terminal of transformer XFMR3 is connected to the output port LO_0°; the collector (D) terminal of transformer XFMR1 is connected to the output port LO_180°; the collector (C) terminal of transformer XFMR4 is connected to the output port LO_90°; and the collector (D) terminal of transformer XFMR1 is connected to the output port LO_270°.

[0049] Figure 4 This is a schematic diagram of the phase-shift driver circuit used in a third harmonic mixer circuit. It consists of transformers xfmr1, xfmr2, xfmr3, xfmr4, xfmr5, and xfmr6; transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, and M32; and current sources I1, I2, I3, I4, I5, and I6. Transformers XFMR1, XFMR2, XFMR3, XFMR4, XFMR5, and XFMR6 have basically the same size and performance. Transistors M5, M6, M11, M12, M13, M14, M15, M16, M17, M18, M27, M28, M29, M30, M31, and M32 all have a size of W / L. Transistors M2, M4, M7, M9, M19, M21, M24, and M26 have a size of W / 2L. Transistors M1, M3, M8, M10, M20, M22, M23, and M25 have a size of [missing information]. The connection relationships are as follows:

[0050] The bias port VB is connected to the f terminals of transformers xfmr1, xfmr2, xfmr3, xfmr4, xfmr5, and xfmr6; the bias port VC is connected to the g terminals of transistors M11, M12, M13, M14, M15, M16, M27, M28, M29, M30, M31, and M32; the c terminal of transformer xfmr1 is connected to the output port LO_30°; the d terminal of transformer xfmr1... The C terminal of transformer XFMR2 is connected to the output port LO_210°; the D terminal of transformer XFMR2 is connected to the output port LO_90°; the D terminal of transformer XFMR2 is connected to the output port LO_270°; the C terminal of transformer XFMR3 is connected to the output port LO_150°; the D terminal of transformer XFMR3 is connected to the output port LO_330°; the C terminal of transformer XFMR4 is connected to the output port LO_0°; the D terminal of transformer XFMR4 is connected to the output port LO_180°; the C terminal of transformer XFMR5 is connected to the output port LO_60°; the D terminal of transformer XFMR5 is connected to the output port LO_240°; the C terminal of transformer XFMR6 is connected to the output port LO_120°. The drain (d) terminal of transformer XFMR6 is connected to the output port LO_300°; ground VSS is connected to the source (s) terminals of transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M17, M18, M19, M20, M21, M22, M23, M24, M25, and M26 respectively; the input port LOIP is connected to the gate (g) terminal of transistor M1, and the crystal... The gate (g) terminals of transistors M10, M17, M19, and M26 are connected; the input port LOIN is connected to the gate (g) terminals of transistors M3, M8, M18, M21, and M24; the input port LOQP is connected to the gate (g) terminals of transistors M2, M5, M7, M20, and M23; the input port LOQN is connected to the gate (g) terminals of transistors M4, M6, M9, M22, and M25; and the source (s) terminal of transistor M11 is connected to the d (d) terminals of transistors M1 and M2.The source (s) terminal of transistor M12 is connected to the d terminals of transistors M3 and M4; the a terminal of transformer xfmr1 is connected to the d terminal of transistor M11; the b terminal of transformer xfmr1 is connected to the d terminal of transistor M12; the emitter (e) terminal of transformer xfmr1 is connected to the a terminal of current source I1; the b terminal of current source I1 is connected to power supply VDD; the source (s) terminal of transistor M13 is connected to the d terminal of transistor M5; the source (s) terminal of transistor M14 is connected to the d terminal of transistor M6; the a terminal of transformer xfmr2 is connected to the d terminal of transistor M13; the b terminal of transformer xfmr2 is connected to the d terminal of transistor M14. The emitter (e) terminal of transformer XFMR2 is connected to the a terminal of current source I2; the b terminal of current source I2 is connected to the power supply VDD; the source (s) terminal of transistor M15 is connected to the d terminals of transistors M7 and M8; the source (s) terminal of transistor M16 is connected to the d terminals of transistors M9 and M10; the a terminal of transformer XFMR3 is connected to the d terminal of transistor M15; the b terminal of transformer XFMR3 is connected to the d terminal of transistor M16; the emitter (e) terminal of transformer XFMR3 is connected to the a terminal of current source I3; the b terminal of current source I3 is connected to the power supply VDD; the source (s) terminal of transistor M27 is connected to the d terminal of transistor M17. Connected; the source (s) terminal of transistor M28 is connected to the drain (d) terminal of transistor M18; the a terminal of transformer XFMR4 is connected to the drain (d) terminal of transistor M27; the b terminal of transformer XFMR4 is connected to the drain (d) terminal of transistor M28; the emitter (e) terminal of transformer XFMR4 is connected to the a terminal of current source I4; the b terminal of current source I4 is connected to power supply VDD; the source (s) terminal of transistor M29 is connected to the drain (d) terminals of transistors M19 and M20; the source (s) terminal of transistor M30 is connected to the drain (d) terminals of transistors M21 and M22; the a terminal of transformer XFMR5 is connected to the drain (d) terminal of transistor M29; transformer XFMR... Terminal b of transformer XFMR5 is connected to terminal d of transistor M30; terminal e of transformer XFMR5 is connected to terminal a of current source I5; terminal b of current source I5 is connected to power supply VDD; terminal s of transistor M31 is connected to terminals d of transistors M23 and M24; terminal s of transistor M32 is connected to terminals d of transistors M25 and M26; terminal a of transformer XFMR6 is connected to terminal d of transistor M31; terminal b of transformer XFMR6 is connected to terminal d of transistor M32; terminal e of transformer XFMR6 is connected to terminal a of current source I6; terminal b of current source I6 is connected to power supply VDD.

[0051] Based on the structural features of phase-shifting drivers used in second-harmonic mixing circuits and third-harmonic mixing circuits, by analogy, a phase-shifting driver (m≥2) used in an m-th harmonic mixing circuit consists of 2m amplifier circuits. It utilizes two pairs of orthogonal differential input signals and, through the current vector synthesis principle of the amplifier circuits, changes the size of the amplifier tubes to obtain multiple pairs of differential signals with the same amplitude but different phases, which are then output to the cascaded mixer.

[0052] The m-th harmonic mixer (m≥2) based on the frequency multiplier structure can be divided into two types: active and passive.

[0053] Figure 5 This is a schematic diagram of the circuit structure of an active mixer based on an m-fold frequency multiplication structure. It includes transistors M1, M2…Mm, Mm+1, Mm+2, Mm+3…M2m, M2m+1, M2m+2…M3m, M3m+1, M3m+2…M4m, adjustable resistor arrays R1, R2, R3, R4, adjustable capacitor arrays C1, C2, an operational amplifier (opamp), and a signal input module. The adjustable resistor arrays R3 and R4, the adjustable capacitors C1 and C2, and the operational amplifier (opamp) form a transimpedance amplifier (TIA). The bandwidth of the intermediate frequency output signal of the mixer is adjusted by regulating the adjustable capacitor arrays C1 and C2, and the gain of the mixer is precisely adjusted by regulating the adjustable resistor arrays R3 and R4. The connections are as follows: Figure 5 As shown:

[0054] Input port RF_IP is connected to terminal A of the signal input module; input port RF_IN is connected to terminal B of the signal input module; the s-terminals of transistors M1, M2, etc., up to the s-terminal of transistor M2m, are connected to terminal C of the signal input module; the s-terminals of transistors M2m+1, M2m+2, etc., up to the s-terminal of transistor M4m, are connected to terminal D of the signal input module; input port LO_IP1 is connected to the g-terminals of transistors M1 and M3m+1; input port LO_IP3 is connected to transistor M2... The input port LO_IP2m-1 with odd suffixes is connected to the g terminal of transistor Mm and the g terminal of transistor M4m; the input port LO_IP2 is connected to the g terminal of transistor Mm+1 and the g terminal of transistor M2m+1; the input port LO_IP4 is connected to the g terminal of transistor Mm+2 and the g terminal of transistor M2m+2; and so on. The input port LO_IP2m with even suffixes is connected to the g terminal of transistor M2m and the g terminal of transistor M3m; the adjustable resistor array R1 The a-terminal of the variable resistor array R3 is connected to the d-terminal of the variable resistor array C1, and so on, up to the d-terminal of the operational amplifier opamp; the a-terminal of the variable resistor array R2 is connected to the d-terminal of the variable resistor array R2, up ... The d terminal of transistor M4m is also connected to the a terminal of adjustable resistor array R4, the a terminal of adjustable capacitor array C2, and the IN terminal of operational amplifier opamp; the power supply VDD is connected to the b terminals of adjustable resistor array R1 and adjustable resistor array R2; the output port IF_ON is connected to the ON terminal of operational amplifier opamp, the b terminal of adjustable resistor array R3, and the b terminal of adjustable capacitor array C1; the output port IF_OP is connected to the OP terminal of operational amplifier opamp, the b terminal of adjustable resistor array R4, and the b terminal of adjustable capacitor array C2.

[0055] The signal input module commonly takes several forms, including common source transistor voltage-to-current conversion structure, transformer coupling structure, and capacitor coupling structure according to the circuit structure. According to the DC bias, it can also be divided into two forms: with current source and without current source. The current source can be an adjustable resistor or a transistor current mirror, including but not limited to these structures.

[0056] by Figure 5Taking the structure within the three boxes below as an example, the common-source transistor voltage-to-current conversion structure includes transistor Ms1, transistor Ms2, and current source I1. Their connections are as follows: port A of the signal input module is connected to the g terminal of transistor Ms1; port B of the signal input module is connected to the g terminal of transistor Ms2; the s terminals of transistors Ms1 and Ms2 are connected to the a terminal of current source I1; the b terminal of current source I1 is connected to ground VSS; the d terminal of transistor Ms1 is connected to port C of the signal input module; and the d terminal of transistor Ms2 is connected to port C of the signal input module.

[0057] The transformer coupling structure includes a transformer xfmr and current sources I2 and I3. The connection relationship is as follows: the b terminal of current source I2 is connected to ground VSS; the a terminal of current source I2 is connected to the c terminal of transformer xfmr and the C port of the input signal module; the a terminal of current source I2 is connected to the d terminal of transformer xfmr and the D port of the input signal module; the A terminal of the signal input module is connected to the a terminal of transformer xfmr; and the B terminal of the signal input module is connected to the b terminal of transformer xfmr.

[0058] The capacitive coupling structure includes capacitors C3 and C4, as well as current sources I4 and I5. The connections are as follows: terminal b of current source I4 and terminal b of current source I5 are connected to ground VSS. Port A of the signal input module is connected to terminal b of capacitor C3; port B of the signal input module is connected to terminal b of capacitor C4; port C of the signal input module is connected to terminal a of current source I4 and terminal a of capacitor C3; and port D of the signal input module is connected to terminal a of current source I5 and terminal a of capacitor C4.

[0059] In this mixer, transistors M1, M2, and up to Mm are connected at their s and d terminals, respectively. The g terminal receives local oscillator signals of different phases. This circuit structure is based on a frequency multiplier. By adjusting the bias of the transistors at the intersection of different local oscillator signals, the portion below the intersection is cut off, thereby achieving the function of frequency multiplication by the mth order. This can be equivalent to a single transistor. A local oscillator signal of the mth order is passed to the g terminal to control the transistor's on / off state to achieve mixing. Similarly, transistors Mm+1, Mm+2, up to M2m are equivalent to a frequency multiplier structure, transistors M2m+1, M2m+2, up to M3m are equivalent to a frequency multiplier structure, and transistors M3m+1, M3m+2, up to M4m are also equivalent to a frequency multiplier structure.

[0060] The m-th harmonic mixer (m≥2) based on a frequency multiplier structure can be divided into active and passive structures. Figure 6This is a schematic diagram of the circuit structure of an m-th order passive harmonic mixer based on an m-th order frequency multiplication structure. It includes transistors M1, M2…Mm, Mm+1, Mm+2, Mm+3…M2m, M2m+1, M2m+2…M3m, M3m+1, M3m+2…M4m, adjustable resistor arrays R3 and R4, adjustable capacitor arrays C1 and C2, an operational amplifier (opamp), and a signal input module. The connections are as follows: Figure 6 As shown:

[0061] Input port RF_IP is connected to port A of the signal input module; input port RF_IN is connected to port B of the signal input module; the s-terminals of transistors M1, M2, etc., up to the s-terminal of transistor M2m, are connected to the C-terminal of the signal input module; the s-terminals of transistors M2m+1, M2m+2, etc., up to the s-terminal of transistor M4m, are connected to the D-terminal of the signal input module; input port LO_IP1 is connected to the g-terminal of transistor M1 and the g-terminal of transistor M3m+1; input port LO_IP3 is connected to... The g-terminals of transistors M2 and M3m+2 are connected; and so on. The odd-numbered input port LO_IP2m-1 is connected to the g-terminals of transistors Mm and M4m; input port LO_IP2 is connected to the g-terminals of transistors Mm+1 and M2m+1; input port LO_IP4 is connected to the g-terminals of transistors Mm+2 and M2m+2; and so on. The even-numbered input port LO_IP2m is connected to the g-terminals of transistors M2m and M3m. The b-terminal of resistor R1 is connected to the d-terminals of transistors M1, M2, Mm, M2m+1, M2m+2, M3m, and so on, up to the d-terminal of transistor M3m. It is also connected to the a-terminal of the adjustable resistor array R3, the a-terminal of the adjustable capacitor array C1, and the IP terminal of the operational amplifier (opamp). The b-terminal of resistor R2 is connected to the d-terminals of transistors Mm+1, Mm+2, M2m, M3m+1, M3m+2, and so on, up to the d-terminal of transistor M2m. The terminals are connected to the d terminal of transistor M4m, the a terminal of adjustable resistor array R4, the a terminal of adjustable capacitor array C2, and the IN terminal of operational amplifier opamp; the port VCM is connected to the a terminal of resistor R1 and the a terminal of resistor R2; the output port IF_ON is connected to the ON terminal of operational amplifier opamp, the b terminal of adjustable resistor array R3, and the b terminal of adjustable capacitor array C1; the output port IF_OP is connected to the OP terminal of operational amplifier opamp, the b terminal of adjustable resistor array R4, and the b terminal of adjustable capacitor array C2.

[0062] The signal input module commonly takes several forms, including transformer coupling and capacitor coupling, depending on the circuit structure. These two structures are included, but not limited to, those two.Figure 6 The two boxes below contain the signal input modules for the example transformer-coupled structure and capacitor-coupled structure, respectively.

[0063] The signal input module of the transformer coupling structure contains only one transformer xfmr. The connection relationship is as follows: the a end of the transformer xfmr is connected to the A end of the signal input module; the b end of the transformer xfmr is connected to the B end of the signal input module; the c end of the transformer xfmr is connected to the C end of the signal input module; and the d end of the transformer xfmr is connected to the D end of the signal input module.

[0064] The signal input module with capacitive coupling structure includes capacitors C3 and C4. Their connection relationship is as follows: terminal b of capacitor C3 is connected to terminal A of the signal input module; terminal a of capacitor C3 is connected to terminal C of the signal input module; terminal b of capacitor C4 is connected to terminal B of the signal input module; and terminal a of capacitor C4 is connected to terminal D of the signal input module.

Claims

1. A low-power fully differential multiple harmonic IQ zero-IF mixer circuit, characterized in that: Including the orthogonal all-pass filter QAF, the phase-shifting driver based on current vector synthesis, the m-th harmonic mixer I_MIXER based on the frequency multiplication structure, and the m-th harmonic mixer Q_MIXER based on the frequency multiplication structure, where m≥2; Input port IP is connected to the INP terminal of the quadrature full-pass filter QAF; input port IN is connected to the INN terminal of the quadrature full-pass filter QAF; the OIP terminal of the quadrature full-pass filter QAF is connected to the LOIP terminal of the phase shift driver; the OQN terminal of the quadrature full-pass filter QAF is connected to the LOQN terminal of the phase shift driver; the OQP terminal of the quadrature full-pass filter QAF is connected to the LOQP terminal of the phase shift driver; the OIN terminal of the quadrature full-pass filter QAF is connected to the LOIN terminal of the phase shift driver. The LO_0 port of the phase shift driver is connected to the LO_IP1 port of the mixer I_MIXER; the LO_... The m port is connected to the LO_IP2 port of the mixer I_MIXER; the LO_2 port of the phase shifter is connected to... The m port is connected to the LO_IP3 port of the mixer I_MIXER; the LO_3 port of the phase shifter is connected to the LO_IP3 port. The m port is connected to the LO_IP4 port of the mixer I_MIXER; and so on, the LO_(2m-2) port of the phase shift driver. The m port is connected to the LO_IP(2m-1) port of the mixer I_MIXER; the LO_(2m-1) port of the phase shift driver... The m port is connected to the LO_IP2m port of the mixer I_MIXER; LO_ of the phase shift driver The 2m port is connected to the LO_IP1 port of the mixer Q_MIXER; the LO_3 port of the phase shifter is connected to... The 2m port is connected to the LO_IP2 port of the mixer Q_MIXER; the LO_5 port of the phase shifter is connected to... The 2m port is connected to the LO_IP3 port of the mixer Q_MIXER; the LO_7 port of the phase shifter is connected to... The 2m port is connected to the LO_IP4 port of the mixer Q_MIXER; similarly, the LO_(4m-3) port of the phase shift driver is connected to the LO_IP4 port of the phase shift driver. The 2m port is connected to the LO_IP(2m-1) port of the mixer Q_MIXER; the LO_(4m-1) port of the phase shift driver... The 2m port is connected to the LO_IP2m port of the mixer Q_MIXER; The input port RFIP is connected to the RF_IP port of mixer I_MIXER and the RF_IP port of mixer Q_MIXER; the input port RFIN is connected to the RF_IN port of mixer I_MIXER and the RF_IN port of mixer Q_MIXER; the IF_OP port of mixer I_MIXER is connected to the output port OIP; the IF_ON port of mixer I_MIXER is connected to the output port OIN; the IF_OP port of mixer Q_MIXER is connected to the output port OQP; and the IF_ON port of mixer Q_MIXER is connected to the output port OQN.

2. The low-power fully differential multiple harmonic IQ zero-IF mixer circuit according to claim 1, characterized in that: The aforementioned quadrature all-pass filter (QAF) includes adjustable resistor arrays R1, R2, R3, and R4, adjustable capacitor arrays C1 and C2, inductors L1 and L2, with the following connection relationships: Input port INP is connected to one end of adjustable resistor array R1 and one end of adjustable capacitor array C1; input port INN is connected to one end of adjustable resistor array R2 and one end of adjustable capacitor array C2; the other end of adjustable resistor array R1 is connected to one end of inductor L1; the other end of adjustable resistor array R2 is connected to one end of inductor L2; output port OIP is connected to the other end of adjustable capacitor array C1 and one end of adjustable resistor array R3; output port OQN is connected to the other end of adjustable resistor array R3 and the other end of inductor L2; output port OIN is connected to one end of adjustable resistor array R4 and the other end of adjustable capacitor array C2; output port OQP is connected to the other end of adjustable resistor array R4 and the other end of inductor L1.

3. The low-power fully differential multiple harmonic IQ zero-IF mixer circuit according to claim 1, characterized in that: The phase-shift driver based on current vector synthesis, through the input quadrature differential signals, uses current vector synthesis in an amplifier circuit to obtain multiple pairs of differential signals with the same amplitude but different phases, which are then input to a mixer based on a frequency multiplier structure. The number of amplifier circuits and the size of the amplifier transistors differ for phase-shift drivers used in different harmonic mixing circuits. The following is a description of the phase-shift drivers used in second-harmonic mixing circuits and third-harmonic mixing circuits: When m=2, the phase-shift driver used in the second harmonic mixer circuit consists of transformers xfmr1, xfmr2, xfmr3, xfmr4, transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, and current... It consists of power source I1, current source I2, current source I3, and current source I4; the four transformers have the same size and performance; transistors M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20 all have a size of W / L, with a gate width of W and a gate length of L; transistors M1, M2, M3, M4, M5, M6, M7, and M8 have a size of W / L. L; its connection relationship is as follows: The bias port VB is connected to the center tap of the secondary coil of transformer XFMR1, transformer XFMR2, transformer XFMR3, and transformer XFMR4; the bias port VC is connected to the gates of transistors M9, M10, M11, M12, M15, M16, M19, and M20; the input port LOIP is connected to the gates of transistors M1, M8, and M13; the input port LOIN is connected to the crystal... The gates of transistors M3, M6, and M14 are connected; the input port LOQP is connected to the gates of transistors M2, M5, and M17; the input port LOQN is connected to the gates of transistors M4, M7, and M18; and ground VSS is connected to the sources of transistors M1, M2, M3, M4, M5, M6, M7, M8, M13, M14, M17, and M18. The drain of transistor M1 is connected to the drain of transistor M2 and the source of transistor M9. The drain of transistor M3 is connected to the drain of transistor M4 and the source of transistor M10; the drain of transistor M5 is connected to the drain of transistor M6 and the source of transistor M11; the drain of transistor M7 is connected to the drain of transistor M8 and the source of transistor M12; and the drain of transistor M13 is connected to the source of transistor M15. The drain of transistor M14 is connected to the source of transistor M16; The drain of transistor M17 is connected to the source of transistor M19; the drain of transistor M18 is connected to the source of transistor M20; the drain of transistor M9 is connected to one end of the primary coil of transformer XFMR1; the drain of transistor M10 is connected to the other end of the primary coil of transformer XFMR1; the middle tap of the primary coil of transformer XFMR1 is connected to one end of current source I1; the other end of current source I1 is connected to power supply VDD; the drain of transistor M11 is connected to one end of the primary coil of transformer XFMR2; the drain of transistor M12 is connected to the other end of the primary coil of transformer XFMR2; the middle tap of the primary coil of transformer XFMR2 is connected to one end of current source I2; the other end of current source I2 is connected to the supply voltage VDD; the drain of transistor M15 is connected to one end of the primary coil of transformer XFMR3; the drain of transistor M16 is connected to the other end of the primary coil of transformer XFMR3. The middle tap of the primary coil of transformer XFMR3 is connected to one end of current source I3; the other end of current source I3 is connected to the supply voltage VDD; the drain of transistor M19 is connected to one end of the primary coil of transformer XFMR4; the drain of transistor M20 is connected to the other end of the primary coil of transformer XFMR4; the middle tap of the primary coil of transformer XFMR4 is connected to one end of current source I4; the other end of current source I4 is connected to the supply voltage VDD; the two ends of the secondary coil of transformer XFMR1 are connected to the output ports LO_45° and LO_225° respectively; the two ends of the secondary coil of transformer XFMR2 are connected to the output ports LO_135° and LO_315° respectively; the two ends of the secondary coil of transformer XFMR3 are connected to the output ports LO_0° and LO_180° respectively; the two ends of the secondary coil of transformer XFMR4 are connected to the output ports LO_90° and LO_270° respectively. When m=3, the phase-shifting driver used in the third harmonic mixer circuit consists of transformers xfmr1, xfmr2, xfmr3, xfmr4, xfmr5, xfmr6, transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, and current sources I1, I2, I3, I4, I5, and I6. Six of the transformers have identical dimensions and performance. Transistors M5, M6, M11, M12, M13, M14, M15, M16, M17, M18, M27, M28, M29, M30, M31, and M32 all have a size of W / L, with a gate width of W and a gate length of L. Transistors M2, M4, M7, M9, M19, M21, M24, and M26 have a size of W / 2L. Transistors M1, M3, M8, M10, M20, M22, M23, and M25 have a size of 3W / L. L; its connection relationship is as follows: The bias port VB is connected to the middle tap of the secondary coil of transformers XFMR1, XFMR2, XFMR3, XFMR4, XFMR5, and XFMR6; the bias port VC is connected to the gates of transistors M11, M12, M13, M14, M15, M16, M27, M28, M29, M30, and M31, and the crystal... The gate of the M32 transistor is connected; the two ends of the secondary coil of transformer XFMR1 are connected to the output ports LO_30° and LO_210° respectively; the two ends of the secondary coil of transformer XFMR2 are connected to the output ports LO_90° and LO_270° respectively; the two ends of the secondary coil of transformer XFMR3 are connected to the output ports LO_150° and LO_330° respectively; the two ends of the secondary coil of transformer XFMR4 are connected to the output ports LO_0° and LO_180° respectively; the two ends of the secondary coil of transformer XFMR5 are connected to the output ports LO_60° and LO_240° respectively; the two ends of the secondary coil of transformer XFMR6 are connected to the output ports LO_120° and LO_300° respectively; ground VSS is connected to the sources of transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M17, M18, M19, M20, M21, M22, M23, M24, M25, and M26, respectively; the input port LOIP is connected to the gates of transistors M1, M10, M17, and M19. The gate of transistor M26 is connected to the gate of transistor M3, transistor M8, transistor M18, transistor M21, and transistor M24; the input port LOQP is connected to the gate of transistor M2, transistor M5, transistor M7, transistor M20, and transistor M23; the input port LOQN is connected to the gate of transistor M4, transistor M6, transistor M9, transistor M22, and transistor M25; the source of transistor M11 is connected to the drain of transistor M1 and the drain of transistor M2; the source of transistor M12 is connected to the drain of transistor M3 and the drain of transistor M4.The two ends of the primary coil of transformer XFMR1 are connected to the drains of transistors M11 and M12, respectively; the middle tap of the primary coil of transformer XFMR1 is connected to one end of current source I1; the other end of current source I1 is connected to power supply VDD; the source of transistor M13 is connected to the drain of transistor M5; the source of transistor M14 is connected to the drain of transistor M6; the two ends of the primary coil of transformer XFMR2 are connected to the drains of transistors M13 and M14, respectively; the middle tap of the primary coil of transformer XFMR2 is connected to one end of current source I2. The other end of current source I2 is connected to power supply VDD; the source of transistor M15 is connected to the drain of transistor M7 and the drain of transistor M8; the source of transistor M16 is connected to the drain of transistor M9 and the drain of transistor M10; the two ends of the primary coil of transformer XFMR3 are connected to the drain of transistor M15 and the drain of transistor M16, respectively; the middle tap of the primary coil of transformer XFMR3 is connected to one end of current source I3; the other end of current source I3 is connected to power supply VDD; the source of transistor M27 is connected to the drain of transistor M17; the source of transistor M28 is connected to the crystal... The drain of transistor M18 is connected to the ground; the two ends of the primary coil of transformer XFMR4 are connected to the drains of transistors M27 and M28 respectively; the middle tap of the primary coil of transformer XFMR4 is connected to one end of current source I4; the other end of current source I4 is connected to power supply VDD; the source of transistor M29 is connected to the drain of transistor M19 and the drain of transistor M20; the source of transistor M30 is connected to the drain of transistors M21 and M22; the two ends of the primary coil of transformer XFMR5 are connected to the drains of transistors M29 and M30 respectively. The primary coil of transformer XFMR5 has its center tap connected to one end of current source I5; the other end of current source I5 is connected to power supply VDD; the source of transistor M31 is connected to the drain of transistor M23 and the drain of transistor M24; the source of transistor M32 is connected to the drain of transistor M25 and the drain of transistor M26; the two ends of the primary coil of transformer XFMR6 are connected to the drains of transistor M31 and M32 respectively; the primary coil of transformer XFMR6 has its center tap connected to one end of current source I6; the other end of current source I6 is connected to power supply VDD. Based on the structural features of phase-shifting drivers used in second-harmonic mixing circuits and third-harmonic mixing circuits, and by analogy, a phase-shifting driver used in an m-th harmonic mixing circuit consists of 2m amplifier circuits. It utilizes two pairs of input quadrature differential signals and, through the current vector synthesis principle of the amplifier circuits, by changing the size of the amplifier tubes, outputs multiple pairs of differential signals with the same amplitude but different phases to the cascaded mixer.

4. The low-power fully differential multiple harmonic IQ zero-IF mixer circuit according to claim 1, characterized in that: The m-th harmonic mixer based on the frequency multiplication structure is divided into two types: active and passive.

5. A low-power fully differential multiple harmonic IQ zero-IF mixer circuit according to claim 4, characterized in that: The m-th order active harmonic mixer based on a frequency multiplication structure includes transistors M1, M2...Mm, Mm+1, Mm+2, Mm+3...M2m, M2m+1, M2m+2...M3m, M3m+1, M3m+2...M4m, adjustable resistor arrays R1, R2, R3, R4, adjustable capacitor arrays C1 and C2.

2. Operational amplifier (opamp) and signal input module; the signal input module has four ports: input ports A and B, and output ports C and D; adjustable resistor array R3, adjustable resistor array R4, adjustable capacitor array C1, adjustable capacitor array C2, and the operational amplifier (opamp) form a transgroup amplifier (TIA). The bandwidth of the mixer's intermediate frequency output signal is adjusted by regulating adjustable capacitor arrays C1 and C2, and the gain of the mixer is precisely adjusted by regulating adjustable resistor arrays R3 and R4. The connection relationship of this mixer is as follows: Input port RF_IP is connected to port A of the signal input module; input port RF_IN is connected to port B of the signal input module; the source of transistor M1, the source of transistor M2, ..., the source of transistor M2m are connected to output port C of the signal input module; the source of transistor M2m+1, the source of transistor M2m+2, ..., the source of transistor M4m are connected to output port D of the signal input module; input port LO_IP1 is connected to the gate of transistor M1 and the gate of transistor M3m+1; input port LO_IP3 is connected to the crystal... The gates of transistors M2 and M3m+2 are connected; and so on. The odd-numbered input port LO_IP(2m-1) is connected to the gates of transistors Mm and M4m; input port LO_IP2 is connected to the gates of transistors Mm+1 and M2m+1; input port LO_IP4 is connected to the gates of transistors Mm+2 and M2m+2; and so on. The even-numbered input port LO_IP2m is connected to the gates of transistors M2m and M3m; adjustable voltage... One end of the resistor array R1 is connected to the drain of transistor M1, the drain of transistor M2, ..., the drain of transistor Mm, the drain of transistor M2m+1, the drain of transistor M2m+2, ..., the drain of transistor M3m, one end of the adjustable resistor array R3, one end of the adjustable capacitor array C1, and the IP terminal of the operational amplifier opamp; one end of the adjustable resistor array R2 is connected to the drain of transistor Mm+1, the drain of transistor Mm+2, ..., the drain of transistor M2m, the drain of transistor M3m+1, the drain of transistor M3m+2, ..., the drain of transistor M... The drain of the 4mA amplifier is connected to one end of the adjustable resistor array R4, one end of the adjustable capacitor array C2, and the IN terminal of the operational amplifier opamp; the power supply VDD is connected to the other end of the adjustable resistor array R1 and the other end of the adjustable resistor array R2; the output port IF_ON is connected to the ON terminal of the operational amplifier opamp, the other end of the adjustable resistor array R3, and the other end of the adjustable capacitor array C1; the output port IF_OP is connected to the OP terminal of the operational amplifier opamp, the other end of the adjustable resistor array R4, and the other end of the adjustable capacitor array C2. The signal input module has a common source transistor voltage-to-current conversion structure, a transformer coupling structure, and a capacitor coupling structure according to its circuit structure; it is divided into two forms according to DC bias: with current source and without current source. The current source is an adjustable resistor or a transistor current mirror. The common-source transistor voltage-to-current conversion structure includes transistor Ms1, transistor Ms2, and current source I1. Their connection relationship is as follows: the A port of the signal input module is connected to the gate of transistor Ms1; the B port of the signal input module is connected to the gate of transistor Ms2; the sources of transistors Ms1 and Ms2 are connected to one end of current source I1; and the other end of current source I1 is connected to ground VSS. The drain of transistor Ms1 is connected to port C of the signal input module; the drain of transistor Ms2 is connected to port D of the signal input module. The transformer coupling structure includes a transformer xfmr, current source I2, and current source I3. Their connection relationship is as follows: one end of current source I2 and one end of current source I3 are connected to ground VSS; the other end of current source I2 is connected to one end of the secondary coil of transformer xfmr and also to the C port of the input signal module; the other end of current source I3 is connected to the other end of the secondary coil of transformer xfmr and also to the D port of the input signal module; the A and B ports of the signal input module are respectively connected to the two ends of the primary coil of transformer xfmr. The capacitive coupling structure includes capacitor C3, capacitor C4, current source I4, and current source I5; their connection relationship is as follows: one end of current source I4, one end of current source I5, and ground VSS are connected; port A of the signal input module is connected to one end of capacitor C3; port B of the signal input module is connected to one end of capacitor C4; port C of the signal input module is connected to the other end of current source I4 and the other end of capacitor C3; port D of the signal input module is connected to the other end of current source I5 and the other end of capacitor C4.

6. A low-power fully differential multiple harmonic IQ zero-IF mixer circuit according to claim 4, characterized in that: The aforementioned m-th order passive harmonic mixer based on a frequency multiplication structure includes transistors M1, M2...Mm, Mm+1, Mm+2...M2m, M2m+1, M2m+2...M3m, M3m+1, M3m+2...M4m, adjustable resistor array R3, adjustable resistor array R4, adjustable capacitor array C1, adjustable capacitor array C2, operational amplifier, and signal input module. The signal input module has four ports: input ports A and B, and output ports C and D. Their connections are as follows: Input port RF_IP is connected to port A of the signal input module; input port RF_IN is connected to port B of the signal input module; the source of transistor M1, the source of transistor M2 up to the source of transistor M2m are connected to port C of the signal input module; the source of transistor M2m+1, the source of transistor M2m+2 up to the source of transistor M4m are connected to port D of the signal input module; input port LO_IP1 is connected to the gate of transistor M1 and the gate of transistor M3m+1; input port LO_IP3 is connected to transistor M2... The gates of transistors M1 and M2 are connected; and so on. The odd-numbered input port LO_IP(2m-1) is connected to the gates of transistors M1 and M4m; the input port LO_IP2 is connected to the gates of transistors M1+1 and M2m+1; the input port LO_IP4 is connected to the gates of transistors M1+2 and M2m+2; and so on. The even-numbered input port LO_IP2m is connected to the gates of transistors M2m and M3m; Adjustable resistor array One end of the adjustable resistor array R1 is connected to the drain of transistor M1, the drain of transistor M2 up to the drain of transistor Mm, the drain of transistor M2m+1, the drain of transistor M2m+2 up to the drain of transistor M3m, one end of the adjustable resistor array R3, one end of the adjustable capacitor array C1, and the IP terminal of the operational amplifier opamp; one end of the adjustable resistor array R2 is connected to the drain of transistor Mm+1, the drain of transistor Mm+2 up to the drain of transistor M2m, the drain of transistor M3m+1, the drain of transistor M3m+2 up to the drain of transistor M4. The drain of the amplifier is connected to one end of the adjustable resistor array R4, one end of the adjustable capacitor array C2, and the IN terminal of the operational amplifier opamp; the port VCM is connected to the other end of the adjustable resistor array R1 and the other end of the adjustable resistor array R2; the output port IF_ON is connected to the ON terminal of the operational amplifier opamp, the other end of the adjustable resistor array R3, and the other end of the adjustable capacitor array C1; the output port IF_OP is connected to the OP terminal of the operational amplifier opamp, the other end of the adjustable resistor array R4, and the other end of the adjustable capacitor array C2. The signal input module has two structures based on its circuit structure: transformer coupling and capacitor coupling. The signal input module with transformer coupling structure contains only one transformer xfmr, and its connection relationship is as follows: the two ends of the primary coil of the transformer xfmr are connected to the A and B ends of the signal input module, respectively; the two ends of the secondary coil of the transformer xfmr are connected to the C and D ends of the signal input module, respectively. The signal input module with capacitive coupling structure includes capacitors C3 and C4. The connection relationship is as follows: one end of capacitor C3 is connected to terminal A of the signal input module; the other end of capacitor C3 is connected to terminal C of the signal input module; one end of capacitor C4 is connected to terminal B of the signal input module; and the other end of capacitor C4 is connected to terminal D of the signal input module.

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