Display panel, driving method, driving circuit and display device

Abstract

The display panel, the driving method, the driving circuit and the display device are provided. In the display panel, the control terminals of two switch elements connected with the same display data output end are connected with one multiplexing control line respectively, and the control terminal of the switch element connected with the outermost isolated data line is connected with one multiplexing control line. The on-off states of the switch elements corresponding to each adjacent two data lines are the same, and the on-off states of the switch elements corresponding to the adjacent data lines are different. When the adjacent display data output end provides different polarity data voltage in the same frame period, more than half of the sub-pixels around the same sub-pixel have opposite polarity with the same sub-pixel.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel, driving method, driving circuit, and display device. Background Technology

[0002] This section is intended to provide background or context for the embodiments set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] With the development of display technology, the resolution of displays is getting higher and higher. However, high-resolution displays have the problem of processing large amounts of data and difficulties in transmission. The pixel structure of BV3 (Bright View III, or virtual display for short) can solve the problems of large data volume and difficult transmission. It is known that the pixel flipping method of the BV3 pixel structure display panel is column flipping. Summary of the Invention

[0004] This disclosure provides a display panel, a driving method, a driving circuit, and a display device.

[0005] This disclosure adopts the following technical solution: a display panel, comprising:

[0006] Multiple rows of subpixels, each row of subpixels is arranged along the row direction, the starting positions of adjacent rows of subpixels are staggered by half a subpixel, each subpixel has a different color from its neighboring subpixels, the arrangement of subpixels in odd-numbered rows is the same, and the arrangement of subpixels in even-numbered rows is the same.

[0007] Multiple data lines, wherein every two adjacent columns of sub-pixels of the same color are connected to the same data line, and isolated single columns of sub-pixels of the same color at the ends of the row are connected to the same data line.

[0008] Multiple switching elements are used, with two data lines separated by one data line connected to a data lead via a switching element, and the outermost isolated data line connected to the outermost data lead via a switching element. Each of the data leads is used to connect to a display data output terminal of the driving circuit.

[0009] Multiple multiplexed control lines are used. The control terminals of two switching elements connected to the same display data output terminal are each connected to a multiplexed control line. The control terminal of the switching element connected to the outermost isolated data line is connected to a multiplexed control line. The on / off states of the switching elements corresponding to each pair of adjacent data lines are the same. The on / off states of the switching elements corresponding to an isolated data line in the row direction are different from those of the switching elements corresponding to adjacent data lines. This ensures that when adjacent display data output terminals provide data voltages of different polarities within the same frame period, the polarity of more than half of the sub-pixels surrounding the same sub-pixel is opposite to the polarity of the same sub-pixel.

[0010] In some embodiments, the multiple multiplexing control lines are an even number of multiplexing control lines, wherein half of the multiplexing control lines are grouped together and have the same timing, and the other half of the multiplexing control lines are grouped together and have the same timing, and the timing of the two groups of multiplexing control lines is reversed.

[0011] In some embodiments, the number of multiplexed control lines is N, and each group of N consecutive data lines is a set. The layout of 2N switching elements connected to a set of data lines is a repeating unit of the switching element layout, where N is an even number greater than or equal to 2.

[0012] In some embodiments, a set of 2N switching elements connected to a set of data lines are arranged in two rows extending along the extension direction of the multiplexing control line, with each row containing N switching elements.

[0013] In some embodiments, the display panel is a liquid crystal display panel.

[0014] This disclosure adopts the following technical solution: a driving method for the aforementioned display panel, comprising:

[0015] A square wave signal is provided to the multiple multiplexed control lines, wherein the timing of some multiplexed control lines is opposite to that of the other multiplexed control lines;

[0016] When the voltage on any multiplexed control line is an effective voltage, the required data voltage is provided to the multiple data leads connected to the multiple multiplexed control line on the data line corresponding to the switching element connected to the multiple multiplexed control line.

[0017] This disclosure adopts the following technical solution: a driving circuit for the aforementioned display panel, comprising: a timing control circuit and a display data output circuit, wherein the timing control circuit is used to provide square wave signals to the plurality of multiplexed control lines, wherein the timing of some multiplexed control lines is opposite to the timing of the remaining multiplexed control lines; the display data output circuit is used to provide the required data voltage to the data lines corresponding to the switching elements connected to the multiple multiplexed control lines when the voltage on any multiplexed control line is an effective voltage.

[0018] The present disclosure adopts the following technical solution: a display device, including the aforementioned display panel and the aforementioned driving circuit. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure, showing a portion of the structure of the display panel and the driving circuit.

[0020] Figure 2 yes Figure 1 The diagram shows the connection relationship of some of the wiring on the display panel in the display device.

[0021] Figure 3a yes Figure 2 The timing diagram for driving the multiplexed control lines is shown.

[0022] Figure 3b This is a flowchart of a display panel driving method according to an embodiment of the present disclosure.

[0023] Figures 4 to 10 This is a layout of a portion of the structure of the display panel in an embodiment of this disclosure.

[0024] Figure 11 This is a block diagram of the driving circuit of the display panel according to an embodiment of the present disclosure. Detailed Implementation

[0025] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure, showing a portion of the structure of the display panel and the driving circuit. Figure 2 yes Figure 1 The diagram shows the connection relationship of some traces on the display panel in the display device. In this embodiment, the pixel structure of the display panel is a BV3 pixel structure.

[0027] Embodiments of this disclosure provide a display panel, including:

[0028] Multiple rows of subpixels, each row of subpixels is arranged along the row direction, the starting positions of adjacent rows of subpixels are staggered by half a subpixel, each subpixel has a different color from its neighboring subpixels, the arrangement of subpixels in odd-numbered rows is the same, and the arrangement of subpixels in even-numbered rows is the same.

[0029] Multiple data lines, wherein every two adjacent columns of sub-pixels of the same color are connected to the same data line, and isolated single columns of sub-pixels of the same color at the ends of the row are connected to the same data line.

[0030] Multiple switching elements are used, with two data lines separated by one data line connected to a data lead via a switching element, and the outermost isolated data line connected to the outermost data lead via a switching element. Each of the data leads is used to connect to a display data output terminal of the driving circuit.

[0031] Multiple multiplexed control lines are used. The control terminals of two switching elements connected to the same display data output terminal are each connected to a multiplexed control line. The control terminal of the switching element connected to the outermost isolated data line is connected to a multiplexed control line. The on / off states of the switching elements corresponding to each pair of adjacent data lines are the same. The on / off states of the switching elements corresponding to an isolated data line in the row direction are different from those of the switching elements corresponding to adjacent data lines. This ensures that when adjacent display data output terminals provide data voltages of different polarities within the same frame period, the polarity of more than half of the sub-pixels surrounding the same sub-pixel is opposite to the polarity of the same sub-pixel.

[0032] Figure 1 In the display device shown, the display data output terminals S1 to S3240 of the driving circuit C (e.g., a display driver chip) are used to output display data for two different colors of sub-pixels. For example, display data output terminal S3240 is used to output display data for the red sub-pixel and display data for the blue sub-pixel in a time-division multiplexing manner. The display data output terminal SR of the driver chip C is used to output display data for the blue sub-pixel.

[0033] Each switching element S has its control terminal connected to one of the multiplexed control lines MUX1-1, MUX1-2, MUX2-1, and MUX2-2. The first terminal of each switching element S is connected via a data lead to one of the display data output terminals S1-S3240 and SR. The second terminal of each switching element S is connected to a data line. The labels of the multiplexed control lines connected to each switching element S are marked in the exemplary box of the switching element S.

[0034] For example, the display data output terminal S3240 is connected to the second terminal of the switching element S, the control terminal of the switching element S is connected to the multiplexing control line MUX1-2, and the first terminal of the switching element S is connected to the data line R1.

[0035] Specifically, in Figure 2 In this circuit, the switching element S is an N-type transistor, numbered T1 to T12 in sequence.

[0036] Most data lines connect two columns of sub-pixels of the same color. For example, data line R1 connects the nearest neighboring column of red sub-pixels in odd-numbered rows and the nearest neighboring column of red sub-pixels in even-numbered rows. Data line G1 connects the nearest neighboring column of green sub-pixels in odd-numbered rows and the nearest neighboring column of green sub-pixels in even-numbered rows. Data line B1 connects the nearest neighboring column of blue sub-pixels in odd-numbered rows and the nearest neighboring column of blue sub-pixels in even-numbered rows. For example, data line R2 connects the nearest neighboring column of red sub-pixels in odd-numbered rows and the nearest neighboring column of red sub-pixels in even-numbered rows. Data line G2 connects the nearest neighboring column of green sub-pixels in odd-numbered rows and the nearest neighboring column of green sub-pixels in even-numbered rows. Data line B2 connects the nearest neighboring column of blue sub-pixels in odd-numbered rows and the nearest neighboring column of blue sub-pixels in even-numbered rows.

[0037] Figure 1 The red sub-pixel containing the positive polarity data voltage is marked as R+, the green sub-pixel containing the positive polarity data voltage is marked as G+, the blue sub-pixel containing the positive polarity data voltage is marked as B+, the red sub-pixel containing the negative polarity data voltage is marked as R-, the green sub-pixel containing the negative polarity data voltage is marked as G-, and the blue sub-pixel containing the negative polarity data voltage is marked as B-.

[0038] During the current frame cycle, display data output terminal S3240 outputs negative display data for the red sub-pixel connected to data line R1 and negative display data for the blue sub-pixel connected to data line B1. Display data output terminal S3239 outputs positive display data for the green sub-pixel connected to data line G1 and positive display data for the red sub-pixel connected to data line R2.

[0039] Because the subpixels in the BV3 pixel structure are not aligned, the outermost column of blue subpixels requires a separate display data output terminal SR to drive it. The on / off state of the display data output terminal SR and the corresponding data line is controlled by the multiplexing control line MUX2-1.

[0040] Most of the display data output terminals of the driving circuit C (except for the display data output terminal SR) drive two data lines, and the polarity of the data voltage output by adjacent display data output terminals is opposite in the same frame period. This makes the polarity of each sub-pixel in the display panel opposite to that of most of the sub-pixels in the surrounding sub-pixels.

[0041] For example, refer to Figure 1 The outermost red sub-pixel has a negative data voltage, while the data voltages of the two surrounding blue sub-pixels and one surrounding green sub-pixel are positive. The middle green sub-pixel has a positive data voltage, and of its six surrounding sub-pixels, four have negative data voltages and two have positive data voltages.

[0042] The pixel flipping mode of this display panel is very close to the dot flipping mode, which effectively suppresses the polarization of the liquid crystal and improves the display quality.

[0043] In some embodiments, combined with Figure 2 and Figure 3a , Figure 3a yes Figure 2 The diagram shows the driving timing of the multiplexed control lines. The multiplexed control lines consist of four multiplexed control lines: MUX1-1, MUX1-2, MUX2-1, and MUX2-2. Two multiplexed control lines, MUX1-1 and MUX2-2, form a group with identical timing, while the other two multiplexed control lines, MUX1-2 and MUX2-1, form another group with identical timing. The timing of the two groups of multiplexed control lines is reversed.

[0044] The timing sequence of multiple multiplexed control lines is the same. This is to reduce the load on each multiplexed control line and ensure that each multiplexed control line has sufficient driving capability. Of course, the display panel can also be equipped with only 2 multiplexed control lines, or an even number of multiplexed control lines such as 6 multiplexed control lines.

[0045] Specifically, the display panel is a liquid crystal display panel.

[0046] Figures 4 to 10 This is a layout diagram of a portion of the structure of a display panel according to an embodiment of this disclosure. It shows 12 consecutive switching elements (top-gate transistors T1 to T12). From the perspective of pixel structure, 12 data lines form a repeating unit. However, from the perspective of transistor layout, 8 transistors form a repeating unit. This makes the layout design of the display panel simpler.

[0047] In the embodiments of this disclosure, the number of multiplexed control lines is N, and each group of N consecutive data lines is a set. The layout of 2N switching elements connected to a set of data lines is a repeating unit of the switching element layout, where N is an even number greater than or equal to 2.

[0048] refer to Figures 4 to 10 The number of multiplexed control lines is 4. Each group of 4 consecutive data lines is a set. The layout of the 8 switching elements connected to a set of data lines is a repeating unit of the switching element layout.

[0049] This is because, from a layout design perspective, it does not distinguish what color of sub-pixel display data is being transmitted by the data cable.

[0050] In some embodiments, a set of 2N switching elements connected to a set of data lines are arranged in two rows extending along the extension direction of the multiplexed control line, and the number of chip switching elements in each row is N.

[0051] refer to Figures 4 to 10The eight switching elements connected by a set of data lines are arranged in two rows, with four switching elements in each row.

[0052] This design provides sufficient layout space for switching elements even with high display density (PPI).

[0053] If these eight switching elements are arranged in a row, the layout space for the switching elements will be too small, the size of the switching elements will be too small, and the conduction capability of the switching elements will be insufficient.

[0054] Figure 3b This is a flowchart of a display panel driving method according to an embodiment of the present disclosure.

[0055] This disclosure also provides a driving method for the aforementioned display panel, comprising:

[0056] Step 101: Provide square wave signals to the multiple multiplexed control lines, wherein the timing of some multiplexed control lines is opposite to that of the other multiplexed control lines;

[0057] Step 102: When the voltage on any multiplexed control line is an effective voltage, provide the required data voltage to the multiple data leads connected to the multiple multiplexed control line, corresponding to the data line of the switching element connected to the multiple multiplexed control line.

[0058] The two sets of multiplexed control lines alternately output effective voltages, and adjacent data lines receive data voltages of different polarities, which makes the polarity of each sub-pixel opposite to that of most of the surrounding sub-pixels.

[0059] Figure 11 This is a block diagram of a driving circuit for a display panel according to an embodiment of this disclosure. This disclosure also provides a driving circuit for the aforementioned display panel, comprising: a timing control circuit 1 and a display data output circuit 2. The timing control circuit 1 is used to provide square wave signals to the plurality of multiplexed control lines, wherein the timing of some multiplexed control lines is opposite to the timing of the remaining multiplexed control lines. The display data output circuit 2 is used to provide the required data voltage to the data lines corresponding to the switching elements connected to any multiplexed control line when the voltage on any multiplexed control line is an effective voltage. This driving circuit can be integrated into a display driver chip.

[0060] Based on the same inventive concept, this disclosure also provides a display device, including the aforementioned display panel and the aforementioned driving circuit. A display device refers to any product or component with a display function. Examples of display devices include display modules, mobile phones, tablet computers, monitors, televisions, vehicle displays, navigation systems, ground displays, electronic billboards, etc.

[0061] The various embodiments in this disclosure are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0062] The scope of protection of this disclosure is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its scope and spirit. If such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, then the intent of this disclosure also includes such modifications and variations.

Claims

1. A display panel, characterized in that, include: Multiple rows of subpixels, each row of subpixels is arranged along the row direction, the starting positions of adjacent rows of subpixels are staggered by half a subpixel, each subpixel has a different color from its neighboring subpixels, the arrangement of subpixels in odd-numbered rows is the same, and the arrangement of subpixels in even-numbered rows is the same. Multiple data lines, wherein every two adjacent columns of sub-pixels of the same color are connected to the same data line, and isolated single columns of sub-pixels of the same color at the ends of the row are connected to the same data line. Multiple switching elements are used, with two data lines separated by one data line connected to a data lead via a switching element, and the outermost isolated data line connected to the outermost data lead via a switching element. Each of the data leads is used to connect to a display data output terminal of the driving circuit. Multiple multiplexed control lines are used. The control terminals of two switching elements connected to the same display data output terminal are each connected to a multiplexed control line. The control terminal of the switching element connected to the outermost isolated data line is connected to a multiplexed control line. The on / off states of the switching elements corresponding to each pair of adjacent data lines are the same. The on / off states of the switching elements corresponding to an isolated data line located at the end in the row direction are different from the on / off states of the switching elements corresponding to the adjacent data lines. This is so that when adjacent display data output terminals provide data voltages of different polarities within the same frame period, the polarity of more than half of the sub-pixels surrounding the same sub-pixel is opposite to the polarity of the same sub-pixel.

2. The display panel according to claim 1, characterized in that, The multiple multiplexing control lines are an even number of multiplexing control lines, of which half of the multiplexing control lines are in one group with the same timing, and the other half of the multiplexing control lines are in one group with the same timing, and the timing of the two groups of multiplexing control lines is opposite.

3. The display panel according to claim 2, characterized in that, The number of multiplexed control lines is N. Each group of N consecutive data lines is a set. The layout of 2N switching elements connected to a set of data lines is a repeating unit of the switching element layout. N is an even number greater than or equal to 2.

4. The display panel according to claim 3, characterized in that, A set of data lines connects 2N switching elements, which are arranged in two rows extending along the extension direction of the multiplexing control line, with each row containing N switching elements.

5. The display panel according to claim 1, characterized in that, The display panel is a liquid crystal display panel.

6. A driving method for a display panel according to any one of claims 1 to 5, characterized in that, include: A square wave signal is provided to the multiple multiplexed control lines, wherein the timing of some multiplexed control lines is opposite to that of the other multiplexed control lines; When the voltage on any multiplexed control line is an effective voltage, the required data voltage is provided to the multiple data leads connected to the multiple multiplexed control line on the data line corresponding to the switching element connected to the multiple multiplexed control line.

7. A driving circuit for a display panel according to any one of claims 1 to 5, characterized in that, include: The system includes a timing control circuit and a display data output circuit. The timing control circuit provides square wave signals to the multiple multiplexed control lines, wherein the timing of some multiplexed control lines is opposite to that of the remaining multiplexed control lines. The display data output circuit provides the required data voltage to the data lines corresponding to the switching elements connected to any multiplexed control line when the voltage on any multiplexed control line is an effective voltage.

8. A display device, characterized in that, It includes the display panel according to any one of claims 1 to 5 and the driving circuit according to claim 7.

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