A memory and display device

Abstract

Embodiments of the present application provide a memory and a display device, the memory comprising a plurality of storage circuits, a plurality of delay circuits and a controller; one delay circuit in the plurality of delay circuits is coupled between one storage circuit in the plurality of storage circuits and the controller, and the plurality of delay circuits are used for performing delay processing on output enable signals of the plurality of storage circuits, so that the plurality of storage circuits synchronously output storage data signals. By setting the plurality of delay circuits to perform delay processing on the output enable signals of the plurality of storage circuits, the storage data signal delay synchronization caused by the signal wire length difference can be realized, and the storage data signal delay synchronization caused by the parasitic capacitance influence can also be realized, so that the plurality of storage circuits synchronously output the storage data signals, thereby improving the reliability of the memory.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a memory and display device. Background Technology

[0002] With the development of semiconductor process technology, the process size is gradually shrinking. For example, the organic light-emitting diode (OLED) driver chip has evolved from 40nm to 28nm, and the 28nm process is becoming increasingly mature. Chips under this process have the advantages of small size and low power consumption, but the shrinking chip size makes the internal circuit of the chip more complex.

[0003] In display devices, the transmission of data signals by the driver chip typically needs to ensure simultaneity, meaning that the multiple signals transmitted by the memory must remain synchronized. The memory transmits data signals through multiple memory arrays. Because each memory array is located in a different memory bank area, and due to chip trace space limitations, the signal trace lengths of each memory array are different, causing the transmission of each signal to be out of sync. Summary of the Invention

[0004] This application provides a memory and a display device for synchronously transmitting multiple storage data signals of the memory, thereby improving the reliability of the memory.

[0005] In a first aspect, embodiments of this application provide a memory, including: a plurality of storage circuits, a plurality of delay circuits, and a controller;

[0006] One of the multiple delay circuits is coupled between one of the multiple storage circuits and the controller. The multiple delay circuits are used to delay the output enable signals of the multiple storage circuits so that the multiple storage circuits can synchronously output stored data signals.

[0007] In one optional implementation, the storage circuit includes: a trigger and a storage component; the input of the trigger is coupled to the output of the storage component, and the output of the trigger is coupled to the input of the controller;

[0008] The delay circuit includes a first delay sub-circuit and / or a second delay sub-circuit;

[0009] The first delay sub-circuit is coupled between the first signal output terminal of the controller and the control terminal of the storage component, and is used to delay the output preparation signal of the storage component.

[0010] The second delay sub-circuit is coupled between the second signal output terminal of the controller and the control terminal of the trigger, and is used to delay the output read signal of the trigger.

[0011] In one optional implementation, a parasitic capacitance exists between the second signal output terminal of the controller and the control terminal of the trigger;

[0012] The parasitic capacitance is formed by the overlapping of the wiring between the second signal output terminal of the controller and the control terminal of the trigger;

[0013] In this case, there are different parasitic capacitances between the control terminal of each trigger and the second signal output terminal of the controller.

[0014] In one alternative implementation, the storage component includes: a storage array and an operational amplifier;

[0015] The first end of the storage array is coupled to the first input end of the operational amplifier, and the second end of the storage array is coupled to the second input end of the operational amplifier;

[0016] The control terminal of the operational amplifier is coupled to the output terminal of the first delay sub-circuit, and the output terminal of the operational amplifier is coupled to the input terminal of the trigger.

[0017] In one optional implementation, both the first delay sub-circuit and the second delay sub-circuit include a first delay unit and a second delay unit;

[0018] The first terminal of the first delay is coupled to the power supply terminal, and the second terminal of the first delay is grounded;

[0019] The first terminal of the second delay is coupled to the power supply terminal, and the second terminal of the second delay is grounded;

[0020] The output terminal of the first delay unit is coupled to the input terminal of the second delay unit;

[0021] In the first delay sub-circuit, the input terminal of the first delay unit is coupled to the first signal output terminal of the controller, and the output terminal of the second delay unit is coupled to the control terminal of the operational amplifier;

[0022] In the second delay sub-circuit, the input terminal of the first delay unit is coupled to the second signal output terminal of the controller, and the output terminal of the second delay unit is coupled to the control terminal of the trigger.

[0023] In one alternative implementation, both the first delay and the second delay include multiple switches connected in series, and the delay time of the delay is related to the number of switches included in the delay.

[0024] In one alternative implementation, in the first delay sub-circuit, the first delay unit and the second delay unit include the same number of switching transistors;

[0025] In the second delay sub-circuit, the first delay unit and the second delay unit include the same number of switching transistors.

[0026] In one optional implementation, both the first delay and the second delay include a first switch, a second switch, a third switch, and a fourth switch.

[0027] The control terminal of the first switch is coupled to the control terminals of the second switch, the third switch, and the fourth switch, respectively, and serves as the input terminal of the first delay unit and the second delay unit.

[0028] The first end of the first switch is coupled to the power supply terminal, the second end of the first switch is coupled to the first end of the second switch, the second end of the second switch is coupled to the first end of the third switch, the second end of the third switch is coupled to the first end of the fourth switch, and the second end of the fourth switch is grounded.

[0029] The second terminal of the second switch serves as the output terminal of both the first delay and the second delay.

[0030] In one optional embodiment, the first and second switching transistors are both P-type switching transistors, and the third and fourth switching transistors are both N-type switching transistors; or, the first and second switching transistors are both N-type switching transistors, and the third and fourth switching transistors are both P-type switching transistors.

[0031] In one optional implementation, the memory array includes: a fifth switch, a sixth switch, a first NOT gate, and a second NOT gate;

[0032] The control terminal of the fifth switch is coupled to the control terminal of the sixth switch. The first terminal of the fifth switch serves as the first terminal of the storage array. The second terminal of the fifth switch is coupled to the input terminal of the first NOT gate and the output terminal of the second NOT gate.

[0033] The first end of the sixth switch is coupled to the output of the first NOT gate and the input of the second NOT gate, and the second end of the sixth switch serves as the second end of the memory array.

[0034] Secondly, embodiments of this application also provide a display device, including a memory as described in any of the first aspects.

[0035] This application provides a memory and a display device. The memory includes multiple storage circuits, multiple delay circuits, and a controller. One of the delay circuits is coupled between one of the storage circuits and the controller. The multiple delay circuits are used to delay the output enable signals of the multiple storage circuits, so that the multiple storage circuits output stored data signals synchronously. By setting multiple delay circuits to delay the output enable signals of the multiple storage circuits, the stored data signals delayed and synchronized due to differences in signal trace lengths, as well as due to the influence of parasitic capacitance, can be delayed and synchronized, thereby improving the reliability of the memory. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram showing the arrangement of various memory arrays in the memory.

[0038] Figure 2 A schematic diagram of the circuit structure of a memory provided in an embodiment of this application;

[0039] Figure 3 A schematic diagram of the circuit structure of another memory provided in an embodiment of this application;

[0040] Figure 4 A schematic diagram of the circuit structure of another memory provided in an embodiment of this application;

[0041] Figure 5 A schematic diagram of the circuit structure of another memory provided in an embodiment of this application;

[0042] Figure 6 A schematic diagram of the circuit structure of another memory provided in an embodiment of this application;

[0043] Figure 7 This is a schematic diagram of the internal structure of a storage array provided in an embodiment of this application;

[0044] Figure 8 A schematic diagram of the circuit structure of another memory provided in an embodiment of this application;

[0045] Figure 9 A signal timing diagram provided for an embodiment of this application;

[0046] Figure 10Another signal timing diagram provided for an embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0048] A memory consists of multiple memory arrays, each of which is used to transmit one bit of stored data signal, such as... Figure 1 The diagram shows the layout of memory arrays in a memory system. Multiple memory arrays are arranged in different bank regions. The diagram shows the most significant bit (MSB) and least significant bit (LSB) of each memory array. The distance between each memory array and the D flip-flop (DFF) is different. In the diagram, the LSB is closest to the DFF, and the MSB is furthest. Each memory array triggers the reading of stored data signals by transmitting signals to the DFF. Because the distance between each memory array and the DFF is different, the signal trace lengths between each memory array and the DFF are also different. This difference in signal trace lengths can cause the stored data signals transmitted by each memory array to be out of sync, affecting the reliability of the memory.

[0049] Furthermore, in 40nm process chips, due to the larger chip size, there is sufficient clearance for the critical path, and the metal signal trace layer does not overlap with the ground layer. However, in 28nm process chips, due to the reduction in chip size, the physical distribution of the chip is somewhat limited, and the ground layer is unlikely to have a sufficiently large critical path clearance. The parasitic capacitance generated by the overlap between the ground layer and the metal layer will cause varying degrees of delay in the memory signals. This delay may lead to errors in reading stored data signals, thereby causing the driver chip to malfunction.

[0050] To improve the reliability of the memory and enable synchronous transmission of multiple storage data signals, embodiments of this application provide a memory, such as... Figure 2 As shown, the memory includes multiple storage circuits 201, multiple delay circuits 202, and a controller 203;

[0051] One of the multiple delay circuits 202 is coupled between one of the multiple storage circuits 201 and the controller 203. The multiple delay circuits 202 are used to delay the output enable signals of the multiple storage circuits 201 so that the multiple storage circuits 201 can output the stored data signals synchronously.

[0052] The memory provided in this application embodiment can delay the output enable signals of multiple storage circuits by setting multiple delay circuits. This can synchronize the storage data signals delayed by the difference in signal trace length, and can also synchronize the storage data signals delayed by the influence of parasitic capacitance, so that multiple storage circuits can output storage data signals synchronously, thereby improving the reliability of the memory.

[0053] In specific implementation, such as Figure 3 As shown, the storage circuit 201 may include: a flip-flop 2012 and a storage component 2011; the input terminal of the flip-flop 2012 is coupled to the output terminal of the storage component 2011, and the output terminal of the flip-flop 2012 is coupled to the input terminal of the controller 203.

[0054] The delay circuit 202 may include a first delay sub-circuit 2021 and / or a second delay sub-circuit 2022. Figure 3 In the circuit structure, the controller 203 and each storage circuit 201 include both a first delay sub-circuit 2021 and a second delay sub-circuit 2022. Alternatively, it may include only the first delay sub-circuit 2021 or only the second delay sub-circuit 2022, depending on the specific situation.

[0055] The first delay sub-circuit 2021 is coupled between the first signal output terminal of the controller 203 and the control terminal of the storage component 2011. It is used to delay the output preparation signal of the storage component 2011. Specifically, the first delay sub-circuit 2021 is coupled between the first signal output terminal of the controller 203 and the control terminal of the storage component 2011. It is used to delay the signal output by the first signal output terminal of the controller 203 and input the delayed signal to the control terminal of the storage component 2011. This signal is the output preparation signal, which is used to prepare for the output of the data storage signal of the storage component.

[0056] By adding a first delay sub-circuit, the delay of the stored data signal caused by the difference in signal trace length can be synchronized, thereby improving the reliability of the memory.

[0057] The second delay sub-circuit 2022 is coupled between the second signal output terminal of the controller 203 and the control terminal of the flip-flop 2012. It is used to delay the output read signal of the flip-flop 2012. Specifically, the second delay sub-circuit 2022 is coupled between the second signal output terminal of the controller 203 and the control terminal of the flip-flop 2012. It is used to delay the signal output by the second signal output terminal of the controller 203 and input the delayed signal to the control terminal of the flip-flop 2012. This signal is the output read signal. Its function is to read the stored data signal input from the storage component 2011 to the flip-flop 2012 on the rising edge of the output read signal.

[0058] In this application, a parasitic capacitance exists between the second signal output terminal of the controller 203 and the control terminal of the trigger 2012. This parasitic capacitance is formed by the overlapping of the traces between the second signal output terminal of the controller 203 and the control terminal of the trigger 2012. Each trigger 2012 has a different parasitic capacitance between its control terminal and the second signal output terminal of the controller 203. The larger the overlapping area, the larger the parasitic capacitance and the stronger the delay effect on the signal. See [link to specific overlapping area description] for details. Figure 3 The bold dashed box 300 shown illustrates trace overlap, referring to the overlap between the signal trace (located on the metal layer) between the second signal output terminal of controller 203 and the control terminal of trigger 2012, and other ground traces on the ground layer. This overlap creates parasitic capacitance, affecting signal transmission and potentially causing signal delay. Additionally, there is also overlap between the signal traces between the second signal output terminal of controller 203 and the control terminal of trigger 2012. Both of these overlap factors contribute to parasitic capacitance, affecting signal transmission.

[0059] It is worth noting that the memory provided in this application embodiment may also have parasitic capacitance caused by overlapping traces in other parts besides the 300 area. However, since the overlap between the ground layer and the metal layer is relatively severe in the signal traces between the second signal output terminal of the controller 203 and the control terminal of the flip-flop 2012, the parasitic capacitance in this part has a greater impact on the signal. Furthermore, the signal output by the second signal output terminal of the controller 203 is a clock signal, which is more sensitive to interference from parasitic capacitance and is greatly affected by it. Therefore, this application adds a second delay sub-circuit 2022 coupled between the second signal output terminal of the controller 203 and the control terminal of the flip-flop 2012 to eliminate the impact of parasitic capacitance.

[0060] In specific implementation, such as Figure 4 As shown, the storage component 2011 may include: a storage array 20111 and an operational amplifier 20112;

[0061] The first terminal of the storage array 20111 is coupled to the first input terminal of the operational amplifier 20112, and the second terminal of the storage array 20111 is coupled to the second input terminal of the operational amplifier 20112.

[0062] The control terminal of the operational amplifier 20112 is coupled to the output terminal of the first delay sub-circuit 2021, and the output terminal of the operational amplifier 20112 is coupled to the input terminal of the flip-flop 2012.

[0063] In specific implementation, such as Figure 5 As shown, both the first delay sub-circuit 2021 and the second delay sub-circuit 2022 include a first delay unit and a second delay unit;

[0064] The first terminal of the first delay unit is coupled to the power supply terminal VDD, and the second terminal of the first delay unit is grounded.

[0065] The first terminal of the second delay is coupled to the power supply terminal VDD, and the second terminal of the second delay is grounded.

[0066] The output of the first delay unit is coupled to the input of the second delay unit;

[0067] In the first delay sub-circuit 2021, the input terminal of the first delay unit is coupled to the first signal output terminal of the controller 203, and the output terminal of the second delay unit is coupled to the control terminal of the operational amplifier 20112.

[0068] In the second delay sub-circuit 2022, the input terminal of the first delayer is coupled to the second signal output terminal of the controller 203, and the output terminal of the second delayer is coupled to the control terminal of the trigger 2012.

[0069] In practical implementation, both the first and second delay units include multiple switching transistors connected in series. The delay time of each delay unit is related to the number of switching transistors it includes. More switching transistors result in a longer delay time, while fewer transistors result in a shorter delay time. Furthermore, the characteristics of the switching transistors in this application also affect the switching rate.

[0070] In a specific implementation, in the first delay sub-circuit 2021, the first delayer and the second delayer include the same number of switching transistors; in the second delay sub-circuit 2022, the first delayer and the second delayer include the same number of switching transistors.

[0071] In specific implementation, such as Figure 6As shown, taking the first and second delay units, each comprising four switching transistors, as an example, the specific structure of the delay units is explained. Both the first and second delay units include a first switching transistor M1, a second switching transistor M2, a second switching transistor M3, and a fourth switching transistor M4. The control terminal of the first switching transistor M1 is coupled to the control terminals of the second switching transistor M2, the third switching transistor M3, and the fourth switching transistor M4, respectively, and serves as the input terminal of both delay units. The first terminal of the first switching transistor M1 is coupled to the power supply terminal VDD, the second terminal of the first switching transistor M1 is coupled to the first terminal of the second switching transistor M2, the second terminal of the second switching transistor M2 is coupled to the first terminal of the third switching transistor M3, the second terminal of the third switching transistor M3 is coupled to the first terminal of the fourth switching transistor M4, and the second terminal of the fourth switching transistor M4 is grounded. The second terminal of the second switching transistor M2 serves as the output terminal of both delay units.

[0072] In this circuit, the first switch M1 and the second switch M2 are both P-type switches, and the third switch M3 and the fourth switch M4 are both N-type switches. When the signal input to the input terminal of the first delay (i.e. the signal output from the first signal output terminal of the controller) is high, the third switch M3 and the fourth switch M4 of the first delay are turned on, and the first switch M1 and the second switch M2 of the first delay are turned off. At this time, the output terminal of the first delay outputs a low-level signal. Then, the first switch M1 and the second switch M2 of the second delay are turned on, and the third switch M3 and the fourth switch M4 of the second delay are turned off. At this time, the output terminal of the second delay outputs a high-level signal, so that the high-level input is sent to the control terminal of the operational amplifier 20112 to control the stored data signal to be output from the operational amplifier and enter the input terminal of the trigger 2012.

[0073] Alternatively, the first switch M1 and the second switch M2 can both be N-type switches, and the third switch M3 and the fourth switch M4 can both be P-type switches. In this case, when the signal input to the first delay terminal is low, the third switch M3 and the fourth switch M4 of the first delay terminal are turned on, and the first switch M1 and the second switch M2 of the second delay terminal are turned on, so that a high level is input to the control terminal of the operational amplifier 20112 to control the stored data signal to be output from the operational amplifier and enter the input terminal of the trigger 2012.

[0074] It is understood that the embodiments are all described using one first delay unit and one second delay unit as examples, and different numbers of first delay units and second delay units can be set as needed. Similarly, the first delay unit and the second delay unit also include multiple first switching transistors M1, multiple second switching transistors M2, multiple second switching transistors M3 and multiple fourth switching transistors M4.

[0075] In some embodiments, the memory includes a plurality of flip-flops, each flip-flop having a different parasitic capacitance between its control terminal and the second signal output terminal of the controller, and the second delay sub-circuit 2022 between the control terminals of each flip-flop and the second signal output terminal of the controller including different numbers of first and second delay units. For example, in the direction closer to the display panel of the display device, the overlapping traces between the control terminals of the flip-flops 2012 and the ground layer and the metal layer are longer and the overlap is more severe, thus the second delay sub-circuit 2022 between the control terminals of the flip-flops and the second signal output terminal of the controller 203 includes fewer first and second delay units; or, in the direction farther from the controller 203, the overlapping traces between the control terminals of the flip-flops 2012 and the ground layer and the metal layer are longer and the overlap is more severe, thus the second delay sub-circuit 2022 between the control terminals of the flip-flops and the second signal output terminal of the controller 203 includes fewer first and second delay units.

[0076] In some embodiments, due to the significant overlap between the ground layer and metal layer in the signal trace between the second signal output terminal of the controller 203 and the control terminal of the flip-flop 2012, the parasitic capacitance in this area has a significant impact on the signal. Furthermore, since the signal output from the second signal output terminal of the controller 203 is a clock signal, which is more sensitive to interference from parasitic capacitance and is significantly affected by it, the second delay sub-circuit 2022 (circuit for transmitting clock signals) coupled between the second signal output terminal of the controller 203 and the control terminal of the flip-flop 2012 includes fewer first and second delay units than the first delay sub-circuit 2021 (circuit for transmitting data signals) coupled between the first signal output terminal of the controller 203 and the storage component 2011. For example, the first delay sub-circuit 2021 includes two first delay units and two second delay units, while the second delay sub-circuit 2022 includes one first delay unit and one second delay unit.

[0077] In some embodiments, the number of second delay sub-circuits 2022 corresponding to LSB is less than the number of second delay sub-circuits 2022 corresponding to MSB.

[0078] In some embodiments, to shorten the time difference between DATA_MSB and DATA_LSB caused by the signal line length, the number of switches in the corresponding second delay sub-circuit 2022 can be set. For example, the farther away from the controller 203, the fewer switches are required in the corresponding second delay sub-circuit 2022.

[0079] In specific implementation, such as Figure 7As shown, the storage array 20111 includes: a fifth switch M5, a sixth switch M6, a first NOT gate N1, and a second NOT gate N2;

[0080] The control terminal of the fifth switch M5 is coupled to the control terminal of the sixth switch M6. The first terminal of the fifth switch M5 serves as the first terminal of the storage array 20111. The second terminal of the fifth switch M5 is coupled to the input terminal of the first NOT gate N1 and the output terminal of the second NOT gate N2.

[0081] The first terminal of the sixth switch M6 is coupled to the output terminal of the first NOT gate N1 and the input terminal of the second NOT gate N2, and the second terminal of the sixth switch M6 serves as the second terminal of the storage array 20111.

[0082] The storage array is used to output two level signals, 0 and 1, to the operational amplifier, which then selects one of them (0 or 1) as a one-bit stored data signal for output.

[0083] The working principle of the memory provided in the embodiments of this application is explained below:

[0084] like Figure 8 The diagram shown is a complete circuit structure schematic of the memory provided in the embodiment of the application. Figure 9 In a corresponding timing diagram, the controller's first signal output terminal outputs a first control signal DASW. After signal delay by the first delay sub-circuit, DASW_EN is obtained. This signal is the operational amplifier's output preparation signal, used to prepare for the output of the stored data signal DATA. The controller's second signal output terminal outputs a second control signal CLK. After signal delay by the second delay sub-circuit, CLK_EN is obtained. This signal is the flip-flop's output read signal, and the stored data signal is read on the rising edge of CLK_EN. Figure 9 As shown, the DASW signal is delayed by the first delay sub-circuit to obtain the DASW_EN signal, which is used to prepare for the output of the stored data DATA signal; the CLK signal is delayed by the second delay sub-circuit to obtain the CLK_EN signal, which is used to read the DATA signal on its rising edge, but... Figure 9In the timing diagram shown, reading the current DATA signal of the MSB and the next NEXT DATA signal of the LSB at the rising edge of the CLK_EN signal still fails to keep the stored data signals DATA of the MSB and LSB read synchronously. This is because the delay time allocation in the second delay sub-circuit 2022 of the MSB and LSB is not optimized enough. It is necessary to further adjust the delay time of the second delay sub-circuit corresponding to the MSB and / or the delay time of the second delay sub-circuit corresponding to the LSB (this can be achieved by adjusting the number of switching transistors in the second delay sub-circuit or by selecting switching transistors with different switching speeds) to keep the stored data signals DATA of the MSB and LSB read synchronously.

[0085] In some embodiments, the rising edge of CLK_EN is shifted forward, such that the time difference between the falling edges of CLK_EN and DASW_EN is less than half of the DASW_EN period. That is, the position of the dashed box of CLK_EN is shifted forward to the position of the solid box of CLK_EN. At this time, the rising edge of CLK_EN corresponds to the same DATA signal of LSB and MSB, so that the stored data signal DATA is kept read synchronously.

[0086] like Figure 10 The diagram shown is a timing diagram after readjusting the delay times of each second delay sub-circuit 2022. For example, the number of switches in the second delay sub-circuit 2022 corresponding to the LSB can be reduced, i.e., the number of switches in the second delay sub-circuit 2022 corresponding to the LSB is less than the number of switches in the second delay sub-circuit 2022 corresponding to the MSB. This reduces the delay time, causing the rising edge of CLK_EN to move forward. That is, the position of the dashed box of CLK_EN moves forward to the position of the solid box of CLK_EN. At this time, the rising edge of CLK_EN corresponds to the same DATA signal of LSB and MSB, so that the stored data signal DATA is read synchronously.

[0087] In some embodiments, the rising edge of CLK_EN is shifted forward, such that the time difference between the falling edges of CLK_EN and DASW_EN is less than half of the DASW_EN period. That is, the position of the dashed box of CLK_EN is shifted forward to the position of the solid box of CLK_EN. At this time, the rising edge of CLK_EN corresponds to the same DATA signal of LSB and MSB, so that the stored data signal DATA is kept read synchronously.

[0088] In some embodiments, the switching speed of the switch transistor in the second delay sub-circuit 2022 corresponding to the LSB is faster than that of the switch transistor in the second delay sub-circuit 2022 corresponding to the MSB (e.g., the mobility of the switch transistor in the second delay sub-circuit 2022 corresponding to the LSB is greater than that of the switch transistor in the second delay sub-circuit 2022 corresponding to the MSB). This reduces the delay time, causing the rising edge of CLK_EN to shift forward, i.e., the position of the dashed box of CLK_EN shifts forward to the position of the solid box of CLK_EN. At this time, the rising edge of CLK_EN corresponds to the same DATA signal of the LSB and MSB, so that the stored data signal DATA is read synchronously. In some embodiments of this application, since there are different parasitic capacitances between the control terminal of each flip-flop and the second signal output terminal of the controller, the parasitic capacitance will also have a delay effect on the signal. Therefore, this application can set the delay time of the second delay sub-circuit to be less than the delay time of the first delay sub-circuit, so that the stored data signal DATA is read synchronously.

[0089] In some embodiments, while keeping the CLK signal and the DASW_EN delay unchanged, the delay time of CLK_EN is reduced, and the delay time difference between DASW_EN and CLK_EN is reduced, ensuring that the rising edge and falling edge of CLK_EN are located on the same DATA signal at the same time, that is, the rising edge and falling edge of CLK_EN are both located on the same DATA of DATA_LSB and DATA_MSB.

[0090] In some embodiments, the rising and falling edges of CLK_EN are both located on the same DATA corresponding to DATA_LSB and DATA_MSB, and the rising edge of CLK_EN is slightly later than the start of DATA_MSB, while the falling edge of CLK_EN is slightly earlier than the shutdown of DATA_LSB. This allows DATA_LSB and DATA_MSB to overlap more fully, reducing data loss and avoiding crosstalk between the current DATA signal of MSB and the next NEXT DATA signal of LSB.

[0091] It is worth noting that, Figure 8 The circuit structure diagram shown and Figure 9 and Figure 10 The timing diagram shown is only an illustration. Since memory arrays include not only LSB and MSB, but also many other memory arrays, it is sufficient to ensure that the memory data signals output by each memory array are synchronized after adding delay circuits.

[0092] Based on the same concept, embodiments of this application also provide a display device, including any of the memories described above.

[0093] This application provides a memory and a display device. The memory includes multiple storage circuits, multiple delay circuits, and a controller. One of the delay circuits is coupled between one of the storage circuits and the controller. The multiple delay circuits are used to delay the output enable signals of the multiple storage circuits, so that the multiple storage circuits output stored data signals synchronously. By setting multiple delay circuits to delay the output enable signals of the multiple storage circuits, the stored data signals delayed and synchronized due to differences in signal trace lengths, as well as due to the influence of parasitic capacitance, can be delayed and synchronized, thereby improving the reliability of the memory.

[0094] The display device described in this application embodiment can be any product or component with display function, such as electronic paper, organic light-emitting diode (OLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame or navigator.

[0095] Those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A memory, characterized in that, include: Multiple storage circuits, multiple delay circuits, and a controller; One of the multiple delay circuits is coupled between one of the multiple storage circuits and the controller. The multiple delay circuits are used to delay the output enable signals of the multiple storage circuits so that the multiple storage circuits can synchronously output stored data signals. The storage circuit includes a trigger and a storage component; the input terminal of the trigger is coupled to the output terminal of the storage component, and the output terminal of the trigger is coupled to the input terminal of the controller. The delay circuit includes a first delay sub-circuit and / or a second delay sub-circuit; The first delay sub-circuit is coupled between the first signal output terminal of the controller and the control terminal of the storage component, and is used to delay the output preparation signal of the storage component. The second delay sub-circuit is coupled between the second signal output terminal of the controller and the control terminal of the trigger, and is used to delay the output read signal of the trigger.

2. The memory as claimed in claim 1, characterized in that, There is a parasitic capacitance between the second signal output terminal of the controller and the control terminal of the trigger; The parasitic capacitance is formed by the overlapping of the wiring between the second signal output terminal of the controller and the control terminal of the trigger; In this case, there are different parasitic capacitances between the control terminal of each trigger and the second signal output terminal of the controller.

3. The memory as claimed in claim 1, characterized in that, The storage component includes: a storage array and an operational amplifier; The first end of the storage array is coupled to the first input end of the operational amplifier, and the second end of the storage array is coupled to the second input end of the operational amplifier; The control terminal of the operational amplifier is coupled to the output terminal of the first delay sub-circuit, and the output terminal of the operational amplifier is coupled to the input terminal of the trigger.

4. The memory as described in claim 3, characterized in that, Both the first delay sub-circuit and the second delay sub-circuit include a first delay unit and a second delay unit; The first terminal of the first delay is coupled to the power supply terminal, and the second terminal of the first delay is grounded; The first terminal of the second delay is coupled to the power supply terminal, and the second terminal of the second delay is grounded; The output terminal of the first delay unit is coupled to the input terminal of the second delay unit; In the first delay sub-circuit, the input terminal of the first delay unit is coupled to the first signal output terminal of the controller, and the output terminal of the second delay unit is coupled to the control terminal of the operational amplifier; In the second delay sub-circuit, the input terminal of the first delay unit is coupled to the second signal output terminal of the controller, and the output terminal of the second delay unit is coupled to the control terminal of the trigger.

5. The memory as claimed in claim 4, characterized in that, Both the first delay unit and the second delay unit include multiple switches connected in series, and the delay time of the delay unit is related to the number of switches included in the delay unit.

6. The memory as claimed in claim 4, characterized in that, In the first delay sub-circuit, the first delay unit and the second delay unit include the same number of switching transistors; In the second delay sub-circuit, the first delay unit and the second delay unit include the same number of switching transistors.

7. The memory as claimed in claim 6, characterized in that, Both the first delay unit and the second delay unit include a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; The control terminal of the first switch is coupled to the control terminals of the second switch, the third switch, and the fourth switch, respectively, and serves as the input terminal of the first delay unit and the second delay unit. The first end of the first switch is coupled to the power supply terminal, the second end of the first switch is coupled to the first end of the second switch, the second end of the second switch is coupled to the first end of the third switch, the second end of the third switch is coupled to the first end of the fourth switch, and the second end of the fourth switch is grounded. The second terminal of the second switch serves as the output terminal of both the first delay and the second delay.

8. The memory as claimed in claim 7, characterized in that, The first and second switching transistors are both P-type switching transistors, and the third and fourth switching transistors are both N-type switching transistors; or, the first and second switching transistors are both N-type switching transistors, and the third and fourth switching transistors are both P-type switching transistors.

9. The memory according to any one of claims 2-8, characterized in that, The memory array includes: a fifth switch, a sixth switch, a first NOT gate, and a second NOT gate; The control terminal of the fifth switch is coupled to the control terminal of the sixth switch. The first terminal of the fifth switch serves as the first terminal of the storage array. The second terminal of the fifth switch is coupled to the input terminal of the first NOT gate and the output terminal of the second NOT gate. The first end of the sixth switch is coupled to the output of the first NOT gate and the input of the second NOT gate, and the second end of the sixth switch serves as the second end of the memory array.

10. A display device, characterized in that, Includes the memory as described in any one of claims 1-9.

Images