Phase focus pixel structure, image sensor, electronic device and manufacturing method

Abstract

The application provides a phase focus pixel structure, an image sensor, an electronic device and a preparation method. The pixel structure comprises: a plurality of pixel regions in a substrate, a first isolation region and a second isolation region in the substrate, which divide the pixel regions into at least two sub-pixel regions to realize phase focus based on the sub-pixel regions, and the second isolation region comprises an ion-doped isolation region. The application introduces the ion-doped isolation region between the sub-pixel regions realizing phase focus, which is beneficial to improving the phase focus speed and focus effect. The application can also realize the separation of the phase focus pixels based on the ion-doped isolation region and a back deep trench isolation region. Through the design of different combinations of the ion-doped isolation region and the back deep trench isolation region, different performance emphases can be selected according to actual needs, so as to improve the overall performance of the pixel unit. The design of the application is easy to realize, compatible with the existing semiconductor manufacturing process, and does not require additional process development.

Description

Technical Field

[0001] This invention belongs to the field of image sensor manufacturing technology, and in particular relates to a phase focusing pixel structure, an image sensor, an electronic device, and a preparation method thereof. Background Technology

[0002] Image sensors utilize the photoelectric conversion function of optoelectronic devices to convert a light image on a photosensitive surface into an electrical signal proportional to the light image. Based on the different components, they can be divided into two main categories: CCD (Charge-Coupled Device) and CMOS (Metal-Oxide-Semiconductor). With the continuous development of CMOS image sensor (CIS) design and manufacturing processes, CMOS image sensors have gradually replaced CCD image sensors and become the mainstream. CMOS image sensors can be further divided into two types: FSI (Front-Side Illumination) and BSI (Back-Side Illumination).

[0003] Currently, camera systems require autofocus (AF) in many applications to ensure that relevant portions of a scene at varying distances from the camera are captured as a focused image plane. Image sensors typically use dual-pixel autofocus (DPI) to acquire information about the image's focus level. Some implementations of DPI AF employ phase detection, where a standard pixel-sized area in the image sensor array is divided into two sub-pixels. By comparing the outputs of these sub-pixels, phase-detection autofocus (PDAF) allows estimation of whether the image is in focus and provides information to a feedback system for rapid convergence of the focused image. In certain operating states, the camera system does not require autofocus and operates only in normal mode (non-focus mode), switching between autofocus and normal modes.

[0004] However, in existing autofocus pixel designs, due to limitations in manufacturing processes and pixel miniaturization, the isolation design of dual-core focusing pixels has a significant impact on pixel performance, making effective isolation difficult to achieve. Furthermore, existing isolation methods cannot flexibly select different performance emphases according to actual needs, resulting in difficulties in effectively improving the performance of focusing pixel units.

[0005] Therefore, it is necessary to provide a phase-detection focusing pixel structure, image sensor, electronic device, and fabrication method to solve the above-mentioned problems in the prior art. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a phase focusing pixel structure, image sensor, electronic device and manufacturing method to solve the problems in the prior art where the performance of focusing pixels is greatly affected by isolation, making it difficult to achieve effective isolation and making it difficult to flexibly design different performance focuses according to actual needs.

[0007] To achieve the above and other related objectives, the present invention provides a phase-detection focusing pixel structure, comprising:

[0008] The substrate comprises several pixel regions;

[0009] A first isolation region is located outside the pixel region to isolate adjacent pixel regions;

[0010] A second isolation region is located within the pixel region and extends into the substrate;

[0011] The second isolation region includes an ion-doped isolation region, and the first isolation region and the second isolation region divide the pixel region into at least two sub-pixel regions to achieve phase focusing based on the sub-pixel regions.

[0012] Optionally, the second isolation region further includes a back deep trench isolation region, wherein the back deep trench isolation region, the ion-doped isolation region, and the first isolation region together divide the pixel region into at least two sub-pixel regions.

[0013] Optionally, the back trench isolation region and the ion-doped isolation region have overlapping areas to form an overlapping isolation region. The overlapping isolation region has at least two overlapping isolation region ends, and each overlapping isolation region end is in contact with the first isolation region to divide the sub-pixel region.

[0014] Optionally, the back deep trench isolation region overlaps with the ion-doped isolation region, wherein the ion-doped isolation region has at least two doped isolation region ends, the back deep trench isolation region has at least two deep trench isolation region ends corresponding to the doped isolation region ends, and both the doped isolation region ends and the deep trench isolation region ends are in contact with the first isolation region.

[0015] Optionally, the second isolation region includes a central portion, and the back deep trench isolation structure partially overlaps with the ion-doped isolation region, wherein the central portion is configured to include the ion-doped isolation region or the overlapping area of ​​the ion-doped isolation region and the back deep trench isolation region.

[0016] Optionally, the ion-doped isolation region has at least two doped isolation region ends, each of which is in contact with the first isolation region, and the back-side deep trench isolation region has at least two deep trench isolation region ends, wherein at least one of the deep trench isolation region ends has a gap with the first isolation region to obtain the central portion formed by the overlapping region.

[0017] Optionally, each of the deep trench isolation regions has a gap between its end and the first isolation region, and the gaps between the ends of each deep trench isolation region and the first isolation region may be the same or different; and / or, the size of the back deep trench isolation region is between 1 / 3 and 2 / 3 of the size of the ion-doped isolation region.

[0018] Optionally, the ion-doped isolation region has at least two doped isolation region ends, at least one of which is spaced from the first isolation region. The back deep trench isolation region includes at least two back deep trench isolation portions, wherein one end of the back deep trench isolation portion contacts the first isolation region, and the other end contacts or overlaps with the corresponding doped isolation region end, to obtain the central portion formed by the ion-doped isolation region.

[0019] Optionally, each of the doped isolation regions has a gap between its end and the first isolation region, and the gaps between the ends of each ion-doped isolation region and the first isolation region may be the same or different; and / or, along the arrangement direction, the size of the back deep trench isolation portion is between 1 / 3 and 2 / 3 of the size of the ion-doped isolation region; and / or, the size of the area where the back deep trench isolation portion overlaps with the corresponding ion-doped end is between 0.3 and 0.5 μm.

[0020] Optionally, the first isolation region includes a peripheral ion-doped region and a peripheral deep trench region, wherein the peripheral deep trench region is located within the peripheral ion-doped region.

[0021] The present invention also provides an image sensor, the image sensor comprising a phase-focusing pixel structure as described in any of the above embodiments.

[0022] The present invention also provides an electronic device including an image sensor as described in any of the above embodiments.

[0023] The present invention also provides a method for preparing a phase-focusing pixel structure, wherein the phase-focusing pixel structure provided by the present invention is preferably prepared by the preparation method of the present invention, but other methods may also be used.

[0024] The preparation method includes the following steps:

[0025] Provide a base;

[0026] A first isolation region and a second isolation region are prepared in the substrate. The first isolation region is located outside the pixel region in the substrate to isolate adjacent pixel regions, and the second isolation region is located within the pixel region and extends into the substrate.

[0027] The second isolation region includes an ion-doped isolation region, and the first isolation region and the second isolation region divide the pixel region into at least two sub-pixel regions to achieve phase focusing based on the sub-pixel regions.

[0028] Optionally, the preparation of the second isolation region further includes the step of preparing a back deep trench isolation region in the substrate, wherein the back deep trench isolation region corresponds to the ion-doped isolation region, and the back deep trench isolation region, the ion-doped isolation region, and the first isolation region together divide the pixel region into at least two sub-pixel regions.

[0029] Optionally, the fabrication steps of the back deep trench isolation region and the ion-doped isolation region include:

[0030] The ion-doped isolation region is prepared in the substrate, having at least two doped isolation region ends;

[0031] The back deep trench isolation region is prepared corresponding to the ion-doped isolation region, and the back deep trench isolation region has at least two deep trench isolation region ends corresponding to the ends of the doped isolation region;

[0032] In this configuration, the ends of all the doped isolation regions are in contact with the first isolation region, and at least one of the ends of the deep trench isolation regions has a gap with the first isolation region, so as to obtain the second isolation region in the center formed by the overlapping area of ​​the ion-doped isolation region and the back deep trench isolation region.

[0033] Optionally, the fabrication steps of the back deep trench isolation region and the ion-doped isolation region include:

[0034] The ion-doped isolation region is prepared in the substrate, having at least two doped isolation region ends;

[0035] The back deep trench isolation region is prepared corresponding to the ion-doped isolation region, and the back deep trench isolation region has at least two back deep trench isolation portions corresponding to the ends of the doped isolation region;

[0036] Wherein, at least one of the ends of the doped isolation region has a gap with the first isolation region, one end of the back deep trench isolation portion is in contact with the first isolation region, and the other end is in contact with or overlaps with the corresponding end of the doped isolation region, so as to obtain the second isolation region in the center composed of the ion-doped isolation region.

[0037] Optionally, the fabrication of the ion-doped isolation region and the back-side deep trench isolation region includes:

[0038] The ion-doped isolation region is formed from a first surface of the substrate; and the back trench isolation region is prepared from a second surface of the substrate, with the second surface opposite to the first surface.

[0039] Optionally, the first isolation region includes a peripheral ion-doped region and a peripheral deep trench region, wherein the fabrication steps of the first isolation region and the second isolation region include:

[0040] The peripheral ion-doped region and the ion-doped isolation region are simultaneously fabricated in the substrate using the same mask; or, the peripheral ion-doped region is fabricated using a first mask, and the ion-doped isolation region is fabricated using a second mask.

[0041] And / or, the peripheral deep trench region and the back deep trench isolation region are prepared using the same process.

[0042] As described above, the phase-detection autofocus pixel structure, image sensor, electronic device, and fabrication method of the present invention, by introducing ion-doped isolation structures between the sub-pixel regions that achieve phase-detection autofocus, can improve the phase-detection autofocus speed and focusing effect. The present invention can also achieve phase-detection pixel isolation based on ion-doped isolation regions and back-side deep trench isolation regions. By matching different combinations of ion-doped isolation regions and back-side deep trench isolation regions, designs with different performance focuses can be selected according to actual needs, thereby improving the overall performance of the pixel unit. The design of the present invention is easy to implement, compatible with existing semiconductor fabrication processes, and requires no additional process development. Full-pixel phase-detection autofocus can be achieved based on the design of the present invention. Attached Figure Description

[0043] Figure 1 The diagram shown is a framework diagram of the image sensor structure system provided in an embodiment of the present invention.

[0044] Figure 2 The diagram shows the fabrication process flow of the phase-focusing pixel structure provided in an embodiment of the present invention.

[0045] Figure 3-8 The diagram shows the structural schematics obtained in each step of the phase focusing pixel structure fabrication process in Embodiment 1 of the present invention.

[0046] Figure 9-12 The diagram shows the structural schematics obtained in each step of the phase focusing pixel structure preparation process in Embodiment 2 of the present invention.

[0047] Figure 13-14 The diagram shows the structural schematics obtained in each step of the phase focusing pixel structure preparation process in Embodiment 3 of the present invention.

[0048] Figure 15-16 The diagram shows top views of different examples of phase-detection pixel structures in Embodiment 4 of the present invention.

[0049] Figure 17-18 The diagram shows top views of different examples of the phase-detection pixel structure in Embodiment 5 of the present invention.

[0050] Figure 19-20 The diagram shows a one-pixel unit layout based on the two-sub-pixel region pixel unit design of Embodiment Six of the present invention.

[0051] Figure 21-22 The diagram shows a pixel unit layout based on the pixel unit design of the four sub-pixel regions in Embodiment Six of the present invention.

[0052] Figure 23 The diagram shows an example of pixel circuit connection based on the phase focusing pixel structure designed in this invention.

[0053] Component designation explanation

[0054] 101 base

[0055] 101a First Page

[0056] 101b Second Page

[0057] 101c thinned substrate back side

[0058] 102 Peripheral Ion Doped Region

[0059] 103 Ion-doped isolation region

[0060] Ends of doped isolation regions 103a, 103b, 103c, and 103d

[0061] 104 Interconnection Layer

[0062] 105 Supporting substrate

[0063] 106 Thinned substrate

[0064] 107 Peripheral Deep Trench Area

[0065] 108 First Quarantine Zone

[0066] 109 pixel area

[0067] 109a sub-pixel region

[0068] 110 Backside deep trench isolation area

[0069] 1101, 1102, 1103, 1104 Backside Deep Groove Isolation Section

[0070] Ends of deep trench isolation zones 110a, 110b, 110c, and 110b

[0071] 111 Second Quarantine Zone

[0072] 200-pixel array

[0073] 201 pixel area

[0074] 201a sub-pixel region

[0075] 202 microlenses

[0076] Steps S1 to S2 Detailed Implementation

[0077] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0078] For ease of description, spatial relation terms such as "below," "below," "lower than," "below," "above," and "upper" may be used herein to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between; "located between" includes a region located between both, which may also be in contact with both; "between" as used in this invention includes two endpoint values. In the context of this application, the described structure of a first feature "above" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0079] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0080] The following detailed description of the invention is provided in conjunction with the accompanying drawings.

[0081] Figure 1 This is shown as a basic structural block diagram of an image sensor system. (Example:) Figure 1 As shown, the image sensor includes a readout circuit and a control circuit connected to the pixel array. A functional logic unit is connected to the readout circuit to perform logic control on the reading of the pixel circuit. The readout circuit and the control circuit are connected to a status register to realize the reading control of the pixel array. The pixel array includes multiple pixel units arranged in rows (R1, R2, R3...Ry) and columns (C1, C2, C3...Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out by the readout circuit with the readout mode specified by the status register, and then transmitted to the functional logic unit. In specific applications, the readout circuit may include an analog-to-digital converter (ADC) circuit, an amplifier circuit, and others. In some application embodiments, the status register may contain a programmed selection system to determine whether the readout system reads out in a rolling shutter mode or a global shutter mode. The functional logic unit may store only image data or image data applied or processed by image effects. In one application example, the readout circuit may be along the readout column lines (e.g., Figure 1 (As shown) Image data is read out one line at a time, or various other methods can be used to read out image data. The operation of the control circuitry is determined by the current settings of the status register. For example, the control circuitry generates a shutter signal to control image acquisition. In some applications, this shutter signal can be a global exposure signal that allows all pixels of the pixel array to acquire their image data simultaneously through a single acquisition window. In other applications, this shutter signal can be a rolling exposure signal, where each pixel row is read out continuously through the acquisition window.

[0082] Depending on the focusing requirements of the actual application, some image sensors require a dual-pixel focusing design. For autofocus, in a specific example, phase detection autofocus (PDAF) can be used. The image acquisition device (such as a camera) uses the image sensor to obtain phase detection data of the image and estimates the focus position based on the linear relationship between the phase detection data and the lens position. In this way, the lens can be moved to the focus position in one step based on phase detection autofocus, thus quickly completing the focusing action.

[0083] However, due to limitations in manufacturing processes and pixel miniaturization, the isolation design of dual-core focusing pixels significantly impacts pixel performance. This invention addresses this issue by proposing a novel design approach. This invention provides a phase-detection focusing pixel structure, an image sensor, an electronic device, and a fabrication method. The phase-detection focusing pixel structure enables phase-detection focusing and also allows for image acquisition in normal shooting modes. The design of this invention is easy to implement, compatible with existing semiconductor fabrication processes, and requires no additional process development. Furthermore, it improves pixel unit performance, allowing for the selection of designs with different performance emphases based on actual needs.

[0084] in, Figure 2-18 The diagram shows the fabrication process flow chart of the phase-focusing pixel structure of the present invention, as well as schematic diagrams of the structures obtained in each step of the fabrication process. Figure 19-22 The image shown is an example of the layout design of the phase-detection pixel structure provided by this invention. Figure 23 The diagram shown is a circuit connection schematic based on the phase focusing pixel structure of the present invention in one example. Figure 8 , Figure 12 , Figure 14-18 This is a top view schematic diagram of the phase-focusing pixel structure obtained in different embodiments of the present invention.

[0085] The following will provide a detailed description of different embodiments.

[0086] Example 1:

[0087] like Figure 2-8As shown, this embodiment provides a phase-detection focusing pixel structure and its fabrication method. Please refer to [link to documentation]. Figure 7 and Figure 8 As shown, the phase-detection pixel structure includes: a substrate, a first isolation region, and a second isolation region, wherein the second isolation region includes an ion-doped isolation region. The first isolation region and the second isolation region divide the pixel region into at least two sub-pixel regions to achieve phase detection based on the sub-pixel regions.

[0088] Based on the above design, by introducing ion-doped isolation regions, it is possible to achieve sub-pixel region isolation to satisfy phase focusing (PDAF) while improving the quantum efficiency (QE) of the relative focusing pixel structure in image acquisition.

[0089] The fabrication method of the phase-detection focusing pixel structure of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that... Figure 2 The order shown does not strictly represent the fabrication order of the phase-focusing pixel structure protected by this invention, and those skilled in the art can change it according to the actual process steps. Figure 2 Only one example of the invention is shown.

[0090] First, such as Figure 2 S1 and Figure 3 As shown, step S1 is performed, providing a substrate 101.

[0091] Specifically, the substrate 101 can be any structure used in the field of image sensors for fabricating various functional regions, such as the photosensitive element and various control transistors of a CMOS image sensor fabricated based on the substrate 101. The substrate 101 can be a structure composed of a single layer of material, including but not limited to a silicon substrate, in which the components in each region are fabricated. This silicon substrate can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, or a silicon-germanium compound; in this embodiment, monocrystalline silicon is selected. The substrate 101 can also be silicon-on-insulator (SOI).

[0092] Alternatively, the substrate 101 can be a stacked structure consisting of two or more material layers, with each region fabricated within any required layer. For example, the substrate 101 may include a silicon substrate and an epitaxial layer (EPI) formed on the silicon substrate, with photosensitive elements and various control transistors fabricated in the epitaxial layer, such as a back-illuminated (BSI) image sensor fabricated based on the above structure. Furthermore, the substrate 101 can also be a structure with n-type doping or p-type doping to meet the functional requirements of the device.

[0093] Please see Figure 3As shown, in one example, the substrate 101 has a first surface 101a and a second surface 101b opposite to each other. In an alternative example, the first surface 101a is formed as one side of the substrate, and the second surface 101b is formed as one side of an epitaxial layer on the substrate. Of course, in other examples, the first surface and the second surface can also be formed as the front and back sides of the substrate opposite to each other.

[0094] Next, as Figure 2 S2 and Figure 4-8 As shown, in step S2, a first isolation region 108 and a second isolation region are prepared in the substrate 101. The first isolation region is located on the periphery of the pixel region 109 of the substrate 101 to isolate adjacent pixel regions 109. The second isolation region is located within the pixel region 109 and extends into the substrate 101.

[0095] The second isolation region includes an ion-doped isolation region 103. The first isolation region 108 and the second isolation region divide the pixel region 109 into at least two sub-pixel regions 109a to achieve phase focusing based on the sub-pixel regions.

[0096] The fabrication process of the ion-doped isolation region 103 shown includes, but is not limited to, ion implantation. As an example, in the isolation process using ion implantation, B or BF2 is used as the ion implanter, with an implantation energy between 10 keV and 1100 keV, and an ion implantation dose between 3e11 and 1e13. Of course, other doping designs for achieving phase focusing can be implemented according to actual needs.

[0097] Specifically, the diagram illustrates the division of pixel region 109 into two sub-pixel regions 109a as an example; however, other numbers of focusing sub-pixels could also be used. Furthermore, this example uses the process of forming a back-illuminated image sensor as an example. The execution of each step is explained below:

[0098] First, please refer to Figure 4 As shown, the ion-doped isolation region 103 is formed in the substrate 101 from a first surface (e.g., front surface) 101a. In one example, the first isolation region shown includes a peripheral ion-doped region 102.

[0099] In this embodiment, the peripheral ion-doped region 102 is used in conjunction with subsequent processes to prepare a first isolation region, achieving isolation between various pixel regions. The ion-doped isolation region 103 is used to form a second isolation region, further dividing the pixel region into sub-pixel regions for phase focusing. In this embodiment, the ion-doped isolation region 103 serves as the second isolation region alone, located within the pixel region to achieve sub-pixel isolation. In the phase-focusing pixel structure, using the ion-doped isolation region 103 as the isolation structure for the focusing sub-pixels can improve the quantum efficiency of the pixel when obtaining a normal image.

[0100] As an example, the width p of the ion-doped isolation region 103 is between 0.3 and 0.5 μm, for example, it can be 0.35 μm, 0.4 μm, or 0.45 μm. Of course, other settings can be made according to actual needs.

[0101] As an example, the peripheral ion-doped region 102 and the ion-doped isolation region 103 are fabricated using the same ion implantation process under the same mask. In one example, the peripheral ion-doped region 102 and the ion-doped isolation region 103 are configured identically, for example, they have the same doping concentration, type, implantation depth, and width.

[0102] It should also be noted that other structures required for the pixel structure of the image sensor can be fabricated in the substrate 101 based on existing processes. For example, photodiodes (PD), transmission transistors (TX), floating diffusion points (FD), reset transistors (RST), source follower transistors (SF), and row select transistors (RS) can be fabricated in the substrate to form 3T, 4T, 5T, and other pixel structures. This fabrication can be carried out after the peripheral ion-doped region 102 and the ion-doped isolation region 103 are fabricated using existing processes. Of course, other process steps can also be designed, without unduly limiting the scope of protection of this invention. In this embodiment, all the transistors mentioned above are selected as N-type; however, it is understood that they can also be P-type in other implementations.

[0103] Next, please refer to Figure 5 As shown, an interconnect layer 104 and a support substrate 105 are formed on the first surface 101a of the substrate.

[0104] Specifically, the interconnect layer 104 and the supporting substrate 105 can be fabricated using existing structures and processes. The interconnect layer 104 realizes the interconnection of various transistors, such as including metal layers and dielectric layers. The supporting substrate 105 can provide support after the substrate 101 is flipped, and the required logic circuits can be set in the supporting substrate 105 using methods commonly used in the art. Of course, before forming the interconnect layer 104 and the supporting substrate 105, the process may include treating the first surface 101a of the substrate or forming a material layer thereon, all of which are within the scope of protection of this invention.

[0105] Finally, please refer to Figures 6-7. In one example, the first isolation region is further comprising a peripheral deep trench region 107. The preparation method includes: flipping the substrate 101 so that the second side (such as the back side) 101b faces upward to prepare the peripheral deep trench region 107, thereby obtaining a first isolation region 108 composed of the peripheral ion-doped region 102 and the peripheral deep trench region 107.

[0106] Specifically, in one example, the peripheral deep trench region 107 can be a back deep trench isolation structure (BDTI), which can be fabricated using existing processes.

[0107] As an example, before forming the peripheral deep trench region 107, a back-side thinning step is included on the substrate 101 to obtain a thinned substrate 106 with a thinned surface 101c. The thinned surface 101c has a gap between it and the bottom of the ion-doped isolation region 103 and the bottom of the peripheral ion-doped region 102; here, the bottom is the bottom at the time of implantation, and after flipping... Figure 7 The middle part corresponds to the upper surface. Of course, the size of the spacing can be determined according to the actual process design, or in other examples, it is preferable not to have the spacing and directly thin it to the bottom of the ion-doped isolation region and the peripheral ion-doped region.

[0108] in, Figure 8 The diagram shows a top view of the phase-focusing pixel structure prepared through the above steps. It can be seen that the ion-doped isolation region 103 is formed between the two sub-pixel regions 109a as an isolation layer, which can improve quantum efficiency while achieving phase focusing. Of course, the number of sub-pixel units 109a can also be other numbers, such as 4, 6, or 8, and is not limited to this. Furthermore, in one example, the ion implantation process of the peripheral doped region 102 and the ion-doped isolation region 103, along with the process of forming the back-side deep trench isolation structure (BDTI), are performed from both surfaces of the substrate, as in the back-illuminated sensor image preparation process described above. Other methods can also be used to obtain the isolation region of this invention to obtain the relative focusing pixel.

[0109] In this example, the pixel area 109 is divided into two sub-pixel areas 109a. The pixel areas 109 can be designed with the same length and width, forming a square layout. Optionally, the side length of the square is between 1.0 and 1.5 μm; for example, it can be a 1.2 × 1.2 μm pixel area design. Alternatively, in this example, in a subsequent fabrication process, a microlens can cover the pixel area 109, that is, cover both sub-pixel areas 109a, such as the 1.2 × 1.2 μm pixel area, with the microlens diameter being the diagonal length.

[0110] Example 2:

[0111] like Figure 9-12 As shown, this embodiment two provides a phase focusing pixel structure and its fabrication method. The main difference between this embodiment two and embodiment one is that the fabrication processes of the peripheral ion-doped region 103 and the ion-doped isolation region 102 are different. Other aspects are the same as or similar to embodiment one, and can be found in the description in embodiment one, which will not be repeated here.

[0112] Specifically, the preparation of the peripheral ion-doped region 103 and the ion-doped isolation region 102 in this embodiment is carried out in two steps: the peripheral ion-doped region 102 is prepared using a first mask; the ion-doped isolation region 103 is prepared using a second mask. The order of the two steps can be selected according to the actual process. In this example, the peripheral ion-doped region 102 is prepared first.

[0113] By performing two ion implantations using the above-described process, structural defects caused by limitations in existing photoresist processes can be improved. In the phase-focusing pixel structure of this invention, based on the design of the above process, the full-well capacity (FW) can be increased while satisfying phase-focusing autofocus (PDAF) by controlling the width of the ion-doped isolation region 102.

[0114] Specifically, firstly, such as Figure 9 As shown, the peripheral ion-doped region 102 is prepared using a first mask, and existing processes can be used to prepare the peripheral ion-doped region 102; then, as... Figure 10 As shown, the ion-doped isolation region 103 is prepared using a second mask, and existing processes can be used to prepare the ion-doped isolation region 103. The first mask and the second mask can be different masks, or they can be the same mask provided the pixel size requirement is met.

[0115] in addition, Figure 11 This is a schematic diagram of a longitudinal section after the formation of the outer deep trench area 107 and the formation of the first isolation area 108. Figure 12The diagram is shown as a top view. The specific process and structure can be found in Embodiment 1. It should be noted that, as those skilled in the art will understand, the different filling colors of the peripheral ion-doped region 103 and the ion-doped isolation region 102 in this embodiment represent that the fabrication process steps are performed separately, and the materials for both can be the same or different.

[0116] Example 3:

[0117] like Figure 13-14 As shown, this third embodiment provides a phase-focusing pixel structure and its fabrication method. The difference between this third embodiment and embodiments one and two is that it further includes a back-side deep trench isolation region 110, such that the ion-doped isolation region 103 and the back-side deep trench isolation region 110 constitute a second isolation region 111. Other aspects are the same as or similar to embodiments one and two, and can be found in the descriptions in embodiments one and two, which will not be repeated here.

[0118] In this embodiment, the second isolation region further includes a back deep trench isolation region, which includes, but is not limited to, a back deep trench isolation structure (BDTI). The back deep trench isolation region, the ion-doped isolation region, and the first isolation region together divide the pixel region into at least two sub-pixel regions.

[0119] In the above manner, the present invention can achieve different performance requirements by using different combinations of the back deep trench isolation region 110 and the ion-doped isolation region 103, and select designs with different performance focuses according to actual needs, thereby improving the overall pixel performance.

[0120] In one example, the back trench isolation region 110 and the ion-doped isolation region 103 have overlapping isolation regions. Each overlapping isolation region has at least two ends, and these ends are in contact with the first isolation region to delineate the sub-pixel area. In other words, in this example, the overlapping isolation region has both the structure of the back trench isolation region and the structure of the ion-doped isolation region; the combination of these two achieves sub-pixel separation. An overlapping arrangement can be chosen, leveraging the back trench isolation region to improve isolation. While sacrificing some quantum efficiency (QE), this can significantly improve phase focusing performance, resulting in images that are easier to focus on.

[0121] For a specific example, please refer to Figure 14As shown, mutually perpendicular x and y directions are defined on the substrate surface. In the y direction, the back deep trench isolation region 110 coincides with the ion-doped isolation region 103, and they are in uniform first isolation region contact. In the x direction, the edge of the back deep trench isolation region does not extend beyond the edge of the ion-doped isolation region, and the overlapping part of the two constitutes the overlapping isolation region. In one example, the back deep trench isolation region is fabricated in the ion-doped isolation region, meaning that the back deep trench isolation region does not extend beyond the ion-doped isolation region in the part where it contacts the ion-doped isolation region. When there is a gap between the ion-doped isolation region and the thinned surface of the substrate, the back deep trench isolation structure has a portion located above the ion-doped isolation region.

[0122] Specifically, such as Figure 13 As shown, in one example, the back deep trench isolation region 110 can be fabricated using the same process as the peripheral deep trench region 107, thus eliminating the need for additional process steps and achieving the effect of this embodiment. Furthermore, Figure 14 The diagram shows a top view of the structure obtained after preparation. It should be noted that the structure shown in the accompanying drawings of this embodiment is based on the process of Example 2, and of course, it can also be based on the process of Example 1.

[0123] Please continue reading. Figure 13 and Figure 14 As shown, as an example, the back deep trench isolation region 110 is located in the ion-doped isolation region 103, wherein the ion-doped isolation region 103 has at least two doped isolation region ends, the deep trench isolation region 110 has at least two deep trench isolation region ends corresponding to the doped isolation region ends, and both the doped isolation region ends and the deep trench isolation region ends are in contact with the first isolation region 108.

[0124] As an example, see Figure 13 As shown, the depth of the back trench isolation region is between 1.5-2 μm, such as 1.8 μm. Furthermore, the distance w between the bottom of the back trench isolation region and the underlying interconnect layer can be set according to actual needs and process requirements. See also... Figure 14 As shown, along the x-direction in the figure, the width q of the back trench isolation region 110 is between 1 / 2 and 1 of the width p of the ion-doped isolation region 103; for example, this ratio can be set to 2 / 3. In an optional example, the width p of the ion-doped isolation region 103 is between 0.3 and 0.4 μm, such as 0.35 μm, and the width q of the back trench isolation region 110 is between 0.2 and 0.3 μm, such as 0.25 μm.

[0125] Example 4:

[0126] like Figure 15-16As shown, this fourth embodiment provides a phase-focusing pixel structure and its fabrication method. The difference between this fourth embodiment and embodiments one to three is that the ion-doped isolation region 103 and the back-side deep trench isolation region 110 partially overlap, combining to form a second isolation region, forming a central portion M. Other aspects are the same as or similar to embodiments one to three, and can be found in the descriptions of the foregoing embodiments, which will not be repeated here. Through the above method, the design of the sub-pixel isolation region can be flexibly configured, thereby obtaining phase-focusing pixel structures with different requirements.

[0127] As an example, the second isolation zone includes a central portion, which can be seen in [reference needed]. Figure 15 and Figure 16 As shown in the elliptical dashed box M, the back deep trench isolation region 110 and the ion-doped isolation region 103 are partially overlapped. The ion-doped isolation region (see...) Figure 15 (as shown) or the overlapping region of the ion-doped isolation region and the deep trench isolation region (see...) Figure 16 The central part M is constituted as shown.

[0128] Please see Figure 15 As shown, in one example, the ion-doped isolation region 103 has at least two doped isolation region ends 103a and 103b, at least one of the doped isolation region ends having a gap with the first isolation region 108, wherein, Figure 5 The diagram shows that both of them have a gap between them and the first isolation zone 108.

[0129] Furthermore, the back trench isolation region 110 includes at least two back trench isolation portions 110a and 110b. Taking the back trench isolation portion 110a as an example, one end of the back trench isolation portion 110a is in contact with the first isolation region 108, and the other end is in contact with or overlaps with the corresponding end of the doped isolation region (such as the end of the doped isolation region 103a). The figure shows an example of overlap to obtain the central portion formed by the ion-doped isolation region 103. Similarly, the back trench isolation portion 110b and the end of the doped isolation region 103b have the same or similar configuration, which can be selected by those skilled in the art.

[0130] Based on the above design, the center of the second isolation region can be understood as a portion extending within a certain size from the center of symmetry of the pixel area, and preferably with the same size extending outward from this center. In this example, the central part is an ion-doped isolation region, and the two ends (the parts near the first isolation region) are respectively set as back-side deep trench isolation regions, forming the second isolation region to divide the focusing sub-pixel area. This can improve the quantum efficiency (QE) while achieving phase focusing, and further facilitates the achievement of QE in ordinary image acquisition and focusing effect in phase focusing PDAF.

[0131] As an example, each of the doped isolation regions has a gap between its end and the first isolation region, and the gaps between the ends of each ion-doped isolation region and the first isolation region may be the same or different. For example, such as Figure 15 As shown, the values ​​of s1 and s2 can be the same or different, and preferably they have the same size.

[0132] As an example, along the arrangement direction, such as the y-direction, the size of the back deep trench isolation portion is between 1 / 3 and 2 / 3 of the size of the ion-doped isolation region; for example, it can be selected as 1 / 2. For example, as... Figure 15 As shown, s1 = 1 / 2s0; s2 = 1 / 2s0, and the values ​​of s1 and s2 are the same, in order to achieve the ideal symmetrical design.

[0133] As an example, the size of the area where the back trench isolation portion overlaps with the corresponding ion-doped end is between 0.3 and 0.5 μm, for example, it can be selected as 0.35 μm, 0.4 μm, or 0.45 μm.

[0134] Additionally, please see Figure 16 As shown, in one example, the ion-doped isolation region 103 has at least two doped isolation region ends 103a and 103b, both of which are in contact with the first isolation region 108. The deep trench isolation region 110 has at least two deep trench isolation region ends 110a and 110b, wherein at least one of the deep trench isolation region ends has a distance d1 and d2 between it and the first isolation region, to obtain the central portion M formed by the overlapping area of ​​the ion-doped isolation region and the deep trench isolation region. Based on the above design, the PDAF effect can be effectively improved with fewer white spots (WP).

[0135] As an example, each of the deep trench isolation areas has a gap between its end and the first isolation area, and the gaps between the ends of each deep trench isolation area and the first isolation area may be the same or different. For example, as... Figure 16 As shown, the values ​​of d1 and d2 can be the same or different, but preferably they have the same size.

[0136] As an example, the size of the back-side deep trench isolation region is between 1 / 3 and 2 / 3 of the size of the ion-doped isolation region, such as 1 / 2. For example, as... Figure 16 As shown, along the extension direction, i.e. the y-direction, the dimensions of the ion-doped isolation region are d0 = 2d1 = 2d2, and their centers coincide. The back deep trench isolation region is vertically symmetrical about the central axis of the pixel region to achieve an ideal symmetrical design.

[0137] Example 5:

[0138] like Figure 17-18 As shown, this embodiment provides another phase-detection autofocus pixel unit structure and fabrication method. The difference between this embodiment and embodiments one to four is that this embodiment designs four sub-pixel regions to achieve phase-detection autofocus and also enables image acquisition in normal mode. Other aspects are the same as or similar to embodiments one to four, and can be found in the descriptions of the foregoing embodiments, which will not be repeated here. Through the above method, the design of the sub-pixel isolation regions can be flexibly configured, thereby obtaining phase-detection autofocus pixel structures to meet different needs.

[0139] For details, please refer to Figure 17 As shown, the structure of this example is similar to... Figure 15 Similar to the structure shown, a second isolation region with a central portion is designed. The ion-doped isolation region serves as the central portion, distributed in a cross shape at the center of the four sub-pixel regions, preferably a symmetrical cross shape. The ends are isolated from the first isolation region by contacting the back deep trench isolation portions. The ion-doped region 103 has four doped region ends 103a, 103b, 103c, and 103d. Correspondingly, the deep trench isolation region 110 has four corresponding back deep trench isolation portions 1101, 1102, 1103, and 1104, which together form the second isolation region. The dimensional design of each part can be found in the description of the previous embodiment, and will not be repeated here.

[0140] Based on the above design, sub-pixels can improve quantum efficiency (QE) during pixel image acquisition while satisfying omnidirectional pixel autofocus (ADAF).

[0141] Additionally, please see Figure 18 As shown, the structure of this example is similar to... Figure 16Similar to the structure shown, a second isolation region with a central portion is designed. The overlapping area of ​​the ion-doped isolation region and the back-side deep trench isolation region serves as the central portion, distributed in a cross shape at the center of the four sub-pixel regions, preferably a symmetrical cross shape. The ends are formed by the remaining ion-doped isolation regions. Specifically, the ion-doped region 103 has four ion-doped region ends 103a, 103b, 103c, and 103d, and correspondingly, the deep trench isolation region 110 has four corresponding deep trench isolation region ends 110a, 110b, 110c, and 110d, together forming the second isolation region. The dimensional design of each part can be found in the description of the previous embodiment, and will not be repeated here.

[0142] Based on the above design, subpixels can significantly improve the omnidirectional pixel autofocus (ADAF) effect when focusing with fewer white points (WP).

[0143] In this embodiment, the pixel area 109 is divided into four sub-pixel areas 109a. The pixel areas 109 can be designed with the same length and width, forming a square layout. Optionally, the side length of the square is between 2.0 and 2.5 μm; for example, it can be a 2.4 × 2.4 μm pixel area design. Each sub-pixel area 109a has a size of 1.2 × 1.2 μm. Alternatively, in this example, in a subsequent fabrication process, a microlens can cover the pixel area 109, that is, cover all four sub-pixel areas 109a, such as the 2.4 × 2.4 μm pixel area, with the microlens diameter being the diagonal length.

[0144] It should be noted that due to limitations in manufacturing processes and pixel miniaturization, the isolation design of dual-core focusing pixels has a significant impact on pixel performance. Based on the design of this invention, different performance-focused designs can be selected according to actual needs, thereby improving the overall performance of the pixel structure. For example, when a better quantum efficiency (QE) and slightly worse phase-detection autofocus (PDAF) effect are required, the method in Example 1 can be selected; when a better full-well capacity (FW) and slightly worse phase-detection autofocus (PDAF) effect are required, the method in Example 2 can be selected; when a better phase-detection autofocus (PDAF) effect is required and slightly worse quantum efficiency (QE) is required, the method in Example 3 can be selected; when both a better quantum efficiency (QE) and a relatively good phase-detection autofocus (PDAF) effect are required, the scheme in Example 4, where a single ion-doped isolation region is used as the central part, can be selected; when a better phase-detection autofocus (PDAF) effect is required and a small amount of white spot (WP) can be received, the overlapping area of ​​the ion-doped isolation region and the back deep trench isolation region in Example 4 can be used as the central part. Similarly, based on the above, the corresponding effect of omnidirectional pixel-based autofocus (ADAF) can be achieved through the four sub-pixel scheme in Example 5.

[0145] Example 6:

[0146] Please see Figure 19-22 As shown, this invention provides a phase-detection autofocus pixel structure, including a pixel array and a pixel circuit. Those skilled in the art will understand that the pixel circuit refers to the circuit that electrically connects the pixel area for signal transmission, and can form existing 4T, 8T, and other structures. It should be noted that this embodiment mainly discloses the layout design of the phase-detection autofocus pixel unit of this invention. The pixel unit of this embodiment may also include the configuration of the first isolation region and the second isolation region as described in any of the schemes in Embodiments I and II, as detailed in the descriptions of the foregoing embodiments, and will not be repeated here.

[0147] Specifically, the pixel array includes several pixel regions arranged in an array, for example, several rows along the x-direction and several columns along the y-direction in a two-dimensional coordinate system. Furthermore, each pixel region includes at least two sub-pixel regions, and each sub-pixel region is provided with a photosensitive element, including but not limited to a photodiode. The number of sub-pixel regions divided into each pixel region is determined according to actual needs, preferably an even number. See the preceding embodiment description for details.

[0148] In addition, the pixel circuit includes at least a transmission transistor, a floating diffusion point, and a source follower transistor. The transmission transistor corresponds to the photosensitive element and its two ends are electrically connected to the photosensitive element and the floating diffusion point, respectively. The source follower transistor is connected to the floating diffusion point. The transmission transistor is disposed at the corner of the corresponding photosensitive element, and four transmission transistors are arranged opposite each other to form an opening. The source follower transistor is located in the opening.

[0149] The structure of each transistor in the pixel circuit can adopt the design of existing CMOS image sensors. In this invention, the phase-detection pixel structure is configured as a four-element shared structure to improve the phase-detection focusing effect.

[0150] Specifically, the pixel unit includes a first focusing pixel group and a second focusing pixel group. The first focusing pixel group is configured to sense a first light to obtain a first focused image; the second focusing pixel group is configured to sense a second light to obtain a second focused image. The first focusing pixel group includes at least one sub-pixel region of the pixel region, and the second focusing pixel group includes at least one additional sub-pixel region within the pixel region. That is, in each pixel region, at least one sub-pixel region is used to obtain the first focused image, and at least one sub-pixel region is used to obtain the second focused image.

[0151] Please see Figure 19-20 The diagram shown is an example schematic of a two-subpixel design based on the present invention.

[0152] Specifically, the phase-detection focusing pixel structure includes a pixel array 200, each pixel region includes two sub-pixel regions 200a, and two adjacent pixel regions form four sub-pixel regions with a shared structure, corresponding to four photosensitive elements PD0, PD1, PD2, and PD3. The transmission transistors TX0, TX1, TX2, and TX3 corresponding to each sub-pixel region are arranged at an angle at the corner of the corresponding photosensitive element, for example, at 45°. The four transmission transistors of adjacent pixel regions are arranged facing each other to form an opening, and two adjacent pixel regions forming the opening share the same pixel circuit.

[0153] As an example, the pixel circuit further includes a reset transistor RST and a row selection transistor RS, which are located on opposite sides of two pixel regions sharing the same pixel circuit. As shown in the figure, one is located outside a photodiode PD0, and the other is located outside a photodiode PD2 diagonally opposite to it.

[0154] As an example, the pixel circuit also includes a gain control transistor DCG. Each pixel region includes two floating diffusion points FD1 and FD2. The sub-pixel regions of two adjacent pixel regions share the corresponding floating diffusion points, such as PD1 and PD2 sharing FD1, and PD0 and PD3 sharing FD2. The gain control transistor and the source follower transistor are distributed on both sides of the floating diffusion point, for example, on both sides of FD1. Of course, in other examples, they can also be set on both sides of FD2.

[0155] Further optionally, when the gain control transistor DCG is present, the reset transistor RST is disposed outside the photodiode close to the gain control transistor, as shown in the figure, which can be disposed outside PD1 or PD2. On this basis, the row selection transistor RS is arranged diagonally to improve the symmetry of the pixel array, reduce interconnection lines, and facilitate phase focusing. In this example, RST is shown to be disposed outside PD2.

[0156] In addition, such as Figure 20 As shown, the pixel unit further includes a plurality of microlenses (ML) 202, each microlens corresponding one-to-one with a pixel region. In this example, each microlens corresponds to two sub-pixel regions of a pixel region.

[0157] Please see Figure 21-22 The diagram shown is an example schematic of a four-sub-pixel design based on the present invention.

[0158] Specifically, each pixel region includes four sub-pixel regions, corresponding to four photosensitive elements PD0, PD1, PD2, and PD3. The transmission transistors TX0, TX1, TX2, and TX3 corresponding to each sub-pixel region are arranged at an angle at the corner of the corresponding photosensitive element, for example, at 45°. The transmission transistors corresponding to the four sub-pixel regions of a pixel region are arranged facing each other to form the opening, and each sub-pixel region of each pixel region shares the same pixel circuit.

[0159] As an example, the pixel circuit further includes an RST and a row selection transistor RS. The row selection transistor is located between adjacent sub-pixel areas in the same row and is arranged in the same direction as the source follower transistor. For example, RS is located between PD0 and PD1 and is arranged in the y-direction with the source follower transistor SF. The reset transistor is located between adjacent sub-pixel areas in the same column and is arranged in another direction with the source follower transistor. For example, RST is located between PD0 and PD3 of adjacent pixel areas and is arranged in the x-direction with the source follower transistor SF.

[0160] As an example, the pixel circuit also includes a gain control transistor DCG, each pixel region includes two floating diffusion points, and two adjacent sub-pixel regions in the same column share the corresponding floating diffusion points. The gain control transistor and the source follower transistor are distributed on both sides of the floating diffusion points, such as DCG being located between PD1 and PD2, and arranged along the x-direction with the source follower transistor SF.

[0161] like Figure 22 As shown, the pixel unit further includes a plurality of microlenses 202, each microlens corresponding one-to-one with a pixel region. In this example, each microlens corresponds to four sub-pixel regions of a pixel region.

[0162] In addition, such as Figure 23 The diagram shown is a schematic of the pixel circuit connection based on this embodiment. Of course, other feasible designs are also possible.

[0163] Example 7:

[0164] The present invention also provides an image sensor, the image sensor comprising a pixel array, the pixel array comprising a plurality of phase-focusing pixel structures arranged in rows and columns as described in any of the above schemes, the image sensor may be a CMOS image sensor, the CMOS image sensor may be a front-illuminated (FSI) image sensor or a back-illuminated (BSI) image sensor, and in this embodiment, a back-illuminated image sensor is preferred.

[0165] The present invention also provides an electronic device comprising an image sensor as described in any of the above embodiments. The electronic device may be a security camera, an automotive electronic camera, a mobile phone camera, a drone, a machine vision system, or an existing camera, and is not limited to the aforementioned devices.

[0166] In summary, the phase-detection pixel structure, image sensor, electronic device, and fabrication method of this invention, by introducing an ion-doped isolation structure between the sub-pixel regions that achieve phase-detection, can improve the phase-detection speed and focusing effect. This invention can also achieve phase-detection pixel separation based on an ion-doped isolation region and a back-side deep trench isolation region. By designing different combinations of the ion-doped isolation region and the back-side deep trench isolation region, designs with different performance focuses can be selected according to actual needs, thereby improving the overall performance of the pixel unit. The design of this invention is easy to implement, compatible with existing semiconductor fabrication processes, and requires no additional process development. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0167] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A phase-detection autofocus pixel structure, characterized in that, The pixel structure includes: a substrate comprising a plurality of pixel regions; a first isolation region located on the periphery of the pixel regions to isolate adjacent pixel regions; and a second isolation region located within the pixel regions and extending into the substrate; wherein the second isolation region includes an ion-doped isolation region, and the first isolation region and the second isolation region divide the pixel regions into four sub-pixel regions to achieve phase focusing based on the sub-pixel regions; The second isolation region further includes a back deep trench isolation region, wherein the back deep trench isolation region, the ion-doped isolation region, and the first isolation region together divide the pixel region into four sub-pixel regions; The ion-doped isolation region extends from the front side of the substrate into the substrate and penetrates the substrate. The back-side deep trench isolation region extends from the back side of the substrate into the substrate. The second isolation region includes a central portion, and the ion-doped isolation region serves as the central portion, distributed in a cross shape at the center of four sub-pixel regions. The ion-doped isolation region has at least two doped isolation region ends, and the deep trench isolation region has at least two deep trench isolation region ends corresponding to the doped isolation region ends. There is a gap between the at least two doped isolation region ends and the first isolation region. One end of the back-side deep trench isolation region contacts the first isolation region, and the other end overlaps with the corresponding doped isolation region end to form the central portion composed of the ion-doped isolation region. Based on the ion-doped isolation region, the interconnection of electrical signals between adjacent photoelectric conversion regions is realized, thereby improving the quantum efficiency during image acquisition.

2. The phase-detection focusing pixel structure according to claim 1, characterized in that, Each of the doped isolation regions has a spacing between its end and the first isolation region, and the spacing between the end of each doped isolation region and the first isolation region may be the same or different; and / or, along the arrangement direction, the size of the back deep trench isolation portion is between 1 / 3 and 2 / 3 of the size of the ion-doped isolation region; and / or, the size of the area where the back deep trench isolation portion overlaps with the corresponding end of the doped isolation region is between 0.3 and 0.5 μm.

3. The phase-detection focusing pixel structure according to claim 1 or 2, characterized in that, The first isolation region includes a peripheral ion-doped region and a peripheral deep trench region, and the peripheral deep trench region is located in the peripheral ion-doped region.

4. An image sensor, characterized in that, The image sensor includes the phase-detection pixel structure as described in any one of claims 1-3.

5. An electronic device, characterized in that, Including the image sensor as described in claim 4.

6. A method for fabricating a phase-detection focusing pixel structure, characterized in that, The preparation method includes the following steps: providing a substrate; A first isolation region and a second isolation region are prepared in the substrate. The first isolation region is located outside the pixel region in the substrate to isolate adjacent pixel regions. The second isolation region is located inside the pixel region and extends into the substrate. The second isolation region includes an ion-doped isolation region. The first isolation region and the second isolation region divide the pixel region into four sub-pixel regions to achieve phase focusing based on the sub-pixel regions. The preparation of the second isolation region further includes the step of preparing a back deep trench isolation region in the substrate, wherein the back deep trench isolation region corresponds to the ion-doped isolation region, and the back deep trench isolation region, the ion-doped isolation region, and the first isolation region together divide the pixel region into four sub-pixel regions; The ion-doped isolation region extends from the front side of the substrate into the substrate and penetrates the substrate. The back-side deep trench isolation region extends from the back side of the substrate into the substrate. The second isolation region includes a central portion, and the ion-doped isolation region serves as the central portion, distributed in a cross shape at the center of four sub-pixel regions. The ion-doped isolation region has at least two doped isolation region ends, and the deep trench isolation region has at least two deep trench isolation region ends corresponding to the doped isolation region ends. There is a gap between the at least two doped isolation region ends and the first isolation region. One end of the back-side deep trench isolation region contacts the first isolation region, and the other end overlaps with the corresponding doped isolation region end to form the central portion composed of the ion-doped isolation region. Based on the ion-doped isolation region, the interconnection of electrical signals between adjacent photoelectric conversion regions is realized, thereby improving the quantum efficiency during image acquisition.

7. The method for fabricating the phase-focusing pixel structure according to claim 6, characterized in that, The fabrication of the ion-doped isolation region and the back trench isolation region includes: forming the ion-doped isolation region from a first surface of the substrate; and fabricating the back trench isolation region from a second surface of the substrate, wherein the second surface is opposite to the first surface.

8. The method for fabricating the phase-focusing pixel structure according to claim 6 or 7, characterized in that, The first isolation region includes a peripheral ion-doped region and a peripheral deep trench region. The fabrication steps of the first isolation region and the second isolation region include: simultaneously fabricating the peripheral ion-doped region and the ion-doped isolation region in the substrate using the same mask; or, fabricating the peripheral ion-doped region using a first mask and fabricating the ion-doped isolation region using a second mask; and / or, fabricating the peripheral deep trench region and the back deep trench isolation region using the same process.

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