Hemt semiconductor device

Abstract

The application relates to a HEMT semiconductor device, which comprises a semiconductor substrate, a channel layer and a barrier layer which are sequentially stacked; a source pad layer is arranged above a first functional area; a plurality of source finger metal field plates are arranged on a second functional area, and the plurality of source finger metal field plates are connected with the source pad layer; a drain pad layer is arranged above a third functional area; a plurality of drain finger metal field plates are arranged on the second functional area, and the plurality of drain finger metal field plates are connected with the drain pad layer; at least one integrated circuit is arranged in the channel layer and the barrier layer and located in the first functional area and / or the third functional area; and an isolation layer is arranged in the channel layer and the barrier layer. Since the integrated circuit does not need to be directly connected with the pad layer, the stress influence of the pad layer on the integrated circuit is extremely small, the integrated circuit can be directly arranged below the pad layer, the internal space of the finger-type HEMT semiconductor device is fully utilized, and the structure of the finger-type HEMT semiconductor device is more compact.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a HEMT semiconductor device. Background Art

[0002] Currently, traditional HEMT (High Electron Mobility Transistor) devices typically use an interdigitated layout, where the PAD metal layer (pad layer) is placed so that it does not overlap with the underlying logic circuits or the electrode metal of the power transistor, preventing the stress generated by the PAD metal from being applied to the circuits directly connected to the PAD metal.

[0003] However, this also means that traditional HEMT devices require a larger chip area to place PAD metal and other circuits separately. The structure of HEMT devices is relatively dispersed and the chip space is not fully utilized. Summary of the Invention

[0004] The purpose of the present application is to provide a HEMT semiconductor device, aiming to solve the problems of traditional HEMT devices with dispersed structures and insufficient utilization of chip space.

[0005] A first aspect of an embodiment of the present application provides a HEMT semiconductor device, comprising: a semiconductor substrate, a channel layer, and a barrier layer stacked in sequence; the barrier layer is divided into a first functional region, a second functional region, and a third functional region, wherein the first functional region, the second functional region, and the third functional region do not overlap with each other; a source pad layer is provided above the first functional region; a plurality of source interdigitated metal field plates are provided on the second functional region, and the plurality of source interdigitated metal field plates are connected to the source pad layer; a drain pad layer is provided above the third functional region; a plurality of drain interdigitated metal field plates are provided on the second functional region; On the functional area, multiple drain interdigitated metal field plates are connected to the drain pad layer, wherein multiple drain interdigitated metal field plates are arranged crosswise with the source interdigitated metal field plates; at least one integrated circuit is arranged in the channel layer and the barrier layer, and is located in the first functional area and / or the third functional area; an isolation layer is arranged in the channel layer and the barrier layer, and is used to isolate the two-dimensional electron gas channel in the channel layer between the integrated circuit and the source interdigitated metal field plate and / or isolate the two-dimensional electron gas channel in the channel layer between the integrated circuit and the drain interdigitated metal field plate.

[0006] In one embodiment, the integrated circuit includes a plurality of diodes, and the plurality of diodes are connected in series or in parallel.

[0007] In one embodiment, a plurality of diodes in the same functional area are sequentially connected in series via the two-dimensional electron gas in the corresponding functional area.

[0008] In one embodiment, the isolation layer is also used to isolate the channel layer and the barrier layer in the first functional area and / or the third functional area into multiple sub-channel layers and multiple sub-barrier layers. One sub-channel layer and the corresponding sub-barrier layer are used to construct one diode, and the multiple diodes in the same functional area are connected through leads or metal layers.

[0009] In one embodiment, the anode metal layer and the cathode metal layer of the diode are located on the barrier layer, and the anode metal layer and the cathode metal layer are connected via the corresponding two-dimensional electron gas to form the diode.

[0010] In one embodiment, at least one of the anode metal layers is connected to the corresponding source interdigitated metal field plate, and at least one of the cathode metal layers is connected to the corresponding drain interdigitated metal field plate.

[0011] In one embodiment, the integrated circuit includes a plurality of memories.

[0012] In one embodiment, it further includes: a gate pad layer, arranged above the third functional area or the first functional area; a plurality of gate interdigitated metal field plates, respectively arranged on the barrier layer between the corresponding drain interdigitated metal field plates and the source interdigitated metal field plates, and all connected to the gate pad layer.

[0013] In one embodiment, a plurality of connection metal layers are further included, and the drain interdigitated metal field plate and the drain pad layer, as well as the source interdigitated metal field plate and the source pad layer are connected via the plurality of connection metal layers.

[0014] In one embodiment, the isolation layer extends from the upper surface of the barrier layer to the semiconductor substrate, and the isolation layer is disposed around the integrated circuit; the isolation layer is silicon oxide or silicon nitride.

[0015] Compared with the prior art, the embodiments of the present application have the following advantages: since the integrated circuit does not need to be directly connected to the pad layer, the stress of the pad layer on the integrated circuit is minimally affected, and the integrated circuit can be directly disposed below the pad layer, thereby fully utilizing the internal space of the interdigitated HEMT semiconductor device and making the structure of the interdigitated HEMT semiconductor device more compact.

[0016] At the same time, when the integrated circuit includes multiple diodes, the anode metal layer of the diode can be connected to the corresponding source interdigitated metal field plate, and the cathode metal layer of the diode can be connected to the corresponding drain interdigitated metal field plate, so that the diode is connected in anti-parallel with the source interdigitated metal field plate and the drain interdigitated metal field plate. When a high voltage is applied to the HEMT semiconductor device, the diode can be broken down first, thereby limiting the voltage applied to the HEMT semiconductor device and improving the high-voltage resistance capability of the HEMT semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A top view of the structure of a HEMT semiconductor device provided in one embodiment of the present application;

[0018] Figure 2 For the Figure 1 A cross-sectional view taken along line AA′;

[0019] Figure 3 For the Figure 1 Cross-sectional view taken along line BB′;

[0020] Figure 4 A top view of the functional areas of the barrier layer provided in one embodiment of the present application;

[0021] Figure 5 A first top view of an interdigitated metal field plate and an integrated circuit provided in one embodiment of the present application;

[0022] Figure 6 A side cross-sectional view of a single diode provided in one embodiment of the present application;

[0023] Figure 7 A second top view of the interdigitated metal field plate and the integrated circuit provided in one embodiment of the present application;

[0024] Figure 8 A third top view of the interdigitated metal field plate and the integrated circuit provided in one embodiment of the present application;

[0025] Figure 9 A fourth top view of an interdigitated metal field plate and an integrated circuit provided in one embodiment of the present application;

[0026] Figure 10 A side cross-sectional view of a single sub-power switch provided in one embodiment of the present application;

[0027] Figure 11 Another side cross-sectional view of a single sub-power switch provided in an embodiment of the present application.

[0028] Description of the above drawings: 110, semiconductor substrate; 120, channel layer; 130, barrier layer; 131, first functional region; 132, second functional region; 133, third functional region; 140, P-type cap layer; 150, isolation layer; 160, passivation layer; 210, source pad layer; 220, drain pad layer; 230, gate pad layer; 310, source interdigitated metal field plate; 320, drain interdigitated metal field plate; 330, gate interdigitated metal field plate; 410, connecting metal layer; 420, conductive via; 430, conductive metal column; 500, integrated circuit; 510, diode; 511, anode metal layer; 512, cathode metal layer; 513, series metal layer. DETAILED DESCRIPTION

[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0030] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0031] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0033] Figure 1 A top view of the structure of a HEMT semiconductor device provided in one embodiment of the present application is shown. For ease of illustration, only the portion related to this embodiment is shown, as detailed below:

[0034] like Figure 1 、 Figure 2 and Figure 3 As shown, a HEMT semiconductor device includes a semiconductor substrate 110, a channel layer 120 and a barrier layer 130 stacked in sequence, a source pad layer 210, a plurality of source interdigitated metal field plates 310, a drain pad layer 220, a plurality of drain interdigitated metal field plates 320, at least one integrated circuit 500 and an isolation layer 150. Figure 4 As shown, the barrier layer 130 is divided into a first functional region 131, a second functional region 132, and a third functional region 133. The first functional region 131, the second functional region 132, and the third functional region 133 do not overlap with each other. The semiconductor substrate 110 may be made of SiC (silicon carbide) or SiN (silicon nitride), the channel layer 120 may be made of GaN (gallium nitride), and the barrier layer 130 may be made of AlGaN (aluminum gallium nitride).

[0035] It should be noted that a two-dimensional electron gas (2DEG) is formed between the channel layer 120 and the barrier layer 130 , and the two-dimensional electron gas can be used as a power transmission channel to transmit electrical energy.

[0036] The source pad layer 210 is disposed above the first functional region 131 of the barrier layer 130. A plurality of source interdigitated metal field plates 310 are disposed on the second functional region 132 of the barrier layer 130 and are connected to the source pad layer 210. The drain pad layer 220 is disposed above the third functional region 133 of the barrier layer 130. A plurality of drain interdigitated metal field plates 320 are disposed on the second functional region 132 of the barrier layer 130 and are connected to the drain pad layer 220. The plurality of drain interdigitated metal field plates 320 are interdigitated with the source interdigitated metal field plates 310. A source interdigitated metal field plate 310 and a drain interdigitated metal field plate 320 , as well as the semiconductor substrate 110 , the channel layer 120 and the barrier layer 130 , can be used to construct a sub-power switch. Multiple sub-power switches are connected in series to construct an interdigitated HEMT device.

[0037] The integrated circuit 500 is disposed within the channel layer 120 and the barrier layer 130 and is located within the first functional region 131 and / or the third functional region 133. The isolation layer 150 is disposed within the channel layer 120 and the barrier layer 130 to isolate the integrated circuit 500 from the two-dimensional electron gas channel in the channel layer 120 between the source interdigitated metal field plate 310 and the drain interdigitated metal field plate 320.

[0038] like Figure 1 、 Figure 2 、 Figure 3 and Figure 5As shown, in an example, the integrated circuit 500 is disposed in the first functional region 131. The isolation layer 150 extends from the upper surface of the barrier layer 130 to the semiconductor substrate 110 and surrounds the integrated circuit 500. The isolation layer 150 can be silicon oxide or silicon nitride.

[0039] It should be noted that since the source pad layer 210 and the drain pad layer 220 are directly connected to the source interdigital metal field plate 310 and the drain interdigital metal field plate 320 respectively, if the source pad layer 210 and the drain pad layer 220 are directly stacked above the metal field plate, the stress generated by the source pad layer 210 and the drain pad layer 220 will be directly applied to the metal field plate, resulting in damage to the metal field plate. The integrated circuit 500 does not need to be directly connected to the pad layer, so the stress of the pad layer on the integrated circuit 500 is minimal, and the integrated circuit 500 can be directly disposed below the pad layer, thereby fully utilizing the internal space of the interdigital HEMT device and making the structure of the interdigital HEMT semiconductor device more compact. The part of the integrated circuit 500 that needs to be disposed outside the interdigital HEMT semiconductor device can be integrated into the interdigital HEMT device, thereby reducing the overall circuit area.

[0040] In this embodiment, the integrated circuit 500 includes a plurality of diodes 510 connected in series or in parallel. The connection mode of the diodes 510 can be configured according to requirements, and this embodiment does not limit the specific connection relationship of the diodes 510. Figure 5 As shown, in an example, the plurality of diodes 510 are connected in series, and the anode of the diode series circuit is connected to the corresponding source interdigital metal field plate 310, and the cathode of the diode series circuit is connected to the corresponding drain interdigital metal field plate 320. When a high voltage is applied to the HEMT semiconductor device of this embodiment, the diode series circuit can be broken down first, thereby limiting the voltage applied to the HEMT semiconductor device and avoiding damage to the HEMT semiconductor device by high voltage. Compared with the traditional interdigital HEMT, the high voltage resistance of this embodiment is stronger.

[0041] The diode 510 can be a Schottky diode constructed based on the channel layer 120 and the barrier layer 130 in the first functional region 131 and / or the third functional region 133, as shown in Figure 6As shown, the anode metal layer 511 and the cathode metal layer 512 of the diode 510 are located on the barrier layer 130. The anode metal layer 511 and the cathode metal layer 512 are connected via the two-dimensional electron gas formed by the barrier layer 130 and the channel layer 120 to form the diode 510. Specifically, the anode metal layer 511 may be a Schottky metal layer, and the cathode metal layer 512 may be an ohmic metal layer. The Schottky metal layer and the barrier layer 130 form a metal-semiconductor junction, which is then connected to the ohmic metal layer via the two-dimensional electron gas, thereby forming a Schottky diode.

[0042] like Figure 5 As shown, in one example, several diodes 510 are formed in the first functional region 131. Since the diodes 510 do not need to be directly connected to the source pad layer 210, even if the source pad layer 210 overlaps with the diodes 510, the stress generated by the source pad layer 210 is unlikely to be applied to the diodes 510. Therefore, the diodes 510 can be disposed in the first functional region 131 below the source pad layer 210.

[0043] In this embodiment, multiple diodes 510 in the same functional area can be connected in series in sequence through the two-dimensional electron gas. Figure 5 As shown, in one example, there are three diodes 510 in the first functional region 131, and each diode 510 is connected in series via a two-dimensional electron gas. In the diode series circuit formed by the three diodes 510 in the first functional region 131, the anode metal layer 511 of the first diode 510 serves as the anode of the series diode circuit. The cathode metal layer 512 of the first diode 510 is connected to the anode metal layer 511 of the adjacent second diode 510 via the two-dimensional electron gas. The cathode metal layer 512 of the second diode 510 is connected to the anode metal layer 511 of the last diode 510 via the two-dimensional electron gas. The cathode metal layer 512 of the last diode 510 serves as the cathode of the series diode circuit.

[0044] like Figure 7 As shown, in one example, three diodes 510 are provided on each of the first functional region 131 and the third functional region 133 of the barrier layer 130 and are sequentially connected in series through the two-dimensional electron gas.

[0045] In another embodiment, the isolation layer 150 is further used to isolate the channel layer 120 and the barrier layer 130 in the first functional area 131 and / or the third functional area 133 into multiple sub-channel layers and multiple sub-barrier layers. One sub-channel layer and the corresponding sub-barrier layer are used to construct a diode 510. Multiple diodes 510 in the same functional area are connected through leads or series metal layers 513. Figure 8As shown, in one example, the diodes 510 in the first functional area 131 and the third functional area 133 are independent of each other, and the diodes 510 in the same functional area are sequentially connected in series via the series metal layer 513 .

[0046] In this embodiment, at least one anode metal layer 511 is connected to the corresponding source interdigitated metal field plate 310 , and at least one cathode metal layer 512 is connected to the corresponding drain interdigitated metal field plate 320 .

[0047] like Figure 8 As shown, in one example, taking the three diodes 510 in the first functional area 131 as an example, in a diode series circuit composed of multiple diodes 510 connected in series, the anode metal layer 511 of the first diode 510 is the anode of the diode series circuit, which is used to be directly connected to the corresponding source interdigitated metal field plate 310, the cathode metal layer 512 of the first diode 510 is connected to the anode metal layer 511 of the adjacent second diode 510, the cathode metal layer 512 of the second diode 510 is connected to the anode metal layer 511 of the last diode 510, and the cathode metal layer 512 of the last diode 510 is the cathode of the diode series circuit, which is used to be directly connected to the corresponding drain interdigitated metal field plate 320.

[0048] like Figure 9 As shown, in one example, taking the three diodes 510 in the first functional area 131 as an example, in a diode series circuit composed of multiple diodes 510 connected in series, each diode 510 corresponds one-to-one to each sub-power switch, and the anode metal layer 511 of each diode 510 is connected to the source interdigitated metal field plate 310 of the corresponding sub-power switch, and the cathode metal layer 512 of each diode 510 is connected to the drain interdigitated metal field plate 320 of the corresponding sub-power switch.

[0049] In another embodiment, the integrated circuit 500 includes multiple memories. Specifically, the memories may be static random-access memories (SRAMs), thereby fully utilizing the internal space of the HEMT semiconductor device and expanding the functionality of the HEMT semiconductor device.

[0050] In this embodiment, the HEMT semiconductor device further includes a gate pad layer 230 and a plurality of gate interdigitated metal field plates 330 .

[0051] like Figure 1 、 Figure 9 、 Figure 10As shown, the gate pad layer 230 is disposed above the third functional region 133 or the first functional region 131. A plurality of gate interdigitated metal field plates 330 are respectively disposed on the barrier layer 130 between the corresponding drain interdigitated metal field plates 320 and the source interdigitated metal field plates 310, and are all connected to the gate pad layer 230. The distance between the gate interdigitated metal field plates 330 and the corresponding source interdigitated metal field plates 310 is smaller than the distance between the gate interdigitated metal field plates 330 and the corresponding drain interdigitated metal field plates 320.

[0052] By changing the voltage applied to the gate interdigitated metal field plate 330 , the on / off of the two-dimensional electron gas between the corresponding drain interdigitated metal field plate 320 and the corresponding source interdigitated metal field plate 310 can be controlled.

[0053] like Figure 10 As shown, specifically, a P-type cap layer 140 is further provided between the gate interdigitated metal field plate 330 and the barrier layer 130. In one example, the material of the P-type cap layer 140 can be P-GaN (P-type gallium nitride). It should be noted that when the voltage applied to the gate interdigitated metal field plate 330 is greater than the corresponding turn-on voltage, the two-dimensional electron gas between the corresponding drain interdigitated metal field plate 320 and the corresponding source interdigitated metal field plate 310 is turned on. When the voltage applied to the gate interdigitated metal field plate 330 is less than the corresponding turn-on voltage, the two-dimensional electron gas between the corresponding drain interdigitated metal field plate 320 and the corresponding source interdigitated metal field plate 310 is cut off.

[0054] like Figure 11 As shown, in another embodiment, multiple connecting metal layers 410 are further included, and the drain interdigitated metal field plate 320 and the drain pad layer 220 as well as the source interdigitated metal field plate 310 and the source pad layer 210 are connected through multiple connecting metal layers 410 to construct logic circuits through the connecting metal layers 410.

[0055] The upper and lower adjacent connection metal layers 410 are connected via conductive vias 420 , and the connection metal layers 410 are connected to the corresponding source interdigitated metal field plates 310 or drain interdigitated metal field plates via conductive metal pillars 430 .

[0056] It should be noted that the number and structure of the connection metal layers 410 can be configured according to actual needs. At the same time, the connection metal layers 410 can also be connected through logic circuits to control each sub-power switch through a certain control logic.

[0057] like Figure 11As shown, in one example, two connection metal layers 410 are provided between each source interdigitated metal field plate 310 and the source pad layer 210 and between each drain interdigitated metal field plate 320 and the drain pad layer 220 , one of which is used to connect to the corresponding pad layer.

[0058] Meanwhile, in this embodiment, the barrier layer 130 is further filled with an isolation fixing material for fixing the source pad layer 210 , the source interdigitated metal field plate 310 , the drain pad layer 220 and the drain interdigitated metal field plate 320 .

[0059] like Figure 11 As shown, in another embodiment, a passivation layer 160 is further formed on the barrier layer 130 to protect the barrier layer 130 .

[0060] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0061] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0062] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A HEMT semiconductor device, characterized in that: include: A semiconductor substrate, a channel layer, and a barrier layer stacked in sequence; The barrier layer is divided into a first functional area, a second functional area and a third functional area, and the first functional area, the second functional area and the third functional area do not overlap with each other; a source electrode pad layer, disposed above the first functional area; A plurality of source interdigitated metal field plates are provided on the second functional area, and the plurality of source interdigitated metal field plates are connected to the source pad layer; a drain pad layer, disposed above the third functional area; a plurality of drain interdigitated metal field plates, each disposed on the second functional region, each of the plurality of drain interdigitated metal field plates being connected to the drain pad layer, wherein the plurality of drain interdigitated metal field plates are disposed crosswise with the source interdigitated metal field plate; at least one integrated circuit, disposed in the channel layer and the barrier layer, and located in the first functional region and / or the third functional region; an isolation layer, disposed within the channel layer and the barrier layer, for isolating the two-dimensional electron gas channel in the channel layer between the integrated circuit and the source interdigitated metal field plate and / or isolating the two-dimensional electron gas channel in the channel layer between the integrated circuit and the drain interdigitated metal field plate.

2. The HEMT semiconductor device according to claim 1, wherein The integrated circuit includes a plurality of diodes, and the plurality of diodes are connected in series or in parallel.

3. The HEMT semiconductor device according to claim 2, wherein: The plurality of diodes in the same functional area are sequentially connected in series via the two-dimensional electron gas in the corresponding functional area.

4. The HEMT semiconductor device according to claim 2, wherein The isolation layer is also used to isolate the channel layer and the barrier layer in the first functional area and / or the third functional area into multiple sub-channel layers and multiple sub-barrier layers. One sub-channel layer and the corresponding sub-barrier layer are used to construct one diode, and the multiple diodes in the same functional area are connected through leads or metal layers.

5. The HEMT semiconductor device according to claim 3 or 4, wherein: The anode metal layer and the cathode metal layer of the diode are located on the barrier layer, and the anode metal layer and the cathode metal layer are connected via the corresponding two-dimensional electron gas to form the diode.

6. The HEMT semiconductor device according to claim 5, wherein: At least one of the anode metal layers is connected to the corresponding source interdigitated metal field plate, and at least one of the cathode metal layers is connected to the corresponding drain interdigitated metal field plate.

7. The HEMT semiconductor device according to any one of claims 1 to 4, wherein: The integrated circuit includes a plurality of memories.

8. The HEMT semiconductor device according to any one of claims 1 to 4, wherein: Also includes: a gate pad layer, disposed above the third functional area or the first functional area; A plurality of gate interdigitated metal field plates are respectively arranged on the barrier layer between the corresponding drain interdigitated metal field plates and the source interdigitated metal field plates, and are all connected to the gate pad layer.

9. The HEMT semiconductor device according to any one of claims 1 to 4, wherein: It also includes a plurality of connection metal layers, and the drain interdigitated metal field plate and the drain pad layer, as well as the source interdigitated metal field plate and the source pad layer are connected via the plurality of connection metal layers.

10. The HEMT semiconductor device according to any one of claims 1 to 4, wherein: The isolation layer extends from the upper surface of the barrier layer to the semiconductor substrate, and the isolation layer is arranged around the integrated circuit; the isolation layer is silicon oxide or silicon nitride.

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