A glitch-free clock signal conversion system
By adding a signal conversion system between the digital module circuit and the oscillator, the problem of glitches generated when the clock signal is modified is solved, thus improving the reliability and stability of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN AIXIESHENG TECH CO LTD
- Filing Date
- 2022-10-15
- Publication Date
- 2026-06-30
AI Technical Summary
In existing technologies, clock signal modifications are prone to generating glitches, which can cause abnormal operation of digital module circuits and severely affect chip functionality.
A signal conversion system is added between the digital module circuit and the oscillator. By receiving the clock stop signal output by the digital module circuit, converting and stabilizing the second clock signal before outputting it, the glitches and interference are avoided.
It effectively eliminates glitches caused by clock signal conversion, improving the reliability and stability of the circuit.
Smart Images
Figure CN115580274B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of clock signal conversion technology, specifically to a system for glitch-free clock signal conversion. Background Technology
[0002] With the rapid advancements in integrated circuit design and manufacturing technologies, the number of transistors integrated on a single chip is increasing daily, while chip size and complexity have become unavoidable challenges for designers. Typically, in large-scale digital circuit implementations, taking a System-on-a-Chip (SoC) as an example, different modules operate in different clock domains to minimize dynamic power consumption caused by signal switching while meeting computational performance requirements. Furthermore, some modules may even switch their clock frequencies during operation due to changes in computational load.
[0003] The primary function of an oscillator (OSC) is to generate a clock signal of a specific frequency, which is then supplied to the digital module circuit for operation. For the OSC, the frequency of the clock signal is controlled by the clock frequency signal emitted by the digital module, while the amplitude is determined by the VDD voltage provided by the voltage regulator module. Currently, any modification to the clock signal generated by the OSC, whether it's the VDD voltage or the clock frequency signal, requires a certain settling time. Before this time, the voltage or frequency of the clock signal may change drastically, or even produce glitches, leading to malfunctions in the digital module circuit and, in severe cases, affecting the chip's functionality. Summary of the Invention
[0004] This invention proposes a glitch-free clock signal conversion system, which solves the problem in the prior art that glitches are easily generated when modifying clock signals, leading to abnormal operation of digital module circuits and even affecting the function of the chip.
[0005] The technical solution of the present invention is as follows:
[0006] A system for glitch-free clock signal conversion includes an oscillator and a digital module circuit. The digital module circuit outputs a first clock conversion signal, and the oscillator outputs the first clock signal. The system also includes a signal conversion system.
[0007] The signal conversion system is used to receive the first clock conversion signal and output a second clock conversion signal to the oscillator. The first clock conversion signal includes a first clock frequency conversion signal OSC_TRIM_DTA, and the second clock conversion signal includes a second clock frequency conversion signal OSC_TRIM.
[0008] The signal conversion system is used to receive the first clock signal OSC_CLK and output the second clock signal OSC_CLK_ATD to the digital module circuit.
[0009] The signal conversion system also receives a first clock stop signal OSC_TRIG_DTA output by the digital module circuit, and after receiving the first clock stop signal OSC_TRIG_DTA, the signal conversion system outputs a low-level second clock signal OSC_CLK_ATD within a preset time.
[0010] Furthermore, the signal conversion system includes a first trigger circuit, a second trigger circuit, a delay control circuit, and a clock signal control circuit.
[0011] The input terminal of the first trigger circuit receives the first clock stop signal OSC_TRIG_DTA, the control terminal of the first trigger circuit receives the first clock signal OSC_CLK, the set terminal of the first trigger circuit receives the first set signal RSTN, and the output terminal of the first trigger circuit is used to output the second clock stop signal TRIG.
[0012] The control terminal of the second trigger circuit is connected to the output terminal of the NOT gate U11. The input terminal of the NOT gate U11 receives the first clock signal OSC_CLK. The set terminal of the second trigger circuit receives the second set signal RSTN_DFF. The output terminal of the second trigger circuit is used to output the third clock stop signal TRIG_FB.
[0013] The first input terminal of the delay control circuit receives the second clock stop signal TRIG, the second input terminal of the delay control circuit receives the third clock stop signal TRIG_FB, and the output terminal of the delay control circuit outputs the second set signal RSTN_DFF.
[0014] The first input terminal of the clock signal control circuit receives the third clock stop signal TRIG_FB, the second input terminal of the clock signal control circuit receives the first clock signal OSC_CLK, and the output terminal of the clock signal control circuit is used to output the second clock signal OSC_CLK_ATD.
[0015] Furthermore, the first trigger circuit includes at least one D flip-flop U1. The input terminal of the D flip-flop U1 receives the first clock stop signal OSC_TRIG_DTA, the control terminal of the D flip-flop U1 receives the first clock signal OSC_CLK, the set terminal of the D flip-flop U1 receives the first set signal RSTN, and the output terminal of the D flip-flop U1 is connected to the input terminal of another D flip-flop U1 or outputs a second clock stop signal TRIG.
[0016] Furthermore, the second trigger circuit includes at least one D flip-flop U17, the input terminal of the D flip-flop U17 is connected to the second output terminal of the D flip-flop U17, the control terminal of the D flip-flop U17 is connected to the output terminal of the NOT gate U11, the set terminal of the D flip-flop U17 receives the second set signal RSTN_DFF, and the first output terminal of the D flip-flop U17 is connected to the control terminal of another D flip-flop U17 or outputs a third clock stop signal TRIG_FB.
[0017] Furthermore, the delay control circuit includes NOR gate U7, NOT gate U8, NAND gate U9, and NOT gate U10. The first input terminal of NOR gate U7 receives a second clock stop signal TRIG, and the second input terminal of NOR gate U7 receives a third clock stop signal TRIG_FB. The output terminal of NOR gate U7 is connected to the first input terminal of NAND gate U9 through NOT gate U8. The second input terminal of NAND gate U9 receives a first set signal RSTN, and the output terminal of NAND gate U9 outputs a second set signal RSTN_DFF through NOT gate U10.
[0018] Furthermore, the clock signal control circuit includes a NAND gate U12 and a NOT gate U13. The first input terminal of the NAND gate U12 receives the third clock stop signal TRIG_FB, the second input terminal of the NAND gate U12 receives the first clock signal OSC_CLK, and the output terminal of the NAND gate U12 outputs the second clock signal OSC_CLK_ATD through the NOT gate U13.
[0019] Furthermore, the clock signal control circuit also includes a D flip-flop U5 and a NOR gate U6. The input of the D flip-flop U5 receives a third clock stop signal TRIG_FB. The control terminal of the D flip-flop U5 is connected to the output of the NOT gate U11. The set terminal of the D flip-flop U5 receives a first set signal RSTN. The output of the D flip-flop U5 is connected to the first input of the NOR gate U6. The second input of the NOR gate U6 receives the third clock stop signal TRIG_FB. The output of the NOR gate U6 is connected to the first input of the NAND gate U12.
[0020] Furthermore, the signal conversion system also includes a signal conversion processing circuit, which includes a D flip-flop U19 and a NOT gate U18. The input of the D flip-flop U19 receives a first clock conversion signal, and the output of the D flip-flop U19 outputs a second clock conversion signal. The control terminal of the D flip-flop U19 is connected to the output of the NOT gate U18. The input of the NOT gate U18 receives a second clock stop signal TRIG, and the set terminal of the D flip-flop U19 receives a first set signal RSTN.
[0021] Furthermore, it also includes a linear regulator for providing VDD power to the oscillator, and the signal conversion system is also used to output a second clock conversion signal to the linear regulator. The first clock conversion signal includes a first clock voltage conversion signal VDD_TRIM_DTA, and the second clock conversion signal includes a second clock voltage conversion signal VDD_TRIM.
[0022] Furthermore, it also includes a bandgap reference circuit, which is used to provide a reference power supply to the linear regulator. The signal conversion system is also used to output a second clock conversion signal to the bandgap reference circuit. The first clock conversion signal includes a first clock reference conversion signal VBG_TRIM_DTA, and the second clock conversion signal includes a second clock reference conversion signal VBG_TRIM.
[0023] The working principle and beneficial effects of this invention are as follows:
[0024] In this invention, an added signal conversion system is used not only for signal transmission between the digital module circuit and the oscillator, but also, when the digital module circuit needs to transform the clock signal output by the oscillator, receives the first clock stop signal OSC_TRIG_DTA output by the digital module circuit, converts this signal to stop the second clock signal OSC_CLK_ATD, and outputs it to the digital module circuit only after the second clock signal OSC_CLK_ATD has stabilized. This avoids glitches caused by clock signal transformation from interfering with the digital module circuit, thus improving the reliability of the entire circuit. Attached Figure Description
[0025] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0026] Figure 1 This is a schematic diagram of the principle of the present invention;
[0027] Figure 2 This is a circuit diagram of the first trigger circuit in this invention;
[0028] Figure 3 This is a circuit diagram of the second trigger circuit in this invention;
[0029] Figure 4 This is a circuit diagram of the delay control circuit in this invention;
[0030] Figure 5 This is a circuit diagram of the clock signal control circuit in this invention;
[0031] Figure 6 This is a circuit diagram of the signal processing circuit in this invention;
[0032] Figure 7 This is a signal timing diagram of the signal conversion system in this invention;
[0033] Figure 8 This is a circuit diagram of the linear regulator in this invention. Detailed Implementation
[0034] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0035] like Figure 1 As shown, this invention proposes a glitch-free clock signal transformation system, which is used to eliminate glitches when digital module circuits transform the frequency or voltage amplitude of clock signals.
[0036] This embodiment includes an oscillator (OSC), a digital module circuit (Digital), and a signal conversion system (DFF_OSC), wherein...
[0037] The digital module circuit is used to output the first clock conversion signal, and the oscillator is used to output the first clock signal.
[0038] The signal conversion system is used to receive a first clock conversion signal and output a second clock conversion signal to the oscillator. The first clock conversion signal includes a first clock frequency conversion signal OSC_TRIM_DTA, and the second clock conversion signal includes a second clock frequency conversion signal OSC_TRIM.
[0039] The signal conversion system receives the first clock signal OSC_CLK and outputs the second clock signal OSC_CLK_ATD to the digital module circuit.
[0040] The signal conversion system also receives the first clock stop signal OSC_TRIG_DTA output by the digital module circuit, and after the signal conversion system receives the first clock stop signal OSC_TRIG_DTA, the signal conversion system outputs a low-level second clock signal OSC_CLK_ATD within a preset time.
[0041] A signal conversion system, DFF_OSC, was added between the Digital module circuit (Digital) and the bandgap reference circuit (BGR), the low-dropout linear regulator (LDO), and the oscillator (OSC). Previously, the signals from the Digital module circuit and the latter three circuits were first processed by the DFF_OSC before being sent to the corresponding circuits. The workflow of the above technical solution is as follows:
[0042] The Digital module circuit modifies the voltage of VBG and VDD or the frequency of the oscillator OSC clock signal by changing one or more of the VBG_TRIM_DTA, VDD_TRIM_DTA or OSC_TRIM_DTA signals, and at the same time sends the OSC_TRIG_DTA signal as a trigger enable for voltage or frequency modification.
[0043] The DFF_OSC circuit receives the modified VBG_TRIM_DTA, VDD_TRIM_DTA, OSC_TRIM_DTA and OSC_TRIG_DTA signals sent by the Digital module circuit, latches them as VBG_TRIM, VDD_TRIM and OSC_TRIM signals respectively and sends them to the corresponding circuits, while stopping the transmission of the OSC_CLK_ATD signal.
[0044] The bandgap reference circuit (BGR), low-dropout linear regulator (LDO), or oscillator (OSC) circuit receives the new VBG_TRIM, VDD_TRIM, or OSC_TRIM signals respectively, and begins to change the output voltage and clock frequency. DFF_OSC starts counting the clock signal and releases OSC_CLK_ATD to the digital module circuit (Digital) after a certain number of clock cycles.
[0045] The digital module circuit receives a clock signal and restarts operation until the next time the voltage or frequency needs to be modified.
[0046] In this embodiment, an added signal conversion system is used not only for signal transmission between the digital module circuit and the oscillator, but also, when the digital module circuit needs to transform the clock signal output by the oscillator, receives the first clock stop signal OSC_TRIG_DTA output by the digital module circuit, converts this signal to stop the second clock signal OSC_CLK_ATD, and outputs it to the digital module circuit only after the second clock signal OSC_CLK_ATD has stabilized. This avoids glitches caused by clock signal transformation from interfering with the digital module circuit, improving the reliability of the entire circuit.
[0047] Furthermore, this embodiment also includes a bandgap reference circuit (BGR) and a linear regulator (LDO). The BGR provides a reference voltage to the LDO. The signal conversion system also outputs a second clock conversion signal to the BGR. The first clock conversion signal includes a first clock reference conversion signal VBG_TRIM_DTA, and the second clock conversion signal includes a second clock reference conversion signal VBG_TRIM. The LDO provides VDD power to the oscillator. The signal conversion system also outputs a second clock conversion signal to the LDO. The first clock conversion signal includes a first clock voltage conversion signal VDD_TRIM_DTA, and the second clock conversion signal includes a second clock voltage conversion signal VDD_TRIM.
[0048] In addition to the frequency conversion mentioned above, clock signal conversion also includes indirect conversion via a bandgap reference circuit (BGR) and direct conversion via a linear regulator (LDO).
[0049] The bandgap reference circuit BGR generates a reference voltage VBG, which does not change with temperature and power supply voltage. The voltage amplitude can be controlled by the digital module circuit Digital. By modifying the value of the VBG_TRIM_DTA signal (the bit value is determined by the adjustment amplitude and step of the VBG voltage), the value of VBG can be directly modified.
[0050] The VBG voltage generated by the bandgap reference circuit BGR is mainly supplied to the low dropout linear regulator LDO to generate the VDD voltage, which is mainly used as the power supply voltage for the circuit.
[0051] Common structures of low dropout linear regulator (LDO) circuits include: Figure 8 As shown, the main structure of a low-dropout linear regulator (LDO) consists of an operational amplifier (AMP) and resistors R1 and R2, which act as voltage dividers and provide feedback. The resistance values can be changed via a register. The AMP is typically a two-stage op-amp with a high static gain, resulting in a virtual short at the AMP input, meaning the VBG voltage is equal to VFB. The potential of VDD can be obtained through resistor division (VDD = VBG / R2*(R1+R2)). The digital module circuit (Digital) can modify the value of VDD_TRIM_DTA to change the resistance of R2, thereby altering the magnitude of the VDD voltage.
[0052] The main function of the oscillator OSC is to generate a first clock signal OSC_CLK at a certain frequency, which is provided to the digital module circuit for operation. The frequency of the first clock signal OSC_CLK is controlled by the digital module circuit. By changing the first clock frequency conversion signal OSC_TRIM_DTA, the frequency of the first clock signal OSC_CLK can be tuned.
[0053] further,
[0054] like Figure 7 As shown, the signal conversion system includes a first trigger circuit, a second trigger circuit, a delay control circuit, and a clock signal control circuit.
[0055] The input terminal of the first trigger circuit receives the first clock stop signal OSC_TRIG_DTA, the control terminal of the first trigger circuit receives the first clock signal OSC_CLK, the set terminal of the first trigger circuit receives the first set signal RSTN, and the output terminal of the first trigger circuit is used to output the second clock stop signal TRIG.
[0056] The control terminal of the second trigger circuit is connected to the output terminal of the NOT gate U11. The input terminal of the NOT gate U11 receives the first clock signal OSC_CLK. The set terminal of the second trigger circuit receives the second set signal RSTN_DFF. The output terminal of the second trigger circuit is used to output the third clock stop signal TRIG_FB.
[0057] The first input terminal of the delay control circuit receives the second clock stop signal TRIG, the second input terminal of the delay control circuit receives the third clock stop signal TRIG_FB, and the output terminal of the delay control circuit outputs the second set signal RSTN_DFF.
[0058] The first input terminal of the clock signal control circuit receives the third clock stop signal TRIG_FB, the second input terminal of the clock signal control circuit receives the first clock signal OSC_CLK, and the output terminal of the clock signal control circuit is used to output the second clock signal OSC_CLK_ATD.
[0059] further,
[0060] like Figure 2 As shown, the first trigger circuit includes at least one D flip-flop U1. The input terminal of the D flip-flop U1 receives a first clock stop signal OSC_TRIG_DTA, the control terminal of the D flip-flop U1 receives a first clock signal OSC_CLK, the set terminal of the D flip-flop U1 receives a first set signal RSTN, and the output terminal of the D flip-flop U1 is connected to the input terminal of another D flip-flop U1 or outputs a second clock stop signal TRIG.
[0061] In this embodiment, the first set signal RSTN is power on control (POC), which is released when the VDD power supply is powered on to a certain potential. The signal changes from 0 to 1, and the D flip-flops U19, U20, and U21 change from the reset state to the normal working state.
[0062] In this embodiment, the first trigger circuit receives the first clock signal OSC_CLK, which is the clock signal generated by the oscillator OSC with a duty cycle of 50%. When the digital circuit needs to transform the clock signal, in addition to sending the first clock transformation signal TRIM_DTA, it also sends OSC_TRIG_DTA. This signal generates TRIG after passing through several cycles under the sampling of the clock signal. In this embodiment, four D flip-flops U1 are set, which are labeled as D flip-flops U1, U2, U3, and U4 for ease of description. Four D flip-flops can achieve a delay of four cycles to ensure correct sampling. The specific number of cycles required can be adjusted according to the actual situation.
[0063] TRIG first changes from 0 to 1, and the delay control circuit causes RSTN_DFF to also change from 0 to 1, releasing all the D flip-flops in the second trigger circuit. Since the second trigger circuit receives the first clock signal OSC_CLK through NOT gate U11, it uses falling edge sampling. Therefore, after half a clock cycle, TRIG_FB is pulled high, and the clock signal control circuit pulls the output of OSC_CLK_ATD to 0. At this point, the clock received by the digital module circuit (Digital) pauses at 0, and the circuit stops working.
[0064] further,
[0065] like Figure 3 As shown, the second trigger circuit includes at least one D flip-flop U17. The input terminal of the D flip-flop U17 is connected to the second output terminal of the D flip-flop U17. The control terminal of the D flip-flop U17 is connected to the output terminal of the NOT gate U11. The set terminal of the D flip-flop U17 receives the second set signal RSTN_DFF. The first output terminal of the D flip-flop U17 is connected to the control terminal of another D flip-flop U17 or outputs the third clock stop signal TRIG_FB.
[0066] When the clock received by the Digital module circuit pauses at 0, the D flip-flops in the second trigger circuit begin clock counting. After a certain number of clock cycles, TRIG_FB is pulled low to 0 again. The number of cycles is related to the OSC_CLK frequency and the settling time required for VDD and VBG. The appropriate number of D flip-flops can be selected to adjust the number of cycles according to the actual situation. In this embodiment, four D flip-flops U17 are set, which are labeled as D flip-flops U17, U16, U14, and U15 for ease of description. An 8-cycle delay can be achieved using four D flip-flops.
[0067] further,
[0068] like Figure 4 As shown, the delay control circuit includes NOR gate U7, NOT gate U8, NAND gate U9, and NOT gate U10. The first input of NOR gate U7 receives a second clock stop signal TRIG, and the second input of NOR gate U7 receives a third clock stop signal TRIG_FB. The output of NOR gate U7 is connected to the first input of NAND gate U9 through NOT gate U8. The second input of NAND gate U9 receives a first set signal RSTN, and the output of NAND gate U9 outputs a second set signal RSTN_DFF through NOT gate U10. In this embodiment, NOR gate U7 and NOT gate U8 can be replaced by an OR gate, and NAND gate U9 and NOT gate U10 can be replaced by an AND gate.
[0069] further,
[0070] like Figure 5 As shown, the clock signal control circuit includes NAND gate U12 and NOT gate U13. The first input of NAND gate U12 receives the third clock stop signal TRIG_FB, the second input of NAND gate U12 receives the first clock signal OSC_CLK, and the output of NAND gate U12 outputs the second clock signal OSC_CLK_ATD through NOT gate U13. In this embodiment, NAND gate U12 and NOT gate U13 can be replaced by an AND gate.
[0071] Furthermore, the clock signal control circuit also includes a D flip-flop U5 and an NOR gate U6. The input of the D flip-flop U5 receives the third clock stop signal TRIG_FB. The control terminal of the D flip-flop U5 is connected to the output of the NOT gate U11. The set terminal of the D flip-flop U5 receives the first set signal RSTN. The output of the D flip-flop U5 is connected to the first input of the NOR gate U6. The second input of the NOR gate U6 receives the third clock stop signal TRIG_FB. The output of the NOR gate U6 is connected to the first input of the AND gate U12.
[0072] Because the clock signal is counted incrementally by a D flip-flop, a time delay occurs. Therefore, the falling edge of TRIG_FB and the rising edge of OSC_CLK_ are staggered. The signal generated after resampling by D flip-flop U5 eliminates the time delay caused by clock counting. These two signals, after passing through a NOR gate, pull the TRIG_DLY signal high, and the stabilized clock signal is output back to the Digital output. Since D flip-flop U5 uses falling edge sampling, clock glitches are avoided during clock recovery, preventing potential adverse effects and improving chip reliability.
[0073] further,
[0074] like Figure 6 As shown, the signal conversion system also includes a signal conversion processing circuit, which includes a D flip-flop U19 and a NOT gate U18. The input of the D flip-flop U19 receives a first clock conversion signal, and the output of the D flip-flop U19 outputs a second clock conversion signal. The control terminal of the D flip-flop U19 is connected to the output of the NOT gate U18. The input of the NOT gate U18 receives a second clock stop signal TRIG, and the set terminal of the D flip-flop U19 receives a first set signal RSTN.
[0075] The D flip-flops for the VBG_TRIM_DTA, VDD_TRIM_DTA, and OSC_TRIM_DTA signals are sampled using the falling edge of the TRIG signal. Therefore, when the TRIG signal changes from 1 to 0, the DFF_OSC circuit will receive the new VBG_TRIM, VDD_TRIM, or OSC_TRIM signal and transmit it to the BGR, LDO, or OSC circuit respectively, and the voltage or frequency will begin to change.
[0076] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A system for glitch-free clock signal conversion, comprising an oscillator and a digital module circuit, wherein the digital module circuit is used to output a first clock conversion signal, and the oscillator is used to output a first clock signal, characterized in that, It also includes signal conversion systems, The signal conversion system is used to receive the first clock conversion signal and output a second clock conversion signal to the oscillator. The first clock conversion signal includes a first clock frequency conversion signal OSC_TRIM_DTA, and the second clock conversion signal includes a second clock frequency conversion signal OSC_TRIM. The signal conversion system is used to receive the first clock signal OSC_CLK and output the second clock signal OSC_CLK_ATD to the digital module circuit. The signal conversion system also receives a first clock stop signal OSC_TRIG_DTA output by the digital module circuit, and after receiving the first clock stop signal OSC_TRIG_DTA, the signal conversion system outputs a low-level second clock signal OSC_CLK_ATD within a preset time. The signal conversion system includes a first trigger circuit, a second trigger circuit, a delay control circuit, and a clock signal control circuit. The input terminal of the first trigger circuit receives the first clock stop signal OSC_TRIG_DTA, the control terminal of the first trigger circuit receives the first clock signal OSC_CLK, the set terminal of the first trigger circuit receives the first set signal RSTN, and the output terminal of the first trigger circuit is used to output the second clock stop signal TRIG. The control terminal of the second trigger circuit is connected to the output terminal of the NOT gate U11. The input terminal of the NOT gate U11 receives the first clock signal OSC_CLK. The set terminal of the second trigger circuit receives the second set signal RSTN_DFF. The output terminal of the second trigger circuit is used to output the third clock stop signal TRIG_FB. The first input terminal of the delay control circuit receives the second clock stop signal TRIG, the second input terminal of the delay control circuit receives the third clock stop signal TRIG_FB, and the output terminal of the delay control circuit outputs the second set signal RSTN_DFF. The first input terminal of the clock signal control circuit receives the third clock stop signal TRIG_FB, the second input terminal of the clock signal control circuit receives the first clock signal OSC_CLK, and the output terminal of the clock signal control circuit is used to output the second clock signal OSC_CLK_ATD.
2. The system for glitch-free clock signal conversion according to claim 1, characterized in that, The first trigger circuit includes at least one D flip-flop U1. The input terminal of the D flip-flop U1 receives the first clock stop signal OSC_TRIG_DTA. The control terminal of the D flip-flop U1 receives the first clock signal OSC_CLK. The set terminal of the D flip-flop U1 receives the first set signal RSTN. The output terminal of the D flip-flop U1 is connected to the input terminal of another D flip-flop U1 or outputs a second clock stop signal TRIG.
3. The system for glitch-free clock signal conversion according to claim 1, characterized in that, The second trigger circuit includes at least one D flip-flop U17. The input terminal of the D flip-flop U17 is connected to the second output terminal of the D flip-flop U17. The control terminal of the D flip-flop U17 is connected to the output terminal of the NOT gate U11. The set terminal of the D flip-flop U17 receives a second set signal RSTN_DFF. The first output terminal of the D flip-flop U17 is connected to the control terminal of another D flip-flop U17 or outputs a third clock stop signal TRIG_FB.
4. The system for glitch-free clock signal conversion according to claim 1, characterized in that, The delay control circuit includes NOR gate U7, NOT gate U8, NAND gate U9, and NOT gate U10. The first input of NOR gate U7 receives a second clock stop signal TRIG, and the second input of NOR gate U7 receives a third clock stop signal TRIG_FB. The output of NOR gate U7 is connected to the first input of NAND gate U9 through NOT gate U8. The second input of NAND gate U9 receives a first set signal RSTN, and the output of NAND gate U9 outputs a second set signal RSTN_DFF through NOT gate U10.
5. The system for glitch-free clock signal conversion according to claim 1, characterized in that, The clock signal control circuit includes a NAND gate U12 and a NOT gate U13. The first input terminal of the NAND gate U12 receives the third clock stop signal TRIG_FB, the second input terminal of the NAND gate U12 receives the first clock signal OSC_CLK, and the output terminal of the NAND gate U12 outputs the second clock signal OSC_CLK_ATD through the NOT gate U13.
6. The system for glitch-free clock signal conversion according to claim 5, characterized in that, The clock signal control circuit also includes a D flip-flop U5 and an NOR gate U6. The input of the D flip-flop U5 receives a third clock stop signal TRIG_FB. The control terminal of the D flip-flop U5 is connected to the output of the NOT gate U11. The set terminal of the D flip-flop U5 receives a first set signal RSTN. The output of the D flip-flop U5 is connected to the first input of the NOR gate U6. The second input of the NOR gate U6 receives the third clock stop signal TRIG_FB. The output of the NOR gate U6 is connected to the first input of the NAND gate U12.
7. The system for glitch-free clock signal conversion according to claim 1, characterized in that, The signal conversion system further includes a signal conversion processing circuit, which includes a D flip-flop U19 and a NOT gate U18. The input of the D flip-flop U19 receives a first clock conversion signal, and the output of the D flip-flop U19 outputs a second clock conversion signal. The control terminal of the D flip-flop U19 is connected to the output of the NOT gate U18. The input of the NOT gate U18 receives a second clock stop signal TRIG, and the set terminal of the D flip-flop U19 receives a first set signal RSTN.
8. The system for glitch-free clock signal conversion according to claim 1, characterized in that, It also includes a linear regulator for providing VDD power to the oscillator, and the signal conversion system is further used to output a second clock conversion signal to the linear regulator. The first clock conversion signal includes a first clock voltage conversion signal VDD_TRIM_DTA, and the second clock conversion signal includes a second clock voltage conversion signal VDD_TRIM.
9. A system for glitch-free clock signal conversion according to claim 8, characterized in that, It also includes a bandgap reference circuit, which is used to provide a reference power supply to the linear regulator. The signal conversion system is also used to output a second clock conversion signal to the bandgap reference circuit. The first clock conversion signal includes a first clock reference conversion signal VBG_TRIM_DTA, and the second clock conversion signal includes a second clock reference conversion signal VBG_TRIM.