Discharge circuit, discharge method, memory, and storage system

Abstract

The application discloses a discharge circuit, a discharge method, a memory and a storage system. The discharge circuit comprises a control branch and a discharge branch. The control branch comprises a first control transistor. The discharge branch comprises a second control transistor. The first control transistor is connected in series between a node to be discharged and a first node. The first node is connected to a control end of the second control transistor. When the node to be discharged is not discharged to a target voltage, the first control transistor is turned on under the action of a first enable signal. The control end of the first control transistor is connected to the first enable signal. The second control transistor is connected in series between the node to be discharged and the ground. The control end of the second control transistor is connected to the first node. When the first control transistor is turned on, the second control transistor is turned on under the action of the voltage of the first node. The discharge branch forms a closed path, and the node to be discharged is discharged.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a discharge circuit, a discharge method, a memory, and a storage system. Background Technology

[0002] Within integrated circuits, some components have output voltages higher than the power supply voltage. When these components are not in use, their output nodes need to be discharged to ground. For example, in memory chips, the output node of the high-voltage regulator that provides the programming voltage to the selected word line needs to be discharged to ground after it completes one power supply cycle. Currently, the discharge circuits used are relatively complex, and because they are affected by logic control, they cannot cope with sudden changes, thus failing to meet the required discharge requirements. Summary of the Invention

[0003] In view of this, embodiments of this application provide a discharge circuit, a discharge method, a memory, and a storage system to solve the above problems.

[0004] Therefore, the technical solution of this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a discharge circuit, including: a control branch and a discharge branch; wherein, the control branch includes a first control transistor; and the discharge branch includes a second control transistor, wherein;

[0006] The first control transistor is connected in series between the node to be discharged and the first node; the first node is located on the connection line of the controlled terminal of the second control transistor; the controlled terminal of the first control transistor is connected to a first enable signal; when the node to be discharged has not been discharged to the target voltage, the first control transistor is turned on under the action of the first enable signal.

[0007] The second control transistor is connected in series between the node to be discharged and ground; the controlled terminal of the second control transistor is connected to the first node; when the first control transistor is turned on, the second control transistor is turned on under the voltage of the first node, and the discharge branch forms a closed circuit to discharge the node to be discharged.

[0008] Secondly, embodiments of this application also provide a discharge method applied to a discharge circuit of a node to be discharged. The discharge circuit includes a control branch and a discharge branch; wherein the control branch includes a first control transistor connected in series between the node to be discharged and a first node; the discharge branch includes a second control transistor connected in series between the node to be discharged and ground; the first node is located at the controlled terminal of the second control transistor; the controlled terminal of the second control transistor is connected to the first node; the discharge method includes:

[0009] The first control transistor is turned on based on the first enable signal received; the first enable signal in the first state is generated by the trigger included in the discharge circuit based on the received discharge trigger signal;

[0010] When the first control transistor is turned on, the voltage of the first node is increased to the first voltage;

[0011] Under the action of the first voltage, the second control transistor is turned on, forming a closed circuit in the discharge branch, and discharging the node to be discharged.

[0012] Thirdly, embodiments of this application also provide a memory, including: a memory array for storing data;

[0013] and peripheral circuitry coupled to and configured to control the memory array; wherein,

[0014] The peripheral circuit includes: the discharge circuit described in any of the preceding items.

[0015] Fourthly, embodiments of this application also provide a storage system, including: one or more of the aforementioned memories; and a memory controller coupled to the one or more memories; the memory controller is configured to control various operations of the one or more memories.

[0016] This application provides a discharge circuit, a discharge method, a memory, and a storage system. The discharge circuit includes a control branch and a discharge branch. The control branch includes a first control transistor; the discharge branch includes a second control transistor. The first control transistor is connected in series between the node to be discharged and a first node. The first node is located on the connection line of the controlled terminal of the second control transistor. The controlled terminal of the first control transistor is connected to a first enable signal. When the node to be discharged has not discharged to the target voltage, the first control transistor is turned on under the action of the first enable signal. The second control transistor is connected in series between the node to be discharged and ground. The controlled terminal of the second control transistor is connected to the first node. When the first control transistor is turned on, the second control transistor is turned on under the voltage of the first node, and the discharge branch forms a closed circuit to discharge the node to be discharged. The discharge circuit of the node to be discharged provided in this application replaces the effective signal for controlling the discharge of the discharge branch with a first enable signal whose effective duration is not affected by the effective duration of the discharge trigger signal. This makes the discharge circuit no longer affected by the effective duration of the discharge trigger signal and prevents overshoot caused by the effective duration of the discharge trigger signal being too short. Furthermore, the layout of the discharge circuit described above reduces the number of switching transistors used, thus saving chip area. Attached Figure Description

[0017] Figure 1 A schematic diagram of the discharge circuit for the node to be discharged provided in an embodiment of this application;

[0018] Figure 2 A flowchart illustrating a discharge method for a node to be discharged, provided in an embodiment of this application. Figure 1 ;

[0019] Figure 3 A flowchart illustrating a discharge method for a node to be discharged, provided in an embodiment of this application. Figure 2 ;

[0020] Figure 4 A flowchart illustrating a discharge method for a node to be discharged, provided in an embodiment of this application. Figure 3 ;

[0021] Figure 5 A schematic diagram of the discharge circuit of the output node of the high voltage regulator provided in the embodiments of this application;

[0022] Figure 6 This is a schematic diagram of an exemplary memory that includes peripheral circuitry;

[0023] Figure 7 This is a schematic diagram of the organizational structure of a storage array;

[0024] Figure 8 A side view of a cross-section of an exemplary memory array containing strings of memory cells, according to some aspects of this application;

[0025] Figure 9 A block diagram of an exemplary memory including a memory array and peripheral circuitry.

[0026] Figure 10 This application provides a schematic diagram of the structure of a storage system according to an embodiment of the present application.

[0027] Figure 11 A block diagram of an exemplary system with memory in the related art;

[0028] Figure 12 A schematic diagram of an exemplary memory card with memory;

[0029] Figure 13 This is a schematic diagram of an exemplary solid-state drive (SSD) with storage. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The flowcharts in the accompanying drawings show a logical order, but in some cases, the steps shown or described may be performed in a different order than that shown herein.

[0031] The present application will be described in detail below with reference to the accompanying drawings.

[0032] See Figure 1 ,like Figure 1 As shown, this application embodiment provides a discharge circuit 100 for a node to be discharged, which includes: a control branch ① and a discharge branch ②; wherein, the control branch ① includes a first control transistor M1; the discharge branch ② includes a second control transistor M2, wherein;

[0033] The first control transistor M1 is connected in series between the node to be discharged and the first node; the first node is located on the connection line of the controlled terminal of the second control transistor M2; the controlled terminal of the first control transistor M1 is connected to a first enable signal; when the node to be discharged has not been discharged to the target voltage, the first control transistor is turned on under the action of the first enable signal.

[0034] The second control transistor M2 is connected in series between the node to be discharged and ground; the controlled terminal of the second control transistor M2 is connected to the first node; when the first control transistor M1 is turned on, the second control transistor M2 is turned on under the voltage of the first node, and the discharge branch ② forms a closed circuit to discharge the node to be discharged.

[0035] In this embodiment, when the node to be discharged has not been discharged to the target voltage, the first enable signal is in a first state, which is generated based on the discharge trigger signal. The effective duration of the first enable signal in the first state does not depend on the effective duration of the discharge trigger signal. In other words, the duration of the first enable signal in the first state is not affected by the effective duration of the discharge trigger signal; more simply, the first enable signal can be in the first state when the discharge trigger signal changes from effective to ineffective. The discharge trigger signal is provided by the control logic unit of the memory or by the memory controller included in the memory system. In some embodiments, the discharge trigger signal is effective when it is high and ineffective when it is low, and its effective duration is the length of time the high level is maintained. In other embodiments, the discharge trigger signal is effective when it is low and ineffective when it is high, and its effective duration is the length of time the low level is maintained. Specifically, which level is used for the discharge trigger signal to be effective depends on the actual circuit design. For the overall explanation of the technical solution of this application, this application uses the condition that the discharge trigger signal is effective when it is high.

[0036] In some embodiments, the node to be discharged can be the output of a high-voltage regulator included in the memory, used to provide programming voltage to the word lines. The input of this high-voltage regulator is connected to the output of a charge pump circuit for regulating the voltage output by the charge pump circuit.

[0037] In some embodiments, the discharge circuit further includes: a trigger connected to the controlled terminal of the first control transistor, configured to receive a discharge trigger signal and generate a first enable signal in a first state based on the received discharge trigger signal; the first enable signal in the first state turns on the first control transistor.

[0038] It should be noted that the trigger can be an RS trigger. The discharge trigger signal mentioned here is the signal that triggers the discharge circuit to discharge. This discharge trigger signal is sent by the control unit (control logic unit or memory controller) coupled to the discharge circuit and is manually configured; its effective duration is a fixed value (i.e., the time it is at a high level is valid). Here, the discharge trigger signal is input into the trigger to generate a first enable signal in a first state. This first enable signal in the first state is input to the controlled terminal of the first control transistor M1, causing the first control transistor M1 to conduct.

[0039] Here, the first state can refer to the first enable signal being at a high level, or it can be said that the first enable signal is valid in the first state.

[0040] Specifically, in some embodiments, the trigger receives a discharge trigger signal and outputs a high-level signal when the rising edge of the discharge trigger signal is detected; this high-level signal is also the first enable signal in the first state. As can be seen from the characteristics of the trigger, the first enable signal in the first state can remain in the first state indefinitely until the discharge ends and is input to another input terminal of the trigger, changing the output state of the trigger.

[0041] In some embodiments, the trigger is further configured to receive a discharge stop signal and generate a first enable signal in a second state based on the discharge stop signal; the first enable signal in the second state causes the first control transistor to turn off.

[0042] Here, the discharge stop signal can refer to a signal that triggers the cessation of discharge to the node to be discharged. When the voltage of the node to be discharged drops to the target voltage or other conditions requiring the discharge to stop, a discharge stop signal is input to the trigger to generate a first enable signal in the second state. Under the action of the first enable signal in the second state, the first control transistor M1 is turned off, preparing to disconnect the discharge branch ②. Here, the second state can refer to the first enable signal being at a low level, or it can be said that the first enable signal in the second state is invalid.

[0043] In some embodiments, the control branch may further include: a first protection transistor M3 connected in series between the node to be discharged and the first control transistor, for overvoltage protection of the first control transistor.

[0044] It should be noted that the voltage of the node to be discharged may be high, while the first control transistor M1 used to control the opening or closing of the control branch is a low-voltage transistor. In order to protect the first control transistor M1, a high-voltage resistant first protection transistor M3 is connected in series near the node to be discharged on the control branch ① to reduce the voltage applied to the first control transistor M1 to a range that it can withstand, thereby protecting the first control transistor M1.

[0045] In some embodiments, the control branch ① may further include: a clamping transistor M4 connected in series between the node to be discharged and the first control transistor, wherein, when the voltage of the node to be discharged is discharged to the target voltage, the clamping transistor is turned off, so that the voltage of the node to be discharged is maintained at the target voltage.

[0046] It should be noted that clamping refers to the measure of limiting the potential of a certain point to a specified potential, which is an overvoltage protection technology. Here, the clamping transistor M4 can be a PMOS transistor controlled by v4x. When the voltage of the node to be discharged drops to v4x + |vthp|, the clamping transistor M4 turns off, causing the voltage of the first node to drop, thereby turning off the second control transistor M2, and thus disconnecting the discharge branch ②, thereby stopping the discharge to the node to be discharged and maintaining the voltage of the node to be discharged at v4x + |vthp|. This v4x + |vthp| is the desired target voltage. Where |vthp| is the absolute value of the threshold voltage of M4, and v4x is the bias voltage applied to the controlled terminal of M4.

[0047] For example, assuming the target voltage of the node to be discharged is 9 volts (V), and |vthp| is approximately 1.5V, then v4x can be 7.5V.

[0048] In some embodiments, the control branch ① may further include: a second protection transistor M5 connected in series between the clamping transistor M4 and the node to be discharged, for overvoltage protection of the clamping transistor M4.

[0049] It should be noted that, based on the clamping transistor M4 in control branch ①, in order to protect the clamping control transistor M4, a high-voltage second protection transistor M5 is connected in series after the node to be discharged to provide overvoltage protection for M4. The value of the second bias voltage vgsw connected to the controlled terminal of the second protection transistor M5 is a default value provided by the power supply in the peripheral circuits of the memory. Under this default value, the relevant switching transistors of the memory are controlled to turn off or on. For example, in this application, the value of the second bias voltage vgsw can be greater than 8V to keep the second protection transistor M5 always on.

[0050] In some embodiments, the control branch ① may further include: a third control transistor M6 connected in series between the first node and ground;

[0051] When the first control transistor M1 is turned off and / or the clamping transistor M4 is turned off, the third control transistor turns on based on the first bias voltage vb connected to its controlled terminal, causing the voltage of the first node to drop to the second voltage; the second control transistor turns off under the action of the second voltage, causing the discharge branch to be disconnected and stopping the discharge to the node to be discharged.

[0052] It should be noted that when M1 and / or M4 are turned off, it means that the discharge to the node to be discharged should be stopped. Therefore, the second control transistor M2 needs to be turned off. At this time, the controlled terminal of the second control transistor M2 needs to receive a control voltage lower than its threshold voltage. That is, the voltage of the first node needs to be reduced to turn off the second control transistor M2, thereby disconnecting the discharge branch ②.

[0053] Here, a third control transistor M6 is connected in series between the first node and ground, and its controlled terminal is connected to a first bias voltage vb. Under the action of this first bias voltage vb, the third control transistor M6 is turned on, connecting the ground voltage to the first node, that is, causing the voltage of the first node to drop to a second voltage. Under the action of the second voltage, the second control transistor M2 is turned off, causing the discharge branch ② to be disconnected, thereby stopping the discharge to the node to be discharged.

[0054] In some embodiments, the control branch ① may further include: a fourth control transistor M7 connected in series between the first node and ground, and the controlled terminal of the fourth control transistor M7 is connected to the first node; the fourth control transistor M7 and the second control transistor M2 form a current mirror for regulating the current flowing through the discharge branch ②.

[0055] It should be noted that when the voltage of the first node drops to the second voltage, the fourth control transistor M7 is turned off; when the voltage of the first node rises to the first voltage, the fourth control transistor M7 is turned on. That is, the fourth control transistor M7 only regulates the current flowing through the discharge branch ② when it is turned on. In some embodiments, the current in the discharge branch ② is adjusted by adjusting the current flowing through M7, and the two currents are positively correlated due to the effect of the current mirror structure. In some embodiments, the resistance value of M7 can be changed by altering its aspect ratio, thereby changing the current flowing through M7 under the same voltage, and thus adjusting the current in the discharge branch ②.

[0056] In some embodiments, the control branch ① may further include: a fifth control transistor M8 connected in series between the first node and ground; the controlled terminal of the fifth control transistor M8 is connected to a second enable signal that is inversely phase to the first enable signal; when the fifth control transistor M8 is turned on when the second enable signal is valid, the voltage of the first node drops to ground voltage, the second control transistor is turned off, and the discharge branch ② is disconnected.

[0057] It should be noted that the second enable signal and the first enable signal are inverse signals of each other. That is, when the first enable signal is in the first state, the second enable signal is in the second state; and when the first enable signal is in the second state, the second enable signal is in the first state. It should be understood that when a component with the node to be discharged provides voltage to other components, the discharge circuit 100 should not discharge the node to be discharged. To ensure the disconnection of the discharge branch ② of the discharge circuit 100, a fifth control transistor M8 is connected in series between the first node and ground, and its controlled terminal is connected to a second enable signal that is inversely phase to the first enable signal. When the first enable signal is in the first state (valid), the second enable signal is in the second state (invalid); when the first enable signal is in the second state (invalid), the second enable signal is in the first state (valid). When the second enable signal is in the first state (valid), the fifth control transistor M8 is turned on, pulling the voltage of the first node down to ground voltage vss, thereby turning off the second control transistor M2, and thus the discharge branch ② is disconnected, and the node to be discharged cannot be discharged.

[0058] In some embodiments, the discharge branch further includes: a third protection transistor M9 connected in series between the node to be discharged and the second control transistor or connected in series between the second node and the second control transistor, for overvoltage protection of the second control transistor; wherein the second node is located on the connection line between the second protection transistor and the clamping transistor.

[0059] It should be noted that the third protection transistor M9 has the same function as the aforementioned first protection transistor M3 and second protection transistor M5, and will not be described again here. Its connection position can be either connected in series between the node to be discharged and the second control transistor, or connected in series between the second node and the second control transistor. Figure 1 The connection shown is a series connection between the second node and the second control transistor.

[0060] In some embodiments, the discharge circuit may further include a capacitor C1 connected in series between the first node and the node to be discharged.

[0061] It should be noted that the capacitor C1 is used to control the discharge rate of the discharge branch ② relative to the voltage of the node to be discharged. Without capacitor C1, the discharge rate of the discharge branch ② might be too fast, so that the control branch ① would not have enough time to react, and the voltage of the node to be discharged might discharge below the target voltage. Therefore, capacitor C1 is used to slow down the discharge rate of the discharge branch ②.

[0062] It should be noted that, Figure 1 The first protection transistor M3, the second protection transistor M5, and the third protection transistor M9 shown are high-voltage transistors used to protect the low-voltage transistors below. All of them are multi-finger N-type transistors (NPN transistors). The third protection transistor M9 contains approximately the same number of single-finger N-type transistors as the second protection transistor M5, which is greater than the number of N-type transistors in the first protection transistor M3, making discharge branch ② the main discharge branch. Figure 1 In this diagram, the first control transistor M1, the second control transistor M2, the third control transistor M6, the fourth control transistor M7, and the fifth control transistor M8 can be N-type transistors. It should be noted that the term "multi-finger N-type transistor" can be equivalent to multiple single-finger MOS transistors connected in parallel, where a single-finger MOS transistor can refer to an NPN junction formed between each pair of source (S) and drain (D).

[0063] The discharge circuit of the node to be discharged provided in this application replaces the effective signal for controlling the discharge of the discharge branch with a first enable signal whose effective duration is not affected by the effective duration of the discharge trigger signal. This makes the discharge circuit no longer affected by the effective duration of the discharge trigger signal and prevents overshoot caused by the effective duration of the discharge trigger signal being too short. Furthermore, the layout of the discharge circuit described above reduces the number of switching transistors used, thus saving chip area.

[0064] Based on the same inventive concept, this application also provides a discharge method for a node to be discharged, applied to a discharge circuit of the node to be discharged. The discharge circuit includes: a control branch and a discharge branch; wherein, the control branch includes a first control transistor connected in series between the node to be discharged and a first node; the discharge branch includes a second control transistor connected in series between the node to be discharged and ground; the first node is located at the control terminal of the second control transistor; the control terminal of the second control transistor is connected to the first node; as shown... Figure 2 As shown, the discharge method includes:

[0065] S201: The first control transistor is turned on based on the first enable signal in the first state received by the access; the first enable signal in the first state is generated by the trigger included in the discharge circuit based on the received discharge trigger signal;

[0066] S202: When the first control transistor is turned on, the voltage of the first node is increased to a first voltage;

[0067] S203: Under the action of the first voltage, the second control transistor is turned on, so that the discharge branch forms a closed circuit and discharges the node to be discharged.

[0068] In some embodiments, such as Figure 3 As shown, the control branch further includes: a third control transistor connected in series between the first node and ground; the discharge method further includes:

[0069] S204: The first control transistor is turned off based on the first enable signal in the second state received by the access; the first enable signal in the second state is generated by the trigger based on the received discharge stop signal;

[0070] S205: Turn on the third control transistor based on the first bias voltage applied;

[0071] S206: When the first control transistor is turned off and the third control transistor is turned on, the voltage of the first node drops to the second voltage;

[0072] S207: Under the action of the second voltage, the second control transistor is turned off, the discharge branch is disconnected, and the discharge to the node to be discharged is stopped.

[0073] In some embodiments, such as Figure 4 As shown, the control branch further includes: a clamping transistor connected in series between the node to be discharged and the first control transistor, and the discharge method further includes:

[0074] S208: When the voltage of the node to be discharged drops to the target voltage, turn off the clamping transistor;

[0075] S209: Turn on the third control transistor based on the first bias voltage applied;

[0076] S2010: When the fourth control transistor is turned off and the third control transistor is turned on, the voltage of the first node drops to the second voltage.

[0077] S2011: Under the action of the second voltage, the second control transistor is turned off, the discharge branch is disconnected, and the discharge to the node to be discharged is stopped.

[0078] It should be noted that the discharge method provided in this application embodiment is based on the aforementioned discharge circuit. The working principle of each transistor has been described in detail above and will not be repeated here.

[0079] To understand this application, as Figure 5 As shown, it illustrates a schematic diagram of the discharge circuit at the output of a high-voltage regulator contained in a memory.

[0080] It should be noted that in XLC (e.g., memory with SLC, MLC, TLC, QLC, etc.) technology, the high voltage vpeh generated by the charge pump in the memory for programming operations cannot be directly used to select word lines. A high-voltage regulator is needed to regulate it to obtain vpe. During the discharge process of programming or pre-programming operations, vpe typically needs to be discharged to the voltage applied to the unselected word line. That is, in this example, the node to be discharged is the output node vpe of the high-voltage regulator in the memory. vpe_dis is the discharge trigger signal; vpe_disc is the first enable signal; vpe_disc_n is the second enable signal; and vpeh_en is the enable signal of another discharge circuit, such as the enable signal of the discharge circuit at the output of the charge pump.

[0081] exist Figure 5 In the process, the discharge process of VPE is as follows: The RS flip-flop detects the rising edge of vpe_dis and obtains the vpe_disc signal in the first state, which is also the first enable signal in the first state. When the vpe_disc signal is high, it is in the first state and is effective, controlling the first control transistor M1 to turn on. Under the action of the VPE voltage, the voltage vmdis of the first node rises to the first voltage, causing the second control transistor M2 to turn on, so that the discharge branch forms a closed circuit to discharge VPE until the voltage of VPE reaches the target voltage (e.g., 8V), and the clamping transistor M4 turns off. Under the action of the first bias voltage vb, the third control transistor M6 turns on, causing the voltage vmdis of the first node to drop to the second voltage, causing the second control transistor M2 to turn off, disconnecting the discharge branch, and stopping the discharge of VPE.

[0082] Because the high-voltage regulator coupled to the selected word line in the memory discharges first, followed by the charge pump coupled to the high-voltage regulator, after the voltage at the output terminal of the high-voltage regulator discharges to the target voltage, the discharge circuit at the output terminal of the high-voltage regulator stops discharging, while the discharge circuit at the output terminal of the charge pump starts working to discharge vpeh until the voltage of vpeh reaches its required target voltage, at which point the discharge of vpeh stops. At this point, the entire discharge process is complete, and a stop trigger signal is generated through vpeh_en (this stop trigger signal is obtained by inverting vpeh_en, that is, the stop trigger signal is inverted with vpeh_en. After the discharge of vpeh ends, vpeh_en changes from a high-level valid state to a low-level invalid state). The RS flip-flop detects the rising edge of the stop trigger signal, causing the output state of the flip-flop's output terminal Q to be in a low-level state, which is the second state vpe_disc signal. The invalid vpe_disc signal causes the first control transistor M1 to turn off, ending the entire discharge process.

[0083] This application also provides a memory, such as... Figure 6 As shown, the memory 600 includes: a memory array 601 for storing data;

[0084] and peripheral circuitry 602 coupled to the memory array and configured to control the memory array; wherein,

[0085] The peripheral circuit includes: the discharge circuit 100 described in any of the preceding claims.

[0086] It should be noted that the foregoing only describes the structure of the peripheral circuit 602 relevant to the embodiments of this application. In practice, the memory array 601 can be a NAND flash memory array, wherein the memory cells 606 are provided in the form of an array of NAND memory cell strings 608, each NAND memory cell string 608 extending vertically above a substrate (not shown). In some embodiments, each NAND memory cell string 608 includes a plurality of memory cells 606 coupled in series and stacked vertically. Each memory cell 606 can hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 606. Each memory cell 606 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0087] In some embodiments, each memory cell 606 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 606 is a multi-level cell (MLC) capable of storing a single bit of data in multiple four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to that memory cell. A fourth nominal storage value may be used for the erase state.

[0088] like Figure 6 As shown, each NAND cell string 608 may include a source select gate (SSG) 610 at its source end and a drain select gate (DSG) 612 at its drain end. SSG 610 and DSG 612 can be configured to activate the selected NAND cell string 608 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND cell strings 608 in the same block 604 are coupled via the same source line (SL) 614 (e.g., common SL). In other words, according to some embodiments, all NAND cell strings 608 in the same block 604 have an array common source (ACS). According to some embodiments, the DSG 612 of each NAND cell string 608 is coupled to a corresponding bit line 616, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory cell string 608 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG612) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG612 via one or more DSG lines 613 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG610) or a deselection voltage (e.g., 0V) to the corresponding SSG610 via one or more SSG lines 615.

[0089] like Figure 6As shown, NAND memory cell strings 608 can be organized into multiple blocks 604, each of which can have a common source line 614 (e.g., coupled to ground). In some embodiments, each block 604 is a basic data unit with an erase operation, i.e., all memory cells 606 on the same block 604 are erased simultaneously. To erase memory cells 606 in a selected block 604, a source line 614 biased to the selected block 604 and unselected blocks 604 on the same plane as the selected block 604 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 606 of adjacent NAND memory cell strings 608 can be coupled via word lines 618, which select which row of memory cells 606 receives read and program operations. In some embodiments, memory cells 606 coupled to the same word line 618 are referred to as pages 620. A page 620 is a basic unit of data used for programming or reading operations, and the size of a page 620, measured in bits, can be related to the number of NAND memory cell strings 608 coupled by word lines 618 in a block 604. Each word line 618 may include multiple control gates (gate electrodes) at each memory cell 606 within the corresponding page 620, as well as gate lines coupling the control gates.

[0090] The organization of the memory array 601 inside the memory is as follows: Figure 7 As shown. The storage array 601 can be divided into several DIEs (or LUNs), each DIE has several planes, each plane has several blocks, each block has several pages, and each page corresponds to a wordline. Wordlines connect thousands upon thousands of storage units 606. The DIE / LUN is the basic unit for receiving and executing operation commands. For example... Figure 7As shown, LUN0 and LUN1 can simultaneously receive and execute different commands (but there are still certain limitations, which vary depending on the manufacturer's flash memory). However, within a single LUN, only one command can be executed independently at a time; it's not possible to write to one page while simultaneously reading from other pages. A LUN is further divided into several Planes. Commonly available LUNs have one or two Planes, but there are also flash memory modules with four Planes, and some even have more than four Planes, such as those with six Planes. It should be understood that the number of Planes in a LUN may increase with technological advancements; this application does not impose any limitations. Each Plane has its own independent cache register and page register, the size of which is equal to the size of a page. When writing to a page, the memory controller first transfers the data from the memory controller to the cache register of the corresponding Plane, and then writes the entire cache register to the memory cell. Reading is the reverse: the data for that page is first read from the memory cell into the cache register, and then transmitted to the memory controller as needed. The "on-demand" aspect means that when we read data, it's unnecessary to send the entire page of data to the memory controller; instead, data is transferred selectively as needed. However, it's important to remember that whether reading data from a memory cell into the cache register or writing data from the cache register into a memory cell, the process is done in units of pages.

[0091] Figure 8 A side view of a cross-section of an exemplary memory array 601 including NAND memory cell strings 608, according to some aspects of this application, is shown. Figure 8 As shown, the NAND memory cell string 608 can extend vertically through the memory stack layer 802 above the substrate 801. The substrate 801 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0092] The memory stack 802 may include alternating gate conductive layers 803 and gate-to-gate dielectric layers 804. The number of pairs of gate conductive layers 803 and gate-to-gate dielectric layers 804 in the memory stack 802 determines the number of memory cells 606 in the memory array 601. The gate conductive layers 803 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 803 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 803 includes a doped polysilicon layer. Each gate conductive layer 803 may include a control gate surrounding the memory cell 606 and may extend laterally at the top of the memory stack 802 as a DSG line 613, at the bottom of the memory stack 802 as an SSG line 615, or between DSG lines 613 and SSG lines 615 as a word line 618.

[0093] like Figure 8 As shown, the NAND memory cell string 608 includes a channel structure 805 extending vertically through the memory stack layer 802. In some embodiments, the channel structure 805 includes channel holes filled with one or more semiconductor materials and one or more dielectric materials. In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 805 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0094] Return to reference Figure 6The peripheral circuitry 602 can be coupled to the memory array 601 via bit lines 616, word lines 618, source lines 614, SSG lines 615, and DSG lines 613. The peripheral circuitry 602 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 601 by applying voltage and / or current signals to each target memory cell 606 via bit lines 616, word lines 618, source lines 614, SSG lines 615, and DSG lines 613, and by sensing voltage and / or current signals from each target memory cell 606. The peripheral circuitry 602 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 9 Some exemplary peripheral circuitry is shown. Peripheral circuitry 602 includes a page buffer / sensing amplifier 904, a column decoder / bit line driver 906, a row decoder / word line driver 908, a voltage generator 910, a control logic unit 912, a register 914, an interface 916, and a data bus 918. It should be understood that in some examples, additional components may be included. Figure 9 Additional peripheral circuitry not shown.

[0095] Page buffer / sensor amplifier 904 can be configured to read data from and program (write) data to memory array 601 according to control signals from control logic unit 912. In one example, page buffer / sensor amplifier 904 can store a page of programming data (write data) to be programmed into a page 620 of memory array 601. In another example, page buffer / sensor amplifier 904 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 606 coupled to selected word line 618. In yet another example, page buffer / sensor amplifier 904 can also sense a low-power signal from bit line 616 representing a data bit stored in memory cell 606 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 906 can be configured to be controlled by control logic unit 912 and select one or more NAND memory cell strings 608 by applying a bit line voltage generated from voltage generator 910.

[0096] The row decoder / word line driver 908 can be configured to be controlled by the control logic unit 912 and to select / deselect block 604 of the memory array 601 and to select / deselect word line 618 of block 604. The row decoder / word line driver 908 can also be configured to drive word line 618 using word line voltages generated from the voltage generator 910. In some embodiments, the row decoder / word line driver 908 can also select / deselect and drive SSG line 615 and DSG line 613. As described in detail below, the row decoder / word line driver 908 is configured to perform an erase operation on memory cell 606 coupled to one or more selected word lines 618. The voltage generator 910 can be configured to be controlled by the control logic unit 912 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 601.

[0097] Control logic unit 912 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 914 can be coupled to control logic unit 912 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 916 can be coupled to control logic unit 912 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 912, as well as to buffer status information received from control logic unit 912 and relay it to the host. Interface 916 can also be coupled to column decoder / bit line driver 906 via data bus 918 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 601. The charge pump and high-voltage regulator involved in this embodiment can be included in voltage generator 910.

[0098] This application also provides a storage system, such as... Figure 10 As shown, the storage system 1000 includes: one or more of the aforementioned memory 600; and a memory controller 1001 coupled to the one or more memory; the memory controller is configured to control various operations of the one or more memory.

[0099] In some embodiments, the storage system is a solid-state drive (SSD) or a memory card.

[0100] It should be noted that storage systems can be coupled with hosts to form data systems, for example... Figure 11The data system shown. This data system 1100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 11 As shown, the data system 1100 may include a host 1108 and a storage system 1000, wherein the storage system 1000 has one or more memories 600 and a memory controller 1001; the host 1108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 1108 may be configured to send data to or receive data from the memories 600. Specifically, the memories 600 may be any memory disclosed in this application, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0101] According to some embodiments, memory controller 1001 is coupled to memory 600 and host 1108 and is configured to control memory 600. Memory controller 1001 can manage data stored in memory 600 and communicate with host 1108. In some embodiments, memory controller 1001 is designed to operate in low duty cycle environments, such as on Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices with low duty cycle environments such as personal calculators, digital cameras, and mobile phones. In some embodiments, memory controller 1001 is designed to operate in high duty cycle environments, such as on solid-state drives (SSDs) or embedded multimedia cards (eMMCs), where SSDs or eMMCs are used as data storage for mobile devices with high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The memory controller 1001 can be configured to control the operation of the memory 600, such as read, erase, and program operations. The memory controller 1001 can also be configured to manage various functions related to data stored or to be stored in the memory 600, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1001 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory 600. The memory controller 1001 can also perform any other suitable functions, such as formatting the memory 600. The memory controller 1001 can communicate with external devices (e.g., host 1108) according to a specific communication protocol.For example, the memory controller 1001 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc. The memory controller 1001 and one or more memories 600 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 1000 can be implemented and packaged into different types of end electronic products. Figure 12 In one example shown, the memory controller 1001 and a single memory 600 can be integrated into a memory card 1202. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for the memory card to a host computer (e.g., Figure 11 The host 1108 in the memory card connector 1404 is coupled to the host 1108. In such a way... Figure 13 In another example shown, the memory controller 1001 and multiple memories 600 can be integrated into the SSD 1302. The SSD may also include components for connecting the SSD to a host computer (e.g., Figure 11 The SSD connector 1304 is coupled to the host 1108 in the memory. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 1001 can also be configured to control erase, read, and write operations of the memory 600.

[0102] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A discharge circuit, characterized in that, include: A control branch and a discharge branch; wherein the control branch includes a first control transistor; the discharge branch includes a second control transistor, wherein; The first control transistor is connected in series between the node to be discharged and the first node; the first node is located on the connection line of the controlled terminal of the second control transistor; the controlled terminal of the first control transistor is connected to the first enable signal; when the node to be discharged has not been discharged to the target voltage, the first control transistor is turned on under the action of the first enable signal. The second control transistor is connected in series between the node to be discharged and ground; the controlled terminal of the second control transistor is connected to the first node; when the first control transistor is turned on, the second control transistor is turned on under the voltage of the first node, and the discharge branch forms a closed circuit to discharge the node to be discharged. The control branch also includes a third control transistor connected in series between the first node and ground. When the third control transistor is turned on, the discharge branch is disconnected, stopping the discharge to the node to be discharged.

2. The discharge circuit according to claim 1, characterized in that, The discharge circuit further includes: a trigger connected to the controlled terminal of the first control transistor, for receiving a discharge trigger signal and generating a first enable signal in a first state based on the received discharge trigger signal; the first enable signal in the first state turns on the first control transistor.

3. The discharge circuit according to claim 2, characterized in that, The trigger is further configured to receive a discharge stop signal and generate a first enable signal in a second state based on the discharge stop signal; the first enable signal in the second state causes the first control transistor to turn off.

4. The discharge circuit according to claim 1, characterized in that, The control branch further includes a first protection transistor connected in series between the node to be discharged and the first control transistor, for overvoltage protection of the first control transistor.

5. The discharge circuit according to claim 1, characterized in that, The control branch further includes a clamping transistor connected in series between the node to be discharged and the first control transistor, wherein when the voltage of the node to be discharged discharges to the target voltage, the clamping transistor is turned off, so that the voltage of the node to be discharged is maintained at the target voltage.

6. The discharge circuit according to claim 5, characterized in that, The control branch further includes a second protection transistor connected in series between the clamping transistor and the node to be discharged, for overvoltage protection of the clamping transistor.

7. The discharge circuit according to claim 5, characterized in that, When the first control transistor is turned off and / or the clamping transistor is turned off, the third control transistor turns on based on the first bias voltage connected to its controlled terminal, causing the voltage of the first node to drop to the second voltage. The second control transistor is turned off under the action of the second voltage, thereby disconnecting the discharge branch and stopping the discharge to the node to be discharged.

8. The discharge circuit according to claim 1, characterized in that, The control branch further includes: a fourth control transistor connected in series between the first node and ground, and the controlled terminal of the fourth control transistor is connected to the first node; the fourth control transistor and the second control transistor form a current mirror for regulating the current flowing through the discharge branch.

9. The discharge circuit according to claim 1, characterized in that, The control branch further includes: a fifth control transistor connected in series between the first node and ground; the controlled terminal of the fifth control transistor is connected to a second enable signal that is inversely phase to the first enable signal; when the fifth control transistor is turned on when the second enable signal is valid, the voltage of the first node drops to ground voltage, the second control transistor is turned off, and the discharge branch is ensured to be disconnected.

10. The discharge circuit according to claim 6, characterized in that, The discharge branch further includes a third protection transistor connected in series between the node to be discharged and the second control transistor or connected in series between the second node and the second control transistor, for overvoltage protection of the second control transistor; wherein the second node is located on the connection line between the second protection transistor and the clamping transistor.

11. The discharge circuit according to claim 1, characterized in that, The discharge circuit further includes a capacitor connected in series between the first node and the node to be discharged.

12. The discharge circuit according to claim 1, characterized in that, The node to be discharged is the output of a high-voltage regulator included in the memory, which provides programming voltage to the word lines.

13. A discharge method, characterized in that, A discharge circuit applied to a node to be discharged, the discharge circuit comprising: a control branch and a discharge branch; wherein, the control branch includes a first control transistor connected in series between the node to be discharged and a first node; the discharge branch includes a second control transistor connected in series between the node to be discharged and ground; the first node is connected to a connection line at the controlled terminal of the second control transistor; the controlled terminal of the second control transistor is connected to the first node; the control branch further includes a third control transistor connected in series between the first node and ground; the discharge method includes: The first control transistor is turned on based on the first enable signal in the first state of the access; the first enable signal in the first state is generated by the trigger included in the discharge circuit based on the received discharge trigger signal; When the first control transistor is turned on, the voltage of the first node is increased to the first voltage; Under the action of the first voltage, the second control transistor is turned on, so that the discharge branch forms a closed circuit and discharges the node to be discharged. When the third control transistor is turned on, the discharge branch is disconnected, stopping the discharge to the node to be discharged.

14. A memory, characterized in that, Includes: storage arrays for storing data; and peripheral circuitry coupled to and configured to control the memory array; wherein, The peripheral circuit includes the discharge circuit according to any one of claims 1 to 12.

15. A storage system, characterized in that, include: One or more of the memories described in claim 14; and a memory controller coupled to the one or more memories; The memory controller is configured to control various operations of the one or more memories.

16. The storage system according to claim 15, characterized in that, The storage system is a solid-state drive (SSD) or a memory card.

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