Micro-bumps and methods for forming the same, chip interconnect structures and methods

Abstract

An embodiment of the present application provides a micro-bump and a method for forming the same, a chip interconnect structure and a method. Among them, the method for forming the micro-bump includes: providing a chip, the chip at least includes a silicon substrate and a through-silicon via penetrating the silicon substrate; forming a conductive layer in the through-silicon via, wherein the conductive layer has a first preset size in a first direction, and the first direction is the thickness direction of the silicon substrate; forming a connection layer on the surface of the conductive layer in the through-silicon via; wherein the connection layer has a second preset size in the first direction; the sum of the first preset size and the second preset size is equal to the initial size of the through-silicon via in the first direction; processing the silicon substrate to expose the connection layer and form a micro-bump corresponding to the through-silicon via. Through the present application, it is possible to fabricate micro-bumps with small size and small pitch.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a micro-bump and a method for forming the same, a chip interconnection structure and a method therefor. Background Art

[0002] In the semiconductor packaging process, the flip-chip bonding process is usually used to bond a chip to a substrate or a chip to a chip. In the related art, copper pillar bumps are usually used to achieve the bonding between a chip and a substrate or between chips. The copper pillar bump technology is a technology for fabricating solder bumps on the surface of a chip, enabling the chip to have better electrical conductivity, thermal conductivity, and electromigration resistance. Using copper pillar bumps for packaging can not only shorten the length of the connection circuit, reduce the area and volume of the chip package, and achieve miniaturization, but also improve the performance of the chip package module.

[0003] However, with the continuous increase in chip integration, the pitch between adjacent bumps is getting smaller and smaller. Due to the limitations of its own process, the copper pillar bump technology in the related art cannot meet the requirements of small pitch and small size. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a micro-bump and a method for forming the same, a chip interconnection structure and a method therefor.

[0005] In a first aspect, an embodiment of the present application provides a method for forming a micro-bump, including:

[0006] Providing a chip, where the chip at least includes a silicon substrate and a silicon through hole penetrating the silicon substrate;

[0007] Forming a conductive layer in the silicon through hole, where the conductive layer has a first preset size in a first direction, and the first direction is the thickness direction of the silicon substrate;

[0008] Forming a connection layer on the surface of the conductive layer in the silicon through hole; where the connection layer has a second preset size in the first direction; the sum of the first preset size and the second preset size is equal to the initial size of the silicon through hole in the first direction;

[0009] Processing the silicon substrate to expose the connection layer and form a micro-bump corresponding to the silicon through hole.

[0010] In some embodiments, before forming the conductive layer, the method further includes:

[0011] Depositing an insulating material on the inner wall of the silicon through hole to form an insulating layer;

[0012] Deposit a barrier material on the surface of the insulating layer to form a barrier layer;

[0013] Deposit a seed material on the surface of the barrier layer to form a seed layer.

[0014] In some embodiments, forming a conductive layer in the through-silicon via includes:

[0015] Using an electrochemical deposition process, electroplate a conductive material on the surface of the seed layer in the through-silicon via to form the conductive layer;

[0016] Wherein, the conductive material is the same as the seed material.

[0017] In some embodiments, forming a connection layer on the surface of the conductive layer in the through-silicon via includes:

[0018] Deposit a welding material on the surfaces of the conductive layer and the seed layer in the through-silicon via to form the connection layer;

[0019] Wherein, the welding material includes a nickel-gold conductive material or solder paste.

[0020] In some embodiments, the insulating layer, the barrier layer, and the seed layer are formed on the first surface of the silicon substrate; the method further includes:

[0021] After forming the connection layer, perform chemical mechanical polishing on the first surface of the silicon substrate to remove the insulating layer, the barrier layer, and the seed layer on the first surface of the silicon substrate.

[0022] In some embodiments, processing the silicon substrate to expose the connection layer and form a microbump corresponding to the through-silicon via includes:

[0023] Taking the first surface of the silicon substrate as an etching starting point, removing the silicon substrate with the second preset size, and retaining the insulating layer, the barrier layer, and the seed layer on the sidewalls of the connection layer, exposing the connection layer with the second preset size, and forming a microbump corresponding to the through-silicon via.

[0024] In some embodiments, processing the silicon substrate to expose the connection layer and form a microbump corresponding to the through-silicon via includes:

[0025] Taking the first surface of the silicon substrate as an etching starting point, removing the silicon substrate with the second preset size and the insulating layer, the barrier layer, and the seed layer on the sidewalls of the connection layer, exposing the connection layer with the second preset size, and forming a microbump corresponding to the through-silicon via.

[0026] In some embodiments, providing the chip includes:

[0027] Provide the silicon substrate;

[0028] Using the first surface of the silicon substrate as the etching starting point, etch the silicon substrate to form the silicon through hole penetrating the silicon substrate;

[0029] Wherein, the size of the silicon through hole in the second direction is less than 15 microns, and the pitch between two adjacent silicon through holes is less than 20 microns; the second direction is perpendicular to the first direction.

[0030] In some embodiments, forming the silicon through hole penetrating the silicon substrate includes:

[0031] Form a first photoresist layer on the first surface of the silicon substrate;

[0032] Pattern the first photoresist layer to form a window that exposes the first surface of the silicon substrate;

[0033] Through the window, etch the silicon substrate to form the silicon through hole penetrating the silicon substrate.

[0034] In some embodiments, the chip further includes:

[0035] A dielectric layer located on the second surface of the silicon substrate; metal interconnect lines connected to the silicon through holes are formed in the dielectric layer; wherein, the first surface and the second surface of the silicon substrate are two opposite surfaces of the silicon substrate along the first direction;

[0036] The silicon through hole and the metal interconnect lines are jointly used to transmit the signal on the first surface of the silicon substrate to the second surface of the silicon substrate.

[0037] In some embodiments, the metal interconnect lines located in the dielectric layer are formed by the following method:

[0038] Deposit a dielectric material on the second surface of the silicon substrate to form the dielectric layer;

[0039] Form a patterned second photoresist layer on the surface of the dielectric layer;

[0040] Through the second photoresist layer, etch the dielectric layer to form the interconnect holes located in the dielectric layer;

[0041] Fill the interconnect holes with a conductive material to form the metal interconnect lines located in the dielectric layer.

[0042] In some embodiments, the chip further includes bonding pads located on the second surface of the silicon substrate;

[0043] The first end of the solder pad is connected to the internal circuit of the chip, and the second end of the solder pad is connected to the metal interconnect line in the dielectric layer; the metal interconnect line is further configured to lead out the signals on the second side of the silicon substrate.

[0044] In a second aspect, an embodiment of the present application provides a microbump, which is formed by the above-mentioned method for forming a microbump;

[0045] The microbump is located in the through-silicon via structure of the chip, and the microbump is at least used to realize the interconnection between two chips.

[0046] In some embodiments, the chip includes a through-silicon via penetrating the silicon substrate of the chip;

[0047] The through-silicon via corresponds to the microbump, and the size of the microbump in the direction perpendicular to the first direction is smaller than the size of the through-silicon via in the direction perpendicular to the first direction;

[0048] Wherein, the first direction is the thickness direction of the silicon substrate.

[0049] In some embodiments, the size of the microbump in the second direction is less than 15 microns, and the pitch between two adjacent microbumps is less than 20 microns, wherein the second direction is perpendicular to the first direction.

[0050] In a third aspect, an embodiment of the present application provides a method for chip interconnection, including:

[0051] Providing at least two chips; the chips include through-silicon vias that are open along the first side of the chip and a dielectric layer located on the second side of the chip; metal interconnect lines connected to the through-silicon vias are formed in the dielectric layer; the first side and the second side are two opposite sides of the chip along the thickness direction of the chip;

[0052] At corresponding positions of the through-silicon vias of the chip, microbumps located on the first side of the chip are formed by the above-mentioned method for forming microbumps;

[0053] Ball planting is performed on the exposed surface of the metal interconnect line in the chip to form bonding bumps located on the second side of the chip;

[0054] Aligning and bonding the microbumps on the first side of the first chip among the at least two chips with the welding bumps on the second side of the second chip among the at least two chips, so as to realize the interconnection between the at least two chips through the microbumps.

[0055] In a fourth aspect, an embodiment of the present application provides a chip interconnection structure, including:

[0056] At least two chips; the chips include through-silicon vias that are open along a first surface of the chip and a dielectric layer located on a second surface of the chip; metal interconnect lines connected to the through-silicon vias are formed in the dielectric layer; the first surface and the second surface are two opposite surfaces of the chip along the thickness direction of the chip;

[0057] Micro-bumps located on the first surface of the chip, wherein the micro-bumps are connected to the through-silicon vias; the micro-bumps are formed by the above-mentioned method for forming micro-bumps;

[0058] Bonding bumps located on the second surface of the chip; wherein the bonding bumps are connected to the metal interconnect lines;

[0059] The micro-bumps on the first surface of the first chip among the at least two chips are electrically connected to the bonding bumps on the second surface of the second chip among the at least two chips.

[0060] The present application provides a method for forming a micro-bump and a chip interconnection structure and method thereof. The method for forming a micro-bump includes: providing a chip, the chip at least includes a silicon substrate and a through-silicon via penetrating the silicon substrate; forming a conductive layer in the through-silicon via, and forming a connection layer on the surface of the conductive layer in the through-silicon via; processing the silicon substrate to expose the connection layer to form a micro-bump corresponding to the through-silicon via. In the embodiments of the present application, since the connection layer for forming the micro-bump is formed in the through-silicon via, by removing the silicon substrate to expose the connection layer, a micro-bump corresponding to the through-silicon via can be formed. In this way, it is possible to fabricate micro-bumps with small size and small pitch. Description of the Drawings

[0061] In the drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0062] Figure 1 It is a schematic cross-sectional structure diagram of a chip packaged using TSV technology in the related art;

[0063] Figure 2 It is an optional flowchart of a method for forming a micro-bump provided by an embodiment of the present application;

[0064] Figures 3a - 3k It is a flowchart for forming a micro-bump provided by an embodiment of the present application;

[0065] Figure 4 It is an optional schematic structural diagram of a chip and a micro-bump provided by an embodiment of the present application;

[0066] Figure 5An optional flowchart of the chip interconnection method provided by an embodiment of the present application;

[0067] Figure 6 An optional structural schematic diagram of the chip interconnection structure provided by an embodiment of the present application;

[0068] The description of the reference numerals is as follows:

[0069] 101 / 301 / 401 / 6013—Dielectric layer; 102 / 3011 / 4011—Metal interconnect line; 103—Copper pillar bump; 1031—Copper pillar; 1032—Tin block; 104 / 305 / 4001 / 6011 / 6012—Through-silicon via; 300 / 400—Silicon substrate; 301—Dielectric layer; 302—Bond pad; 303—Internal circuit; 304—First photoresist layer; 3041—Window; 306—Insulating layer; 307—Barrier layer; 308—Seed layer; 309—Conductive layer; 310—Connection layer; 50 / 71—Micro bump; 601 / 602—Chip; 72—Bonding bump. Detailed implementation manners

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will further describe the specific technical solutions of the invention in detail with reference to the accompanying drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application but are not intended to limit the scope of the present application.

[0071] In subsequent descriptions, the use of suffixes such as "module" or "unit" for representing elements is only for the convenience of description of the present application, and it has no specific meaning itself. Therefore, "module" or "unit" can be used interchangeably.

[0072] Before describing the micro bump of the embodiment of the present application, first, the copper pillar bump in the related art will be introduced.

[0073] In the related art, copper pillar bumps are usually used to achieve the bonding between a chip and a substrate or between chips. Figure 1 A cross-sectional structural schematic diagram of a chip encapsulated using the TSV technology in the related art, as Figure 1 shown. A metal interconnect line 102 located in the dielectric layer 101 is formed on the first surface of the chip (such as Figure 1 the A surface shown in Figure 1 ), and the metal interconnect line 102 is used to lead out the signals on the first surface of the chip; a copper pillar bump 103 is formed on the second surface of the chip (such as Figure 1It can be seen that the size D1 of the copper pillar bump in the related art is larger than the size D2 of the through-silicon via.

[0074] As the chip integration level continues to increase, the pitch between adjacent bumps becomes smaller and smaller. However, the size of the copper pillar bumps formed in the related art is relatively large, and it is impossible to achieve a bump pitch less than 20 micrometers. Therefore, it cannot meet the requirements for micro-bumps with small pitch and small size in the current chip stacking technology.

[0075] Based on the above problems existing in the related art, an embodiment of the present application provides a method for forming micro-bumps. Usually, a chip transmits signals from the front side of the chip to the back side through the through-silicon via (TSV) technology, and the direct stacking between chips requires interconnection through micro-bumps. Figure 2 As shown in Figure 2 a schematic flowchart of an optional method for forming micro-bumps provided by an embodiment of the present application, the method includes the following steps:

[0076] Step S201, provide a chip, where the chip at least includes a silicon substrate and a through-silicon via penetrating the silicon substrate.

[0077] Various active devices and circuits are formed inside the chip to implement various functions. In the embodiment of the present application, the chip at least includes a silicon substrate.

[0078] The through-silicon via is a via formed inside the chip and penetrating the silicon substrate of the chip. The inside of the through-silicon via is filled with a conductive material to implement the transmission of signals from the front side of the chip to the back side of the chip.

[0079] The silicon substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface of the silicon substrate, a direction perpendicular to the top surface and the bottom surface of the silicon substrate, that is, the thickness direction of the silicon substrate, is defined as the first direction. Inside the top surface and the bottom surface of the silicon substrate (i.e., the plane where the silicon substrate is located), any one direction is defined as the second direction. Here, the first direction is perpendicular to the second direction. In the embodiment of the present application, the first direction is defined as the X-axis direction, and the second direction is defined as the Y-axis direction.

[0080] Step S202, form a conductive layer in the through-silicon via.

[0081] Wherein, the conductive layer has a first preset size in the first direction, and the first direction is the thickness direction of the silicon substrate.

[0082] In some embodiments, the conductive material of the conductive layer may be metal copper or metal tungsten.

[0083] In other embodiments, before forming the conductive layer in the through-silicon via, an insulating layer, a barrier layer, and a seed layer may be formed in the through-silicon via first. Among them, the material of the insulating layer may be SiO2; the material of the barrier layer may be tantalum or tantalum nitride; the material of the seed layer may be tungsten, cobalt, copper, aluminum, or any combination thereof.

[0084] Step S203: Form a connection layer on the surface of the conductive layer in the through-silicon via.

[0085] Among them, the connection layer has a second preset size in the first direction; the sum of the first preset size and the second preset size is equal to the initial size of the through-silicon via in the first direction.

[0086] In the embodiments of the present application, the connection layer is used to form subsequent micro-bumps.

[0087] Step S204: Process the silicon substrate to expose the connection layer and form micro-bumps corresponding to the through-silicon vias.

[0088] In the embodiments of the present application, processing the silicon substrate refers to etching the silicon substrate or thinning the silicon substrate to expose the connection layer. Here, etching the silicon substrate may be etching the silicon substrate using a dry etching process, and the dry etching process may be a plasma etching process, a reactive ion etching process, or an ion milling process.

[0089] It should be noted that in the embodiments of the present application, processing the silicon substrate to expose the connection layer has two meanings: one is to process the silicon substrate to completely expose the connection layer; the other is to process the silicon substrate to expose a part of the connection layer.

[0090] In the embodiments of the present application, forming micro-bumps corresponding to the through-silicon vias means, on the one hand, that the positions of the formed micro-bumps correspond to the through-silicon vias, that is, a micro-bump will be formed corresponding to the position of each through-silicon via; on the other hand, since the micro-bumps in the embodiments of the present application are formed inside the through-silicon vias, the size of the formed micro-bumps is less than or equal to the size of the through-silicon vias.

[0091] In the method for forming micro-bumps provided by the embodiments of the present application, since the connection layer for forming the micro-bumps is formed in the through-silicon via, by removing the silicon substrate to expose the connection layer, micro-bumps corresponding to the through-silicon vias can be formed. In this way, it is possible to fabricate micro-bumps with small size and small pitch.

[0092] Figures 3a - 3k FIG. is a schematic flow chart of forming micro-bumps provided by the embodiments of the present application. Next, please refer to Figures 3a - 3k For a further detailed description of the method for forming micro-bumps provided by the embodiments of the present application.

[0093] First, reference can be made toFigures 3a - 3d , perform step S201: Provide a chip, where the chip at least includes a silicon substrate and through - silicon vias penetrating the silicon substrate.

[0094] In an embodiment of the present application, the chip includes a silicon substrate and through - silicon vias that are open on a first surface of the silicon substrate. The chip further includes a dielectric layer on a second surface of the silicon substrate, and metal interconnect lines connected to the through - silicon vias are formed in the dielectric layer. The through - silicon vias and the metal interconnect lines are jointly used to transmit signals on the first surface of the silicon substrate (i.e., the first surface of the chip) to the second surface of the silicon substrate (i.e., the second surface of the chip), or to transmit signals on the second surface of the silicon substrate (i.e., the second surface of the chip) to the first surface of the silicon substrate (i.e., the first surface of the chip). The first surface and the second surface of the silicon substrate are two opposite surfaces of the silicon substrate along a first direction. The first direction is the thickness direction of the silicon substrate.

[0095] In some embodiments, the chip further includes bonding pads on the second surface of the silicon substrate; a first end of the bonding pad is connected to an internal circuit of the chip, and a second end of the bonding pad is connected to the metal interconnect lines in the dielectric layer; the metal interconnect lines are further used to lead out signals on the second surface of the silicon substrate (i.e., the second surface of the chip).

[0096] In some embodiments, the metal interconnect lines in the dielectric layer are formed by the following method:

[0097] Deposit a dielectric material on the second surface of the silicon substrate to form the dielectric layer.

[0098] Here, the dielectric material may be SiO2 or other insulating materials. The process of depositing the dielectric material on the second surface of the silicon substrate may include Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).

[0099] Form a patterned second photoresist layer on the surface of the dielectric layer.

[0100] Etch the dielectric layer through the second photoresist layer to form interconnect holes in the dielectric layer.

[0101] Fill the interconnect holes with a conductive material to form the metal interconnect lines in the dielectric layer.

[0102] In some embodiments, the conductive material includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0103] In some embodiments, during the formation of the chip, a dielectric layer and metal interconnects are first formed, and then through-silicon vias are formed. Figure 3a FIG. is a schematic cross-sectional structure diagram of the dielectric layer and metal interconnects provided by the embodiments of the present application. As Figure 3a shown, a dielectric layer 301 is formed on the second surface (such as the C surface shown in Figure 3a ) of the silicon substrate 300, and metal interconnects 3011 are formed in the dielectric layer 301. The chip further includes a bonding pad 302 located on the second surface of the silicon substrate. The first end of the bonding pad 302 is connected to the internal circuit 303 in the chip, and the second end of the bonding pad 302 is connected to the metal interconnects 3011 in the dielectric layer 301.

[0104] In some embodiments, the chip provided can be realized through the following steps:

[0105] Step S2011: Provide the silicon substrate.

[0106] Step S2012: Using the first surface of the silicon substrate as the etching starting point, etch the silicon substrate to form the through-silicon vias penetrating the silicon substrate.

[0107] In some embodiments, the formation of the through-silicon vias penetrating the silicon substrate can be formed through the following steps:

[0108] Form a first photoresist layer on the surface of the silicon substrate.

[0109] Here, the first photoresist layer can be formed on the first surface of the silicon substrate through any suitable deposition process.

[0110] Pattern the first photoresist layer to form a window, and the window exposes the first surface of the silicon substrate.

[0111] In some embodiments, the first photoresist layer can be patterned through steps such as exposure and development to form the window.

[0112] As Figure 3b shown, a first photoresist layer 304 is formed on the first surface (such as the D surface in Figure 3b ) of the silicon substrate 300, and the first photoresist layer 304 is patterned to form a window 3041, and the window 3041 exposes the first surface of the silicon substrate. It should be noted that Figure 3b only one window is exemplarily shown in the first photoresist layer. In the actual process, at least two windows can be formed in the first photoresist layer.

[0113] In the embodiments of the present application, the size of the formed through-silicon vias in the Y-axis direction is less than 15 microns, and the pitch between adjacent two through-silicon vias is less than 20 microns.

[0114] Through the window, etch the silicon substrate to form a through-silicon via penetrating the silicon substrate.

[0115] As Figure 3c shown, by etching the silicon substrate 300 through the window 3041, a through-silicon via 305 penetrating the silicon substrate 300 is formed. It should be noted that Figure 3c only one through-silicon via is exemplarily shown herein. In the actual process, at least two through-silicon vias are formed in the chip.

[0116] In some embodiments, after forming the through-silicon via through the window in the first photoresist layer, the method for forming the micro-bump further includes: removing the first photoresist layer.

[0117] In the embodiments of the present application, the first photoresist layer can be removed by a wet etching process or a dry etching process. As Figure 3d shown, the first photoresist layer is removed, exposing the D surface of the silicon substrate 300.

[0118] Next, reference can be made to Figures 3e - 3g , and step S202 is performed: forming a conductive layer in the through-silicon via.

[0119] In some embodiments, before forming the conductive layer in the through-silicon via, the method for forming the micro-bump further includes the following steps:

[0120] Deposit an insulating material on the inner wall of the through-silicon via to form an insulating layer.

[0121] In the embodiments of the present application, the insulating material can be silicon oxide or silicon oxynitride, and the insulating layer is used to protect the silicon substrate from being damaged. Here, the insulating layer can be formed by any suitable deposition process.

[0122] In some embodiments, the silicon substrate can also be oxidized by in-situ oxidation under high temperature and high pressure conditions to form an insulating layer on the inner wall of the through-silicon via.

[0123] As Figure 3e shown, the insulating layer 306 is formed on both the inner wall of the through-silicon via 305 and the first surface (D surface) of the silicon substrate 300.

[0124] Deposit a barrier material on the surface of the insulating layer to form a barrier layer.

[0125] In the embodiments of the present application, the barrier material can be tantalum or tantalum nitride, and the barrier layer is used to prevent the diffusion of the conductive material filled in the through-silicon via subsequently. Here, the barrier layer can be formed by any suitable deposition process.

[0126] Deposit a seed material on the surface of the barrier layer to form a seed layer.

[0127] In the embodiments of the present application, the seed layer material can be any conductive material, for example, tungsten, cobalt, copper, aluminum, or any combination thereof. The seed layer is used to provide a connection function for subsequently forming a conductive layer in the through-silicon via.

[0128] As Figure 3f shown, a barrier layer 307 is formed on the surface of the insulating layer 306, and a seed layer 308 is formed on the surface of the barrier layer 307.

[0129] In some embodiments, forming the conductive layer in the through-silicon via may include the following steps:

[0130] Step S2021: Electroplate a conductive material on the surface of the seed layer in the through-silicon via by using an electrochemical deposition process to form the conductive layer.

[0131] In some embodiments, the conductive material includes: tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. The conductive material and the seed material may be the same or different. In the embodiments of the present application, both the conductive material and the seed material for forming the conductive layer are metallic copper.

[0132] As Figure 3g shown, a conductive material is electroplated in the through-silicon via by using an electrochemical deposition process to form a conductive layer 309. The conductive layer 309 has a first preset dimension D3 in the X-axis direction, and the first preset dimension D3 is smaller than the initial dimension D4 of the through-silicon via in the X-axis direction. That is, in the embodiments of the present application, the conductive layer 309 does not fill the through-silicon via.

[0133] Next, reference can be made to Figure 3h and 3i to perform step S203: Form a connection layer on the surface of the conductive layer in the through-silicon via.

[0134] In some embodiments, forming the connection layer on the surface of the conductive layer in the through-silicon via includes the following steps:

[0135] Step S2031: Deposit a welding material on the surfaces of the conductive layer and the seed layer in the through-silicon via to form the connection layer.

[0136] In the embodiments of the present application, the welding material includes a nickel-gold (Ni / Au) conductive material or solder paste (Solder). Here, the connection layer can be formed by any suitable deposition process.

[0137] As Figure 3hAs shown, a welding material is deposited on the surfaces of the conductive layer 309 and the seed layer 308 in the through-silicon via to form a connection layer 310. The connection layer 310 has a second preset dimension D5 in the X-axis direction, and the sum of the second preset dimension D5 and the first preset dimension D3 is equal to the initial dimension D4 of the through-silicon via in the X-axis direction.

[0138] In some embodiments, when forming the insulating layer, the barrier layer, and the seed layer in the through-silicon via, the insulating layer, the barrier layer, and the seed layer are also formed on the first surface of the silicon substrate simultaneously. The method for forming the micro-bumps further includes:

[0139] After forming the connection layer, a chemical mechanical polishing process is performed on the first surface of the silicon substrate to remove the insulating layer, the barrier layer, and the seed layer on the first surface of the silicon substrate.

[0140] As Figure 3i shown, a chemical mechanical polishing process is performed on the first surface (D surface) of the silicon substrate 300 to remove the insulating layer, the barrier layer, and the seed layer on the first surface of the silicon substrate 300, exposing the first surface of the silicon substrate 300.

[0141] Next, reference can be made to Figure 3j and 3k to perform step S204, process the silicon substrate, expose the connection layer, and form micro-bumps corresponding to the through-silicon via.

[0142] In some embodiments, the process of processing the silicon substrate, exposing the connection layer, and forming micro-bumps corresponding to the through-silicon via may include the following steps:

[0143] Step S2041: Taking the first surface of the silicon substrate as the etching starting point, removing the silicon substrate with the second preset dimension, retaining the insulating layer, the barrier layer, and the seed layer on the sidewalls of the connection layer, exposing the connection layer with the second preset dimension, and forming micro-bumps corresponding to the through-silicon via.

[0144] As Figure 3j shown, taking the D surface of the silicon substrate 300 as the etching starting point, using a dry etching process to etch and remove the silicon substrate with the second preset dimension D5, and retaining the insulating layer 306, the barrier layer 307, and the seed layer on the sidewalls of the connection layer 310, exposing the connection layer 310 with the second preset dimension D5, and forming micro-bumps corresponding to the through-silicon via.

[0145] In the embodiments of the present application, the formed micro - bumps not only include a connection layer, but also include a barrier layer and an insulating layer located on the sidewalls of the connection layer. The size of the formed micro - bumps in the Y - axis direction is equal to the size of the through - silicon via in the Y - axis direction. The insulating layer and the barrier layer can, to a certain extent, prevent the welding material of the connection layer from overflowing and avoid bridging between the connection layers.

[0146] In some embodiments, the processing of the silicon substrate to expose the connection layer and form micro - bumps corresponding to the through - silicon vias may include the following steps:

[0147] Step S2042: Taking the first surface of the silicon substrate as the etching starting point, removing the silicon substrate with the second preset size and the insulating layer, the barrier layer, and the seed layer located on the sidewalls of the connection layer, exposing the connection layer with the second preset size, and forming micro - bumps corresponding to the through - silicon vias.

[0148] As Figure 3k shown, taking the D surface of the silicon substrate 300 as the etching starting point, using a dry - etching process to etch and remove the silicon substrate with the second preset size D5, and etching and removing the insulating layer, the barrier layer, and the seed layer located on the sidewalls of the connection layer 310, exposing the connection layer 310 with the second preset size D5, and forming micro - bumps corresponding to the through - silicon vias.

[0149] In the embodiments of the present application, the formed micro - bumps only include a connection layer, and do not include a barrier layer and an insulating layer located on the sidewalls of the connection layer. The size of the formed micro - bumps in the Y - axis direction is equal to the size of the conductive layer in the Y - axis direction, and the size of the micro - bumps in the Y - axis direction is smaller than the size of the through - silicon vias in the Y - axis direction. In the embodiments of the present application, by removing the insulating layer and the barrier layer on the sidewalls of the connection layer, micro - bumps with small size and small pitch can be prepared.

[0150] In some embodiments, the silicon substrate with the second preset size and the insulating layer, the barrier layer, and the seed layer located on the sidewalls of the connection layer can be etched and removed simultaneously, or the silicon substrate with the second preset size and the insulating layer, the barrier layer, and the seed layer located on the sidewalls of the connection layer can be removed sequentially.

[0151] The embodiments of the present application provide a new method for preparing micro - bumps, which can realize the preparation of Micro bumps with small size and small pitch to meet the requirements of three - dimensional (3D) interconnection of future appropriate - pitch bumps. Through the micro - bumps formed by the embodiments of the present application, the bump size can be controlled below 15 microns. For example, the bump size can be 7 microns; the bump pitch can be controlled below 20 microns. For example, the bump pitch can be 10 microns.

[0152] In the embodiments of the present application, during the implementation of the Through-Silicon Via (TSV) Via last packaging process, part of the filling is first passed, and the remaining part is filled with Ni / Au Micro Bump or Solder. The excess silicon is etched to expose the Micro Bump. Through the method for forming a micro bump provided by the embodiments of the present application, both the Bump pitch and the Bump size of the formed micro bump can be reduced to varying degrees.

[0153] The embodiments of the present application provide a micro bump, which is formed by the method for forming a micro bump provided by the above embodiments. The micro bump is located in the Through-Silicon Via structure of the chip, and the micro bump is at least used to realize the interconnection between two chips.

[0154] In other embodiments, the micro bump is also used to realize the interconnection between the chip and the substrate.

[0155] Figure 4 FIG. is an optional structural schematic diagram of the chip and the micro bump provided by the embodiments of the present application. As Figure 4 shown, the chip includes a silicon substrate 400 and a dielectric layer 401 on the surface of the silicon substrate 400. A Through-Silicon Via 4001 is formed in the silicon substrate. The Through-Silicon Via 4011 corresponds to the micro bump 50. The size D6 of the micro bump 50 in the Y-axis direction is smaller than the size D7 of the Through-Silicon Via 4001 in the Y-axis direction.

[0156] It should be noted that Figure 4 only one Through-Silicon Via and one micro bump are shown. In the actual manufacturing process, the chip includes at least two Through-Silicon Vias, and a micro bump is formed corresponding to each Through-Silicon Via.

[0157] In the embodiments of the present application, the size of the micro bump in the Y-axis direction is less than 15 microns, and the pitch between two adjacent micro bumps is less than 20 microns.

[0158] In some embodiments, a metal interconnect line 4011 connected to the Through-Silicon Via 4001 is also formed in the dielectric layer 401. The Through-Silicon Via 4001 and the metal interconnect line 4011 are jointly used to transmit the signal on the first surface of the silicon substrate 400 (i.e., the first surface of the chip) to the second surface of the silicon substrate 400 (i.e., the second surface of the chip), or transmit the signal on the second surface of the silicon substrate (i.e., the second surface of the chip) to the first surface of the silicon substrate (i.e., the first surface of the chip). The first surface and the second surface of the silicon substrate are two opposite surfaces of the silicon substrate along the X-axis direction.

[0159] The micro bump provided by the embodiments of the present application has a small pitch and a small size, and can meet the 3D interconnection requirements of future fine pitch bump.

[0160] The microbumps provided in the embodiments of the present application are formed in a similar manner to the microbumps in the above embodiments. For the technical features not detailedly disclosed in the embodiments of the present application, please refer to the above embodiments for understanding, and will not be elaborated here.

[0161] The embodiments of the present application provide a chip interconnection method. Figure 5 As an optional process schematic diagram of the chip interconnection method provided by the embodiments of the present application, as Figure 5 shown, the method includes the following steps:

[0162] Step S501: Provide at least two chips; the chips include through-silicon vias that are open along the first surface of the chip and a dielectric layer located on the second surface of the chip; metal interconnect lines connected to the through-silicon vias are formed in the dielectric layer; the first surface and the second surface are two opposite surfaces of the chip along the thickness direction of the chip.

[0163] In the embodiments of the present application, the chips are chips to be encapsulated. The chips include a silicon substrate and a dielectric layer. The through-silicon vias are formed in the silicon substrate and penetrate through the silicon substrate. Metal interconnect lines are formed in the dielectric layer, and the metal interconnect lines are connected to the through-silicon vias. The through-silicon vias and the metal interconnect lines are jointly used to transmit signals on the first surface of the chip to the second surface of the chip.

[0164] Step S502: Form microbumps on the first surface of the chip at positions corresponding to the through-silicon vias of the chip.

[0165] The microbumps are formed by the method for forming microbumps provided in the above embodiments. For the technical features not detailedly disclosed in the embodiments of the present application, please refer to the above embodiments for understanding.

[0166] In the embodiments of the present application, the chips include at least two through-silicon vias, and a microbump is formed at the corresponding position of each through-silicon via.

[0167] Step S503: Perform ball planting on the exposed surface of the metal interconnect lines in the chip to form bonding bumps on the second surface of the chip.

[0168] In some embodiments, the metal interconnect lines are also used to lead out signals on the second surface of the chip. The bonding bumps are also used to achieve stacking between chips or between a chip and a substrate. Here, the size of the bonding bumps is larger than the size of the microbumps.

[0169] Step S504: Align and bond the microbumps on the first surface of the first chip among the at least two chips with the welding bumps on the second surface of the second chip among the at least two chips, so as to achieve interconnection between the at least two chips through the microbumps.

[0170] In the embodiments of the present application, the interconnection between chips is achieved by face-to-back welding, that is, the first surface of the first chip among at least two chips is in contact with the second surface of the second chip among at least two chips. The interconnection between chips is realized through the alignment and bonding between micro-bumps and bonding bumps.

[0171] For the chip interconnection method provided by the embodiments of the present application, since the micro-bumps formed on the first surface of the chip can achieve small size and small pitch, thus, it can meet the requirements of future 3D interconnection.

[0172] The embodiments of the present application also provide a chip interconnection structure, which includes at least two chips, micro-bumps located on the first surface of each chip, and bonding bumps located on the second surface of each chip. Figure 6 For an optional structural schematic diagram of the chip interconnection structure provided by the embodiments of the present application, as Figure 6 shown, in the embodiments of the present application, the chip interconnection structure 60 includes two stacked chips 601 and 602, micro-bumps 71 located on the first surface of each chip, and bonding bumps 72 located on the second surface of each chip.

[0173] In the embodiments of the present application, the structure of each chip in the chip interconnection structure is the same. Below, the internal structure of the chip will be introduced by taking the chip 601 as an example.

[0174] Please continue to refer to Figure 6 , the chip 601 includes through-silicon vias 6011 and 6012 that are opened along the first surface of the chip (such as the E surface shown in Figure 6 ) and a dielectric layer 6013 located on the second surface of the chip (such as the F surface shown in Figure 6 ); metal interconnect lines 6014 connected to each through-silicon via 6011 and 6012 are formed in the dielectric layer 6013. Among them, the first surface (E surface) and the second surface (F surface) are two opposite surfaces of the chip 601 along the X-axis direction.

[0175] In the embodiments of the present application, the micro-bumps of each chip are connected to the through-silicon vias, and the micro-bumps are formed by the method for forming micro-bumps provided in the above embodiments. And the bonding bumps of each chip are connected to the metal interconnect lines. The micro-bumps on the first surface of the first chip among the at least two chips are electrically connected to the bonding bumps on the second surface of the second chip among the at least two chips.

[0176] It should be noted that in the embodiments of the present application Figure 6 , only two through-silicon vias and two micro-bumps are exemplarily shown. In the actual process, there are multiple through-silicon vias in the chip, and a micro-bump will be formed at the position of each through-silicon via.

[0177] The chip interconnect structure provided by the embodiments of the present application is similar to the chip interconnect method in the above embodiments. For the technical features not disclosed in detail in the embodiments of the present application, please refer to the above embodiments for understanding and will not be elaborated here.

[0178] The chip interconnect structure provided by the embodiments of the present application can meet the requirements of future 3D interconnections because the microbumps formed on the first side of the chip can achieve small size and small pitch.

[0179] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings between the various components shown or discussed are either direct couplings.

[0180] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0181] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0182] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for forming microbumps, characterized in that, the method comprises: providing a chip, the chip at least comprising a silicon substrate and a through-silicon via penetrating the silicon substrate; forming a conductive layer in the through-silicon via, wherein the conductive layer has a first preset size in a first direction, and the first direction is the thickness direction of the silicon substrate; forming a connection layer on the surface of the conductive layer in the through-silicon via; wherein the connection layer has a second preset size in the first direction; the sum of the first preset size and the second preset size is equal to the initial size of the through-silicon via in the first direction; processing the silicon substrate to expose the connection layer and form microbumps corresponding to the through-silicon vias; before forming the conductive layer, the method further comprises: depositing an insulating material on the inner wall of the through-silicon via to form an insulating layer; depositing a barrier material on the surface of the insulating layer to form a barrier layer; depositing a seed material on the surface of the barrier layer to form a seed layer; the insulating layer, the barrier layer and the seed layer are formed on the first surface of the silicon substrate; the method further comprises: after forming the connection layer, performing chemical mechanical polishing on the first surface of the silicon substrate to remove the insulating layer, the barrier layer and the seed layer on the first surface of the silicon substrate; wherein, the processing the silicon substrate to expose the connection layer and form microbumps corresponding to the through-silicon vias comprises: taking the first surface of the silicon substrate as an etching starting point, removing the silicon substrate with the second preset size, and retaining the insulating layer, the barrier layer and the seed layer on the sidewall of the connection layer to expose the connection layer with the second preset size and form microbumps corresponding to the through-silicon vias; or, the processing the silicon substrate to expose the connection layer and form microbumps corresponding to the through-silicon vias comprises: taking the first surface of the silicon substrate as an etching starting point, removing the silicon substrate with the second preset size and the insulating layer, the barrier layer and the seed layer on the sidewall of the connection layer to expose the connection layer with the second preset size and form microbumps corresponding to the through-silicon vias.

2. The method according to claim 1, characterized in that, the forming a conductive layer in the through-silicon via comprises: adopting an electrochemical deposition process to electroplate a conductive material on the surface of the seed layer in the through-silicon via to form the conductive layer; wherein, the conductive material is the same as the seed material.

3. The method according to claim 1, characterized in that, the forming a connection layer on the surface of the conductive layer in the through-silicon via comprises: depositing a welding material on the surface of the conductive layer and the seed layer in the through-silicon via to form the connection layer; wherein, the welding material comprises a nickel-gold conductive material or solder paste.

4. The method according to claim 1, characterized in that, the providing a chip comprises: providing the silicon substrate; taking the first surface of the silicon substrate as an etching starting point, etching the silicon substrate to form the through-silicon via penetrating the silicon substrate; Wherein, the size of the through-silicon via in the second direction is less than 15 microns, and the pitch between two adjacent through-silicon vias is less than 20 microns; the second direction is perpendicular to the first direction.

5. The method according to claim 4, wherein forming the through-silicon via penetrating the silicon substrate includes: forming a first photoresist layer on the first surface of the silicon substrate; patterning the first photoresist layer to form a window that exposes the first surface of the silicon substrate; etching the silicon substrate through the window to form a through-silicon via penetrating the silicon substrate.

6. The method according to claim 1, wherein the chip further includes: a dielectric layer located on the second surface of the silicon substrate; metal interconnect lines connected to the through-silicon vias are formed in the dielectric layer; wherein, the first surface and the second surface of the silicon substrate are two opposite surfaces of the silicon substrate along the first direction; the through-silicon vias and the metal interconnect lines are jointly used to transmit signals on the first surface of the silicon substrate to the second surface of the silicon substrate.

7. The method according to claim 6, wherein the metal interconnect lines located in the dielectric layer are formed by the following method: depositing a dielectric material on the second surface of the silicon substrate to form the dielectric layer; forming a patterned second photoresist layer on the surface of the dielectric layer; etching the dielectric layer through the second photoresist layer to form interconnect holes located in the dielectric layer; filling the interconnect holes with a conductive material to form the metal interconnect lines located in the dielectric layer.

8. The method according to claim 6, wherein the chip further includes a solder pad located on the second surface of the silicon substrate; the first end of the solder pad is connected to the internal circuit of the chip, and the second end of the solder pad is connected to the metal interconnect lines in the dielectric layer; the metal interconnect lines are further used to lead out signals on the second surface of the silicon substrate.

9. A micro-bump, wherein the micro-bump is formed by the method for forming a micro-bump provided in any one of claims 1 to 8 above; the micro-bump is located in the through-silicon via structure of the chip, and the micro-bump is at least used to realize the interconnection between two chips.

10. The micro-bump according to claim 9, wherein the chip includes a through-silicon via penetrating the silicon substrate of the chip; the through-silicon via corresponds to the micro-bump, and the size of the micro-bump in the direction perpendicular to the first direction is less than the size of the through-silicon via in the direction perpendicular to the first direction; wherein, the first direction is the thickness direction of the silicon substrate.

11. The micro-bump according to claim 10, wherein the size of the micro-bump in the second direction is less than 15 microns, and the pitch between two adjacent micro-bumps is less than 20 microns, wherein the second direction is perpendicular to the first direction.

12. A chip interconnection method, wherein the method includes: Provide at least two chips; the chips include through-silicon vias that are open along a first surface of the chip and a dielectric layer located on a second surface of the chip; metal interconnect lines connected to the through-silicon vias are formed in the dielectric layer; the first surface and the second surface are two opposite surfaces of the chip along the thickness direction of the chip; At a corresponding position of the through-silicon via of the chip, micro-bumps located on the first surface of the chip are formed by the method according to any one of claims 1 to 8 above; Ball implantation is performed on an exposed surface of the metal interconnect line in the chip to form bonding bumps located on the second surface of the chip; Align and bond the micro-bumps on the first surface of the first chip among the at least two chips with the bonding bumps on the second surface of the second chip among the at least two chips, so as to achieve interconnection between the at least two chips through the micro-bumps.

13. A chip interconnection structure, characterized in that Comprising: At least two chips; The chips include through-silicon vias that are open along a first surface of the chip and a dielectric layer located on a second surface of the chip; Metal interconnect lines connected to the through-silicon vias are formed in the dielectric layer; the first surface and the second surface are two opposite surfaces of the chip along the thickness direction of the chip; Micro-bumps located on the first surface of the chip, wherein the micro-bumps are connected to the through-silicon vias; the micro-bumps are formed by the method for forming micro-bumps provided by any one of claims 1 to 8 above; Bonding bumps located on the second surface of the chip; wherein the bonding bumps are connected to the metal interconnect lines; The micro-bumps on the first surface of the first chip among the at least two chips are electrically connected to the bonding bumps on the second surface of the second chip among the at least two chips.

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