A method of identifying a leakage path of a transistor and a gate to a body, a storage device

Abstract

The application discloses a method for identifying a transistor gate-to-body leakage path, comprising: obtaining a layout, identifying M0P, V0 and M1 having a connection relationship with a target transistor gate according to a connection relationship between layers, merging the M0P, V0 and M1 to obtain a graph and recording as seed_conn; obtaining a circuit path connected with a body electrode of the target transistor according to a circuit connection relationship in the layout, identifying a circuit path having a connection relationship with the seed_conn in the circuit path and recording as a leakage path of the target transistor gate to the body electrode, and determining that there is a leakage risk. The application also discloses a method for identifying a transistor leakage path, which can comprehensively characterize the leakage risk of the transistor. In addition, the application also discloses a storage device, which can be used to execute instructions of the above-mentioned method for identifying a transistor gate-to-body leakage path.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a method for identifying a transistor and a leakage path from a gate to a body of the transistor, and a storage device. BACKGROUND

[0002] In a semiconductor production process, a test chip is needed to analyze defects in a process flow. In a design process of a test chip based on a product chip in a front-end and middle-end process layer, a via layer and a metal layer (i.e., the aforementioned connection layer, polysilicon connection layer, etc.) of a large number of transistors in the chip are usually connected to a pad, and defects in the process flow are analyzed according to abnormal values of electrical test data.

[0003] In an actual test process, the abnormal values of the electrical test data may not completely come from the process flow defects. For example, there may be a leakage path between a drain, a gate, a source and a body of a transistor, and the existence of the leakage path will interfere with the electrical test data, thereby affecting the analysis result. Therefore, it is necessary to exclude the influence of the leakage path existing in the transistor itself on the test result.

[0004] If detection of whether the transistor leaks or not is performed in the test process, a large amount of time and labor cost will be spent. The prior art is limited in obtaining information of the leakage path in the transistor at the initial stage of chip design, and cannot evaluate the leakage risk degree of the leakage path. Therefore, it is necessary to provide a method for identifying the leakage path of the transistor at the initial stage of chip design, and evaluating the leakage risk of the leakage path. SUMMARY

[0005] In view of the deficiencies of the prior art described above, the purpose of the present application is to provide a method for identifying a leakage path from a gate to a body of a transistor, which can identify the leakage path of a target transistor and the number of the leakage paths, and can evaluate the leakage risk of each leakage path and the overall leakage risk of the target transistor from the gate to the body according to the leakage risk of each leakage path. The present application further provides a storage device, which can perform the method for identifying the leakage path from the gate to the body of the transistor.

[0006] To achieve the above-mentioned part or all of the purposes of the present application, the present application provides the following technical solutions.

[0007] The present application provides a method for identifying a leakage path from a gate to a body of a transistor, comprising the following steps:

[0008] Step one: Obtain a layout, the layout comprising at least a polysilicon connection layer, a via layer, a connection layer and a polysilicon layer; wherein the pattern of the polysilicon connection layer is denoted as M0P, used for connecting the polysilicon layer; the pattern of the connection layer is denoted as M1; the pattern of the via layer is denoted as V0, used for connecting M0 and M1; the M0 comprises M0P and M0A, the pattern of the active region connection layer is denoted as M0A, used for connecting the active region;

[0009] According to the connection relationship between the layers, the M0P, V0 and M1 having the connection relationship with the target transistor gate are identified, the M0P, V0 and M1 are merged to obtain a pattern and denoted as seed_conn;

[0010] Step two: According to the circuit connection relationship in the layout, obtain a circuit path connected with the body electrode of the target transistor, identify the circuit path having the connection relationship with the seed_conn in the circuit path and denoted as the leakage path from the gate electrode to the body electrode of the target transistor, and determine that there is a leakage risk.

[0011] The technical scheme has the beneficial effects that the leakage path from the gate electrode to the body electrode of the transistor can be comprehensively obtained according to the layout information at the early stage of chip design, the number of leakage paths is identified, and the leakage risk of the transistor is evaluated.

[0012] The method for identifying the leakage path from the gate electrode to the body electrode of the transistor further identifies the floating gate and the number thereof through which the leakage path from the gate electrode to the body electrode of the target transistor passes; the floating gate refers to a gate electrode without a connection line externally leading for input / output control.

[0013] The method for identifying the leakage path from the gate electrode to the body electrode of the transistor takes the number of floating gates through which the leakage path from the gate electrode to the body electrode of the target transistor passes as an index to represent the leakage risk of the leakage path, and the less the floating gates through which the leakage path passes, the higher the leakage risk. The technical scheme takes the number of floating gates as an index to evaluate the leakage risk of the leakage path, and quantitatively represents the leakage risk of each leakage path.

[0014] Further, a vector parameter is used to represent the overall leakage risk from the gate electrode to the body electrode of the target transistor, specifically: <m1> ， <m2>, ..., <M i－1 >, <M i >}, where i is a positive integer not less than 1, the <M i > represents the i-th leakage path from the gate to the body of the target transistor, M i The value is the number of floating gates traversed by the i-th leakage path. The beneficial effect of this technical solution is that the vector parameter M intuitively represents the number of leakage paths from the gate to the body of the target transistor, as well as the number of floating gates traversed by each leakage path, i.e., the leakage risk of each leakage path. It reflects the overall leakage risk from the gate to the body of the target transistor from two dimensions: the number of leakage paths and the leakage risk of each leakage path.

[0015] The method for identifying the gate-to-body leakage path of a transistor can also define a parameter m as an indicator characterizing the overall leakage risk, where m represents the minimum number of floating gates traversed in the leakage path from the gate to the body of the i target transistors, i.e., the { <m1> ， <m2>, …, <M i－1 >, <M i} the minimum M i value, representing the number of floating gates that the gate-to-body leakage path with the highest risk of leakage passes through.

[0016] The method of identifying the gate-to-body leakage path of the transistor can also define a parameter n as an index representing the overall risk of leakage, n representing the number of leakage paths that pass through the least number of floating gates among i target transistor gate-to-body leakage paths, i.e. the { <m1> ， <m2>..., <M i－1 >, <M i} the number of occurrences of the minimum value represents the number of the leakage paths with the highest leakage risk.

[0017] The application also provides a method for identifying the leakage paths of a transistor, comprising identifying the leakage paths between the source and the drain of the transistor, the leakage paths from the source and the drain to the body of the transistor, and the leakage paths from the gate to the body of the transistor; wherein the leakage paths from the gate to the body of the transistor are identified by the method for identifying the leakage paths from the gate to the body of the transistor. The technical scheme has the beneficial effects that the method can comprehensively identify the leakage paths between the source and the drain, the leakage paths from the source and the drain to the body, and the leakage paths from the gate to the body of the transistor, and comprehensively characterize the leakage risk of the transistor.

[0018] Further, the method for identifying the leakage paths between the source and the drain of the transistor comprises the following steps: step 1: obtaining a layout, and obtaining the circuit path from the source to the drain (Source to Drain) of a target transistor according to the circuit connection relationship in the layout, denoted as loop_n (n=1, 2, 3,...);

[0019] Step 2: in the loop_n, identify the loop_i (i=1, 2, 3,...) in which there is a floating gate in the circuit path, and determine that the loop_i is the leakage path between the source and the drain of the target transistor, i.e. there is a leakage risk, and the number of floating gates in the loop_i is negatively correlated with the leakage risk. The leakage path refers to the circuit path with a leakage risk.

[0020] Preferably, between step 1 and step 2, there is also a screening step 1.1:

[0021] When there are multiple circuit paths from the source to the drain above the target transistor, the shortest circuit path is screened out and denoted as loop_up_n (n=x);

[0022] When there are multiple circuit paths from the source to the drain below the target transistor, the shortest circuit path is screened out and denoted as loop_down_n (n=x);

[0023] After step 1.1 is performed, the loop_n in step 2 refers to the loop_up_n (n=x) and / or the loop_down_n (n=x).

[0024] In step 2, the leakage risk of the leakage path between the source and the drain of the target transistor is determined according to the loop_i, and the determination is as follows:

[0025] The loop_i is annular, and the middle closed area of the annular loop_i is recorded as loop_holes; define risk parameters n1, n2, n3 and N to represent the electric leakage risk of the loop_i;

[0026] The gate in contact with the loop_holes is recorded as loopgate, and the risk parameter n1 is defined to represent the number of loopgates;

[0027] The gate of the target transistor in the loopgate is recorded as agate_except, and the risk parameter n2 is defined to represent the number of agate_except;

[0028] The controlled gate in the loopgate except the agate_except is recorded as agate_control, which refers to the gate controlled by input / output, and the risk parameter n3 is defined to represent the number of agate_control. Generally, the controlled gate refers to the gate controlled by input / output through the connection line, such as M0P, V0, M1, etc. to the pad;

[0029] The gate in the loopgate except the agate_except and the agate_control is recorded as a floating gate, and the risk parameter N is defined to represent the number of floating gates passed by the loop_i, i.e. N=n1-n2-n3;

[0030] It is determined that the loop_i with N>0 and n3=0 has an electric leakage risk, which is the electric leakage path between the source and drain of the target transistor. The size of N is negatively correlated with the electric leakage risk, i.e. the fewer the number of floating gates, the higher the electric leakage risk.

[0031] Define risk parameters sdleakagepath, sdleakagedummygate_up, sdleakagecontrolgate_up, sdleakagedummygate_down and sdleakagecontrolgate_down to represent the electric leakage risk of the target transistor. Specifically, the sdleakagepath is the sum of n1 values of the electric leakage path between the source and drain of the target transistor, which is used to represent whether there is an electric leakage path between the source and drain of the target transistor, 0 indicating the absence, and other numerical values indicating the presence;

[0032] The sdleakagedummygate_up is the value of N of the electric leakage path between the source and drain above the target transistor, which is used to represent the number of floating gates passed by the electric leakage path between the source and drain above the target transistor;

[0033] The sdleakagecontrolgate_up is the value of n3 of the leakage path between the source and drain above the target transistor, used to represent the number of controlled gates through which the leakage path between the source and drain above the target transistor passes;

[0034] The sdleakagedummygate_down is the value of N of the leakage path between the source and drain below the target transistor, used to represent the number of floating gates through which the leakage path between the source and drain below the target transistor passes;

[0035] The sdleakagecontrolgate_down is the value of n3 of the leakage path between the source and drain below the target transistor, used to represent the number of controlled gates through which the leakage path between the source and drain below the target transistor passes.

[0036] A method for identifying the leakage path from the source and drain to the body of a transistor, comprising the following steps:

[0037] Step 1: Obtain a layout, and according to the circuit connection relationship in the layout, obtain the circuit path from the source to the drain of the target transistor (Source to Drain), denoted as loop_n (n = 1, 2, 3,...), the loop_n is annular, and the middle closed area of the annular loop_n is denoted as loop_holes;

[0038] The gate in contact with the loop_holes is denoted as loopgate;

[0039] The gate of the target transistor in the loopgate is denoted as agate_except;

[0040] The controlled gate in the loopgate except the agate_except is denoted as agate_control; the controlled gate refers to the gate that is controlled for input / output, generally, the controlled gate refers to the gate that is led out for input / output control through a connection line, such as led out to a pad through M0P, V0, M1, etc.

[0041] The gate in the loopgate except the agate_except and the agate_control is denoted as a floating gate;

[0042] Step 2: Cutting with the agate_except and the agate_control, the loop_n is divided into several segments loop_remain, among which the loop_remain in contact with the left side of the agate_except is recorded as loop_lef, and the loop_remain in contact with the right side of the agate_except is recorded as loop_right;

[0043] The connection line for connecting the active region is recorded as M0A;

[0044] The M0A in contact with the loop_left is recorded as M0A_loop_left, and the agate_control in connection with the M0A_loop_left is recorded as agate_sd_left; and the risk parameter n4 is defined to represent the number of agate_sd_left;

[0045] The M0A in contact with the loop_right is recorded as M0A_loop_right, and the agate_control in connection with the M0A_loop_right is recorded as agate_sd_right; and the risk parameter n5 is defined to represent the number of agate_sd_right;

[0046] If n4>0, it is determined that the target transistor has a leakage path from its left (source / drain) to the body;

[0047] If n5>0, it is determined that the target transistor has a leakage path from its right (source / drain) to the body.

[0048] The risk parameters n6 and n7 are also defined to represent the number of floating gates through which the leakage path from the source / drain of the target transistor to the body passes:

[0049] Among the agate_control in contact with the loop_left, the number of agate_control other than the agate_sd_left, agate_sd_right and agate_except, i.e. the number of floating gates through which the leakage path from the left (source / drain) of the target transistor to the body passes, is recorded as the value of n6, and the smaller the value of n6, the higher the risk of leakage;

[0050] The number of agate_control, which is in contact with the loop_right, except for the agate_sd_left, agate_sd_right and agate_except in the agate_control, that is, the number of floating gates through which the leakage path from the right (source / drain) of the target transistor to the body exists, is recorded as the value of n7. The smaller the value of n7, the higher the risk of leakage.

[0051] Preferably, in the step 1, after obtaining the circuit path from the source to the drain of the target transistor, a screening step 1.1 is further performed.

[0052] When there are multiple circuit paths from the source to the drain above the target transistor, the shortest circuit path is screened out and recorded as loop_up_n.

[0053] When there are multiple circuit paths from the source to the drain below the target transistor, the shortest circuit path is screened out and recorded as loop_down_n.

[0054] After performing the step 1.1, the loop_n (n=1, 2, 3...) in the step 1 refers to the loop_up_n and / or the loop_down_n.

[0055] The risk parameters llktoloopgate_up, llktoloopgate_down, rlktoloopgate_up, rlktoloopgate_down are defined, which are respectively used to represent the number of floating gates in the leakage path from the source / drain to the body located above the left, below the left, above the right and below the right of the target transistor, that is, the values of n8, n9, n10 and n11.

[0056] Further, the identification method of the leakage path from the source / drain to the body of the transistor includes the following steps:

[0057] Step one: obtaining a layout, the layout including an active area layer and an active area connection layer, the pattern of the active area layer being an active area, recorded as AA; the pattern of the active area connection layer being an active area connection line, recorded as M0A, used for connecting the active area;

[0058] Step two: along the gate of the target transistor, cutting off the AA where the target transistor is located, and dividing to obtain a plurality of AA sub-regions, the AA sub-regions being recorded as dif_not_seed; according to the connection relationship between the layers, identifying the dif_not_seed that exists connection with the body of the target transistor through the M0A, recorded as err_path1;

[0059] Step three: define the risk parameter c1, which represents the number of err_path1; when c1=0, it is determined that the target transistor does not exist a source / drain to body leakage path; when c1>0, it is determined that the target transistor exists a source / drain to body leakage path.

[0060] By cutting off the active area (AA) where the target transistor is located, find the AA sub-area err_path1 which exists a leakage path (through M0A and the body of the target transistor). If the number of AA sub-areas which exist a leakage path is greater than 0, it is determined that the target transistor exists a source / drain to body leakage path. The source / drain to body leakage path of the target transistor refers to the source / drain to body leakage path, that is, the source to body leakage path and the drain to body leakage path. Here, the so-called leakage path refers to a circuit path which exists a leakage risk.

[0061] According to the circuit connection relationship in the layout, identify the source / drain to body circuit path of the target transistor, denoted as err_path1_hole; and record the floating gate through which the err_path1_hole passes as err_path1_dumgate, where the floating gate refers to a gate which has no connection line for input / output control.

[0062] Define the risk parameter c2, which represents the number of err_path1_hole connected to the err_path1, and define the risk parameter c3, which represents the number of err_path1_dumgate connected to the err_path1; use the risk parameters c1, c2 and c3 to quantitatively represent the leakage risk of the source / drain to body circuit path of the target transistor: when c1>0 and c1=c2, it is indicated that the target transistor exists a source / drain to body leakage path, and the leakage path passes through c3 floating gates, and the smaller the value of c3 is, the higher the risk of the source / drain to body leakage path of the target transistor is; when c1>0 and c1>c2, it is indicated that the target transistor exists a source / drain to body leakage path, and the leakage path is that the source / drain directly connects to the body through M0A without passing through a floating gate, and at this time, the risk of the leakage path is the highest.

[0063] The position of the circuit path of the source / drain electrode of the target transistor to the body is characterized by parameter quantization. The number of the least floating gates in the circuit path of the source / drain electrode of the target transistor to the body on the right side of the target transistor is characterized by parameter quantization, and the number of the circuit paths of the source / drain electrode of the target transistor to the body passing through the least floating gate number on the right side of the target transistor is characterized by parameter quantization. The number of the least floating gates in the circuit path of the source / drain electrode of the target transistor to the body on the left side of the target transistor is characterized by parameter quantization, and the number of the circuit paths of the source / drain electrode of the target transistor to the body passing through the least floating gate number on the left side of the target transistor is characterized by parameter quantization. The information parameters for characterizing the details of the target transistor are increased, which can help the selection of the test transistor in the chip, the analysis of the abnormal values of the transistor test data, and the provision of information for subsequent layout verification.

[0064] The application further provides a storage device, which stores a plurality of instructions.

[0065] Compared with the prior art, the application has the following beneficial effects:

[0066] 1. The method for identifying the gate-to-body leakage path of a transistor provided by the application obtains the gate-to-body leakage path of a target transistor according to layout information, and uses the number of floating gates passed by the leakage path as an index for evaluating the leakage risk of the leakage path, thereby quantitatively characterizing the leakage risk of each leakage path.

[0067] 2. The method for identifying the leakage path of a transistor provided by the application can comprehensively identify the leakage paths between the source and drain electrodes, between the source and drain electrodes and the body, and between the gate and the body of a transistor, and comprehensively characterize the leakage risk of the transistor.

[0068] 3. The application can comprehensively extract the leakage path of the source / drain electrode to the body of a transistor, and use the number of floating gates passed by the leakage path as an important index for evaluating the risk degree of the leakage path, thereby quantitatively characterizing the risk degree of the leakage path, helping the selection of a test transistor in a chip and the analysis of abnormal values of transistor test data. The application can be automatically applied to the extraction of the leakage path of the source / drain electrode to the body of a transistor in a layout file, and automatically generate a risk prompt, which is helpful for the design program of a test chip.

[0069] 4、The application can comprehensively extract the leakage path between the source and the drain and the leakage path from the source and the drain to the body due to the circuit path between the source and the drain, and extract the number of controlled gates and the number of floating gates in the leakage path as important indexes for evaluating the risk degree of the leakage path, quantitatively represent the risk degree of the leakage path, so as to help select the test transistor in the chip and analyze the abnormal value of the transistor test data. BRIEF DESCRIPTION OF DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the specific embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings described below are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0071] Figure 1 is a flowchart of a method for identifying the leakage path from the gate to the body of a transistor according to an embodiment of the application;

[0072] Figure 2 is a schematic diagram of seed_conn of a target transistor in an embodiment of the application;

[0073] Figure 3 is Figure 2 is an enlarged view of A in FIG.

[0074] Figure 4 and Figure 5 is a schematic diagram of a method for identifying the leakage path between the source and the drain of a transistor according to embodiment 3 of the application.

[0075] Figure 6 and Figure 7 is a schematic diagram of a method for identifying the leakage path from the source and the drain to the body of a transistor according to embodiment 4 of the application.

[0076] Figure 8 is a flowchart of a method for identifying the leakage path from the source and the drain to the body of a transistor according to embodiment 6 of the application.

[0077] Figure 9 is a leakage path from the source and the drain to the body according to embodiment 7 of the application.

[0078] Figure 10 is a leakage path from the source and the drain to the body according to embodiment 7 of the application.

[0079] Figure 11 is a leakage path from the source and the drain to the body according to embodiment 8 of the application. DETAILED DESCRIPTION

[0080] The technical solutions in the specific embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work belong to the protection scope of the present application.

[0081] Embodiment 1

[0082] Figure 1 is a method flow diagram in an embodiment of the present application, please refer to Figure 1 The embodiment discloses a method for identifying a leakage path from a transistor gate to a body, comprising the following steps:

[0083] Step 1: Obtain a layout, the layout at least comprising a polysilicon connection layer, a via layer, a connection layer and a polysilicon layer; wherein the pattern of the polysilicon connection layer is denoted as M0P, used for connecting the polysilicon layer; the pattern of the connection layer is denoted as M1; the pattern of the via layer is denoted as V0, used for connecting M0 and M1; the M0 comprises M0P and M0A, the pattern of the active area connection layer is denoted as M0A, used for connecting the active area;

[0084] According to the connection relationship between the layers, the M0P, V0 and M1 having the connection relationship with the target transistor gate are identified, the M0P, V0 and M1 are combined to obtain a pattern and denoted as seed_conn;

[0085] Step 2: According to the circuit connection relationship in the layout, obtain a circuit path connected with the body of the target transistor, identify the circuit path having the connection relationship with the seed_conn in the circuit path and denoted as the leakage path from the gate to the body of the target transistor, and determine that there is a leakage risk.

[0086] Figure 2 is a schematic diagram of the seed_conn of the target transistor in an embodiment of the present application, Figure 3 is Figure 2 is an enlarged view of A in Figure 2 and Figure 3 The method for identifying the leakage path from the transistor gate to the body provided by the present application will be described in detail:

[0087] In the embodiment, M0P, M1 and V0 connected with the target transistor gate in the layout information are identified, the M0P, V0 and M1 are combined to obtain a graph and recorded as seed_conn; according to the circuit connection relationship in the layout, a circuit path connected with the target transistor body is obtained, the circuit path connected with the seed_conn in the circuit path is identified and recorded as the leakage path of the target transistor gate to the body, it is determined that there is a leakage risk, and the leakage path is defined as err_dio1_hole. In the embodiment, the graph of the polysilicon connection layer (M0P) is a metal connection line for connecting the polysilicon layer; the graph of the connection layer (M1) is a connection line; and the graph of the via layer (V0) is a via for connecting M0 and M1, wherein M0 includes M0P and M0A, and M0A is the graph of the active area connection layer for connecting the active area.

[0088] The floating gate on the err_dio1_hole and the number of floating gates are identified, the floating gate connected with the err_dio1_hole is set as err_dio1_dumgate, and the number of floating gates passed by each err_dio1_hole is taken as an index to represent the leakage risk of the err_dio1_hole. As shown in FIG. 6, the number of err_dio1_hole connected with the seed_conn is 3, the number of err_dio1_dumgate connected with two err_dio1_hole is 1, that is, the two leakage paths pass through 1 floating gate, and the number of err_dio1_dumgate connected with the other err_dio1_hole is 3, that is, the leakage path passes through 3 floating gates. The leakage path passing through the least floating gate is the leakage path with the highest leakage risk, and in the embodiment, the two leakage paths passing through the floating gate with the number of 1 are determined as the leakage paths with the highest leakage risk. Figure 3

[0089] Further, the vector parameter is set as <m1> ， <m2><1>, <2>, <3>, …, <M i－1 <1>, <2>, <3>, …, <M i} represents the overall leakage risk of the target transistor gate-to-body, i is a positive integer not less than 1, the <M i <1>, <2>, <3>, …, <M i The value of the <M In this embodiment, the vector parameter is {<1>, <1>, <3>}, which can reflect the number of err_dio1_hole and err_dio1_dumgate in the target transistor at the same time, thereby quantitatively characterizing the overall leakage risk of the target transistor.

[0090] Define parameters m and n, where m represents the number of floating gates passed by the leakage path with the highest leakage risk among the i target transistor gate-to-body leakage paths, and n represents the number of leakage paths with the highest leakage risk among the i target transistor gate-to-body leakage paths. The vector format parameter is saved in the seed_conn in the form of {<1>, <1>, <3>}. When this parameter is passed into the gate of the target device connected with the seed_conn, each array element in the vector format parameter can be traversed, and the minimum value m=1 in the array element and the number of times n=2 that the minimum value appears in the array element are recorded. The values of the parameters m and / or n can be used as a basis for quantitatively characterizing the overall leakage risk of the target transistor gate-to-body leakage path.

[0091] The application further provides a storage device having a plurality of instructions stored therein, which are loaded and executed by a processor, and the instructions include the method for identifying the transistor gate-to-body leakage path in the above technical solution.

[0092] Embodiment 2

[0093] The application further provides a method for identifying a transistor leakage path, which includes identifying: a leakage path between the source and drain of a transistor, a leakage path from the source and drain of a transistor to a body, and a leakage path from the gate of a transistor to a body; wherein the leakage path from the gate of a transistor to a body is implemented by using the method for identifying the leakage path from the gate of a transistor to a body.

[0094] Embodiment 3

[0095] In combination Figure 4 and Figure 5 As shown in the embodiment of the method for identifying the leakage path between the source and the drain of the transistor, step 1: obtaining a layout, and according to the circuit connection relationship between layers in the layout, obtaining the circuit path from the source to the drain of the target transistor, denoted as loop_n, in this embodiment, there are loop_1 and loop_2; step 2: in the loop_n, identify the loop_n in which the floating gate exists in the circuit path, denoted as loop_i, (such as Figure 4 determining that the loop_i is the leakage path between the source and the drain of the target transistor, i.e., there is a risk of leakage, and the number of floating gates in the loop_i is negatively correlated with the risk of leakage.

[0096] Performing the screening step 1.1, and screening the shortest circuit path above the target transistor, denoted as loop_up_i, and screening the shortest circuit path above the target transistor, denoted as loop_down_i.

[0097] As shown in step two, according to the loop_i, the risk of leakage of the leakage path between the source and the drain of the target transistor is determined, and the specific steps are as follows: Figure 5

[0098] After the loop_i is dug, the intermediate loop_holes are obtained, all gates are defined as agate, all gates in contact with the loop_holes are defined as loopgate, the loopgate in contact with the target transistor gate (G) is defined as agate_except, and the loopgate in contact with the leakage path control gate (controlgate) of the target transistor is defined as agate_control. The number n1 / n2 / n3 of loopgate / agate_except / agate_control in contact with the loop_holes is transmitted as a parameter into the gate pattern of the target transistor, (n1-n2-n3) represents the number of floating gates in the leakage path of the target transistor Source to Drain, n3 represents the number of controlled gates in the leakage path of the target transistor Source to Drain, when ((n1-n2-n3)>0) and (n3=0), it is proved that the target transistor has a Source to Drain leakage path and no controlled gate is connected out, which is easy to cause abnormal test data. And the smaller the value of (n1-n2-n3) is, the fewer the number of floating gates in the Source to Drain leakage path is, and the higher the risk of leakage is.

[0099] Setting a parameter to represent the risk degree of the Source to Drain leakage path of the target transistor:​

[0100] sdleakagepath indicates whether there is a Source to Drain leakage path for the target transistor, 0 indicates that there is no leakage path, and other values indicate that there is a leakage path. In this embodiment, sdleakagepath = 2.

[0101] sdleakagedummygate_up indicates the number of floating gates passed in the Source to Drain leakage path above the target transistor. In this embodiment, sdleakagedummygate_up = 4.

[0102] sdleakagecontrolgate_up indicates the number of control gates in the Source to Drain leakage path above the target transistor. In this embodiment, sdleakagecontrolgate_up = 1.

[0103] sdleakagedummygate_down indicates the number of floating gates passed in the Source to Drain leakage path below the target transistor. In this embodiment, sdleakagedummygate_down = 0.

[0104] sdleakagecontrolgate_down indicates the number of control gates in the Source to Drain leakage path below the target transistor. In this embodiment, sdleakagecontrolgate_down = 0.

[0105] A storage device stores a plurality of instructions, which are suitable for being loaded and executed by a processor to perform the above-mentioned method of identifying a leakage path between source and drain of a transistor.

[0106] Embodiment 4

[0107] In combination Figure 6 and In combination with the specific implementation of the method of identifying a leakage path between source and drain of a transistor as shown in Figure 7 Step 1: Obtain a layout, and according to the circuit connection relationship in the layout, obtain a circuit path from the source to the drain of the target transistor (Source to Drain), denoted as loop_n (n = 1, 2, 3,...), the loop_n is annular, as shown in Figure 7 The middle closed area of the annular loop_n is denoted as loop_holes;

[0108] The gate in contact with the loop_holes is recorded as loopgate;

[0109] The gate of the target transistor in the loopgate is recorded as agate_except;

[0110] The controlled gate in the loopgate except the agate_except is recorded as agate_control; the controlled gate refers to the gate for input / output control, generally, the controlled gate refers to the gate for input / output control led out through the connection line, such as led out to the pad through the connection line of M0P, V0, M1, etc.

[0111] The gate in the loopgate except the agate_except and the agate_control is recorded as a floating gate;

[0112] Step 2: disconnect the loop_n from the agate_except and the agate_control to obtain the loop_remain, define the loop_remain intersecting with the left side of the agate_except as loop_left, and define the loop_remain intersecting with the right side of the agate_except as loop_right. Define the M0A cluster intersecting with the loop_left as M0A_loop_left, and the agate_control having a connection relationship with it as agate_sd_left. Define the M0A cluster intersecting with the loop_right as M0A_loop_right, and the agate_control having a connection relationship with it as agate_sd_right. The number n4 / n5 of the agate_sd_left / agate_sd_right in contact with the loop_holes is transmitted as a parameter into the gate of the target transistor, (n4>0) proves that there is a leakage path from the controlled gate to the left Source / Drain of the gate of the target transistor, (n5>0) proves that there is a leakage path from the controlled gate to the right Source / Drain of the gate of the target transistor. At the same time, the number n6 / n7 of the (agate NOT (OR agate_sd_left agate_sd_right agate_except)) intersecting with the loop_left / loop_right is the number of floating gates through which the leakage path from the controlled gate to the left / right Source / Drain of the target transistor. Since the Body of the target transistor is connected with the leakage path controlled gate during the test, it is equivalent to the existence of the leakage path from the Source / Drain to the Body, which is easy to cause abnormal test data.

[0113] Preferably, in the step 1, after the circuit path (Source to Drain) from the source to the drain of the target transistor is obtained, a screening step 1.1 is further performed:

[0114] When there are multiple circuit paths (Source to Drain) above the target transistor, the shortest circuit path is screened out and marked as loop_up_n.

[0115] When there are multiple circuit paths (Source to Drain) below the target transistor, the shortest circuit path is screened out and marked as loop_down_n.

[0116] After the step 1.1 is performed, the loop_n (n = 1, 2, 3,...) in the step 1 refers to the loop_up_n and / or the loop_down_n.

[0117] The risk parameters llktoloopgate_up, llktoloopgate_down, rlktoloopgate_up and rlktoloopgate_down represent the risk degree of the leakage path of the target transistor, specifically, llktoloopgate_up represents the number of floating gates + 1 in the leakage path from the Source / Drain to the control gate (controlled gate) on the left side of the gate of the target transistor in the Source to Drain leakage path above the target transistor, and 0 represents the absence. In this embodiment, llktoloopgate_up = 1.

[0118] llktoloopgate_down represents the number of floating gates + 1 in the leakage path from the Source / Drain to the control gate (controlled gate) on the left side of the gate of the target transistor in the Source to Drain leakage path below the target transistor, and 0 represents the absence. In this embodiment, llktoloopgate_down = 0.

[0119] rlktoloopgate_up represents the number of floating gates + 1 in the leakage path from the Source / Drain to the control gate (controlled gate) on the right side of the gate of the target transistor in the Source to Drain leakage path above the target transistor, and 0 represents the absence. In this embodiment, rlktoloopgate_up = 0.

[0120] rlktoloopgate_down represents the number of floating gates + 1 in the Source / Drain to controlgate (controlled gate) leakage path on the right side of the target transistor gate in the lower Source to Drain leakage path of the target transistor, and 0 represents the absence of the leakage path. In the present embodiment, rlktoloopgate_down = 0.

[0121] A storage device stores a plurality of instructions adapted to be loaded by a processor and execute the above-mentioned method of identifying the leakage path between the source and drain of a transistor.

[0122] Embodiment 5

[0123] A storage device, in combination with Embodiment 3 and Embodiment 4, stores a plurality of instructions adapted to be loaded by a processor and execute the above-mentioned method of identifying the leakage path between the source and drain of a transistor and the method of identifying the leakage path from the source and drain to the body of a transistor.

[0124] Embodiment 6

[0125] A method of identifying the leakage path from the source and drain to the body of a transistor is provided, referring to Figure 8 , comprising the following steps:

[0126] Step 1: Obtain a layout, which includes an active area layer and an active area connection layer. The pattern of the active area layer is an active area, denoted as AA. The pattern of the active area connection layer is an active area connection line, denoted as M0A, which is used to connect the active area AA.

[0127] Step 2: Along the gate of the target transistor, cut off the active area AA where the target transistor is located, and divide to obtain a plurality of AA sub-regions, denoted as dif_not_seed. That is, the active area AA is cut off from the gate of the target transistor to obtain dif_not_seed. According to the connection relationship between layers, identify the dif_not_seed where the target transistor exists, which is defined as err_path1, through the connection relationship between M0A (active area connection line) and the Body (body) of the target transistor.

[0128] Step three: According to the circuit connection relationship in the layout, the Source / Drain to Body circuit path of the target transistor is identified, and the Source / Drain to Body circuit path is defined as err_path1_hole. According to the circuit connection relationship in the layout, the floating gate in contact with the err_path1_hole is identified, and the floating gate passed by the err_path1_hole is recorded as err_path1_dumgate. The floating gate refers to the gate without connection line external input / output control.

[0129] The err_path1, err_path1_hole, and err_path1_dumgate are bundled as parameters and input into the gate of the target device, i.e., the target transistor, connected to the err_path1. Three risk parameters are defined to quantify the risk degree of the existence of the source / drain to body leakage path of the target transistor. The number of err_path1 connected to the gate of the target transistor is recorded as c1, the number of err_path1_hole connected to the err_path1 is recorded as c2, and the number of err_path1_dumgate connected to the err_path1 is recorded as c3.

[0130] When c1=0, it means that the target transistor has no Source / Drain to Body leakage path.

[0131] When c1>0 and c1=c2, it means that the target transistor has a Source / Drain to body leakage path, and the leakage path passes through c3 floating gates. At this time, the smaller the value of c3, the higher the risk of the source / drain to body leakage path of the target transistor.

[0132] When c1>0 and c1>c2, it means that the target transistor has a Source / Drain to body leakage path, and the leakage path is Source / Drain directly connected to Body through M0A (active area connection line) without passing through floating gate. At this time, the risk of the leakage path is the highest.

[0133] According to the combination of different parameters, it can be judged whether the Source / Drain to Body leakage path exists and its risk, and the risk degree of the leakage path is quantitatively characterized, which can help to select the test transistor in the chip, so as to analyze the abnormal value of the subsequent transistor test result data.

[0134] Example 7

[0135] As Figure 9 and Figure 10 The setting parameter represents the risk degree of the leakage path of the source / drain to body of the target transistor (as shown in the figure Figure 9 And Figure 10 The body) of the target transistor:

[0136] The position of the circuit path of the source / drain to body of the target transistor is quantitatively represented by the parameter, which can be divided into the circuit path on the left side of the gate of the target transistor and the circuit path on the right side of the gate of the target transistor. Lblkpath represents the number of Source / Drain to Body circuit paths on the left side of the gate of the target transistor, and 0 represents that there is no such path. In this embodiment, lblkpath=1.

[0137] Lblk_mindumgate represents the number of floating gates through which the circuit path of the source / drain to body on the left side of the gate of the target transistor passes. In this embodiment, there is only one Source / Drainto Body circuit path on the left side of the gate of the target transistor, and the number of floating gates through which the circuit path passes is 3, and lblk_mindumgate=3.

[0138] Lblk_mindumgatepath represents the number of circuit paths through which the circuit path of the source / drain to body on the left side of the gate of the target transistor passes. In this embodiment, lblk_mindumgatepath=1.

[0139] Rblkpath represents the number of Source / Drain to Body circuit paths on the right side of the gate of the target transistor, and 0 represents that there is no such path. In this embodiment, rblkpath=0.

[0140] Rblk_mindumgate represents the number of floating gates through which the circuit path of the source / drain to body on the right side of the gate of the target transistor passes. In this embodiment, there is no Source / Drain to Body circuit path on the right side of the gate of the target transistor, and rblk_mindumgate=0.

[0141] Rblk_mindumgatepath represents the number of circuit paths through which the circuit path of the source / drain to body on the right side of the gate of the target transistor passes. In this embodiment, rblk_mindumgatepath=0.

[0142] That is, through the above quantitative parameter setting, the risk situation of the source / drain to body leakage path of the target transistor of embodiment 7 is specifically characterized.

[0143] Embodiment 8

[0144] As shown in Figure 11 , the setting parameter characterizes the risk of the source / drain to body leakage path of the target transistor: Figure 11

[0145] The position of the circuit path of the source / drain to body of the target transistor is quantitatively characterized by the parameter. It can be divided into the circuit path on the left side of the gate of the target transistor and the circuit path on the right side of the gate of the target transistor. lblkpath represents the number of Source / Drain to Body circuit paths on the left side of the gate of the target transistor, and 0 represents the absence. In this embodiment, lblkpath=0.

[0146] lblk_mindumgate represents the number of floating gates through which the circuit path of Source / Drain to Body on the left side of the gate of the target transistor passes. In this embodiment, there is no Source / Drain to Body circuit path on the left side of the gate of the target transistor, and lblk_mindumgate=0.

[0147] lblk_mindumgatepath represents the number of circuit paths through which the number of floating gates passing through the Source / Drain to Body circuit path on the left side of the gate of the target transistor is the least. In this embodiment, lblk_mindumgatepath=0.

[0148] rblkpath represents the number of Source / Drain to Body circuit paths on the right side of the gate of the target transistor, and 0 represents the absence. In this embodiment, rblkpath=1.

[0149] rblk_mindumgate represents the number of floating gates through which the circuit path of Source / Drain to Body on the right side of the gate of the target transistor passes. In this embodiment, there is only one Source / Drain to Body circuit path on the right side of the gate of the target transistor, and rblk_mindumgate=1.

[0150] ​rblk_mindumgatepath represents the number of circuit paths that pass through the least number of floating gates in the circuit path from the Source / Drain to the Body on the right side of the gate of the target transistor. In this embodiment, rblk_mindumgatepath = 1.

[0151] That is, through the above quantitative parameter setting, the risk of the source / drain to body leakage path of the target transistor of embodiment 8 is specifically characterized.

[0152] Embodiments 7 and 8 are directed to the identification of the source / drain to body leakage path of the target transistor of the same layout obtained. The risk of the source / drain to body leakage path of the target transistor of embodiment 7 is less than that of the target transistor of embodiment 8.

[0153] The embodiment provides a storage device, wherein a plurality of instructions are stored in the storage device, and the instructions are suitable for being loaded and executed by a processor to execute the method for identifying the source / drain to body leakage path of the transistor provided in the above embodiments.

[0154] The above embodiments are only used to help understand the method and core idea of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present application. < / m1> ​ < / m1> < / m1> < / m1>

Claims

1. A method of identifying a transistor gate-to-body leakage path, comprising: The method comprises the following steps: Step one: obtaining a layout, the layout comprising at least a polysilicon connection layer, a via layer, a connection layer and a polysilicon layer; wherein the pattern of the polysilicon connection layer is denoted as M0P, used for connecting the polysilicon layer; the pattern of the connection layer is denoted as M1; the pattern of the via layer is denoted as V0, used for connecting M0 and M1; the M0 comprises M0P and M0A, the pattern of the active region connection layer is denoted as M0A, used for connecting the active region; According to the connection relationship between the layers, the M0P, V0 and M1 having the connection relationship with the target transistor gate are identified, and the M0P, V0 and M1 are combined to obtain a pattern and denoted as seed_conn; Step two: according to the circuit connection relationship in the layout, the circuit path connected with the body electrode of the target transistor is obtained, the circuit path having the connection relationship with the seed_conn in the circuit path is identified and denoted as the leakage path of the target transistor gate to the body electrode, and it is determined that there is a leakage risk; The floating gate and the number of the floating gate through which the leakage path of the target transistor gate to the body electrode passes are also identified, the floating gate refers to the gate without connection line external lead for input / output control; the number of the floating gate through which the leakage path of the target transistor gate to the body electrode passes is taken as an index to represent the leakage risk of the leakage path, and the fewer the floating gates through which the leakage path passes, the higher the leakage risk.

2. The method of identifying a gate-to-body leakage path of a transistor of claim 1, wherein, The vector parameter is used to represent the overall leakage risk of the target transistor gate to the body electrode, specifically: Definition of vector parameters <m1> ， <m2>..., <M1-1>, }, wherein i is a positive integer not less than 1, and the For the i-th leakage path of the target transistor gate to the body electrode, the value of Mi is the number of the floating gates through which the i-th leakage path passes. < / m1> 3. The method of identifying a gate-to-body leakage path of a transistor of claim 2, wherein, The parameter m is defined as an indicator representing the overall leakage risk, m representing the number of least floating gates passed in the i target transistor gate-to-body leakage paths, i.e. the <m1> ， <m2>< M1-1>,..., The minimum value of Mi in the above formula represents the number of the floating gates through which the leakage path with the highest leakage risk passes. < / m1> 4. The method of identifying a gate-to-body leakage path of a transistor of claim 3, wherein, The parameter n is defined as an indicator representing the overall leakage risk, n representing the number of leakage paths with the least number of floating gates among i target transistor gate-to-body leakage paths, i.e. the <m1> ， <m2>..., <M1-1>, The number of times that the minimum value of Mi appears in the above formula represents the number of the leakage paths with the highest leakage risk. < / m1> 5. A method of identifying a leakage path of a transistor, the method comprising: The method comprises identifying the leakage paths between the source and the drain of the transistor, the leakage paths from the source and the drain of the transistor to the body electrode and the leakage paths from the gate of the transistor to the body electrode; wherein the leakage paths from the gate of the transistor to the body electrode are realized by the method for identifying the leakage paths from the gate of the transistor to the body electrode according to any one of claims 1 to 4.

6. A storage device having stored therein a plurality of instructions, the instructions being loaded and executed by a processor, characterized in that, The instructions comprise the method for identifying the leakage paths from the gate of the transistor to the body electrode according to any one of claims 1 to 4.

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