Method for reducing source-drain short and static random access memory

Abstract

The application discloses a method for reducing source-drain short circuit and a static random access memory, which can reduce the risk of bridge connection and short circuit between adjacent transistor source-drain, and can improve the semiconductor device density in the unit area of integrated circuit. The method comprises the following steps: providing a substrate, the substrate is distributed with first trench isolation regions arranged at intervals, and the substrate and the top of the first trench isolation regions are deposited with a body silicon layer, an OPL layer, an anti-reflection layer and a photoresist layer distributed in sequence from bottom to top; etching the middle part of the OPL layer to obtain an etching groove, removing the photoresist layer, depositing a first etching layer in the etching groove and on the top of the anti-reflection layer, depositing a second etching layer on the top of the first etching layer, removing part of the first etching layer and the second etching layer above the OPL layer and in the etching groove to obtain an isolation layer, the width of the isolation layer is equal to the minimum distance between the source-drain of adjacent two transistors, and the OPL layer on both sides of the isolation layer is removed to make the body silicon layer on both sides of the isolation layer grow into source-drain.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and particularly to a method for reducing source-drain short circuit and a static random access memory prepared by using the method. BACKGROUND

[0002] With the development of semiconductor technology, the density of semiconductor devices in unit area of integrated circuit is increasing, and the physical size of semiconductor devices is continuously reduced, but the risk of short circuit between adjacent semiconductors increases. For example, in the preparation of transistors distributed adjacent to each other in an integrated circuit, due to the limitation of processing technology, it is easy to cause bridging between the source and drain of adjacent transistors due to the close distance, and the bridging is easy to cause short circuit between the source and drain of adjacent MOS transistors. The commonly used method to reduce the source-drain short circuit is to reduce the size of the active area of the MOS transistor to leave sufficient space or to improve the epitaxial growth process, but with the continuous reduction of the physical size of semiconductor devices, the process of reducing the size of the active area or the epitaxial growth process has reached the technical limit. How to further improve the processing technology to reduce the short circuit between the source and drain of adjacent MOS transistors has become a problem to be solved by those skilled in the art. SUMMARY

[0003] In view of the above problems existing in the prior art, the present application provides a method for reducing source-drain short circuit, which can reduce the risk of short circuit caused by bridging between the source and drain of adjacent transistors, and can increase the density of semiconductor devices in unit area.

[0004] To achieve the above-mentioned purpose, the present application adopts the following technical scheme:

[0005] A method for reducing source-drain short circuit, the method comprising the following steps: S1, providing a substrate, the substrate being provided with first trench isolation regions arranged at intervals, and a bulk silicon layer, an OPL layer, an anti-reflection layer and a photoresist layer being sequentially deposited on the top end of the substrate and the first trench isolation regions from bottom to top;

[0006] S2, etching the middle part of the OPL layer by using a photolithography process to obtain an etching groove;

[0007] S3, removing the photoresist layer to expose the top end of the anti-reflection layer;

[0008] S4, depositing a first etching layer on the inner surface of the etching groove and the top end of the anti-reflection layer;

[0009] S5, depositing a second etching layer on the top end of the first etching layer;

[0010] S6, etching the first etching layer and the second etching layer by using a photolithography process, removing the first etching layer and the second etching layer above the OPL layer, and removing part of the first etching layer and the second etching layer inside the etching groove, to obtain an isolation layer, wherein the width of the isolation layer is equal to the minimum distance between the source and the drain of two adjacent transistors;

[0011] S7, removing the OPL layer on both sides of the isolation layer;

[0012] S8, growing the source and the drain on both sides of the isolation layer from the bulk silicon layer.

[0013] Further features are,

[0014] The photoresist layer comprises a first photoresist layer and a second photoresist layer arranged adjacent to each other, and a gap is arranged between the first photoresist layer and the second photoresist layer, wherein the width of the gap is equal to the minimum distance between the source and the drain of two adjacent transistors in an integrated circuit.

[0015] The width of the etching groove is equal to the width of the gap, and the width of the gap and the width of the etching groove are both 30nm-46.3nm.

[0016] The material of the first etching layer is SiN, and the thickness of the first etching layer is

[0017] The material of the second etching layer is SiO2, and the thickness of the second etching layer is

[0018] The isolation layer comprises the first etching layer and the second etching layer, and the thickness of the isolation layer is

[0019] The material of the source and the drain is germanium silicon (SiGe).

[0020] A static random access memory comprises at least two adjacent transistors, and each of the transistors comprises a source and a drain, characterized in that the isolation layer is arranged between the source and the drain of two adjacent transistors, and the isolation layer is prepared by using the above method for reducing short circuit of the source and the drain.

[0021] Further features are,

[0022] The minimum width between the source and the drain of two adjacent transistors is 30.3nm, and the maximum width is 46.3nm.

[0023] The transistor is a planar transistor or a fin field effect transistor.

[0024] The method for reducing source-drain short circuit of the application has the following beneficial effects: the isolation layer is prepared before the growth of the source-drain, and the source-drain is grown on both sides of the isolation layer, so that the bridging during the growth of the source-drain can be effectively avoided, and the risk of short circuit between the source-drains of the adjacent transistors is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is an enlarged view of the existing source-drain of two adjacent transistors under a microscope.

[0026] Figure 2 It is a distribution structure of two adjacent transistors in the existing integrated circuit.

[0027] Figure 3 It is a flow chart of the method for reducing source-drain short circuit of the application.

[0028] Figure 4 It is a front view structural schematic diagram of the distribution of the first trench isolation region, the bulk silicon layer, the OPL layer, the anti-reflection layer and the photoresist layer in step S1 of the method for reducing source-drain short circuit of the application.

[0029] Figure 5 It is a front view structural schematic diagram after the photoresist layer is removed in step S3 of the method for reducing source-drain short circuit of the application.

[0030] Figure 6 It is a front view structural schematic diagram after the first etching layer is deposited in step S4 of the method for reducing source-drain short circuit of the application.

[0031] Figure 7 It is a front view structural schematic diagram after the second etching layer is deposited in step S5 of the method for reducing source-drain short circuit of the application.

[0032] Figure 8 It is a front view structural schematic diagram after part of the first etching layer and the second etching layer are removed in step S6 of the method for reducing source-drain short circuit of the application.

[0033] Figure 9 It is a front view structural schematic diagram after the OPL layer is removed in step S7 of the method for reducing source-drain short circuit of the application.

[0034] Figure 10 It is a front view structural schematic diagram after the source-drain is grown in step S8 of the method for reducing source-drain short circuit of the application. DETAILED DESCRIPTION

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product or device.

[0037] Figure 1 , Figure 2 It provides the distribution structure of two adjacent transistors in existing integrated circuits, from Figure 1 As can be seen, the minimum spacing between the source and drain electrodes of two adjacent transistors is 30.3 nm, and the maximum is 46.3 nm. Due to the limitations of the fabrication process, bridging and short circuits easily occur between the source and drain electrodes of the grown adjacent transistors. The closer the distance between the source and drain electrodes of adjacent transistors, the greater the risk of short circuits, which limits the increase in semiconductor device density per unit area of ​​integrated circuits. Currently, common methods to reduce short circuits between the source and drain electrodes of adjacent transistors include active region size reduction processes or epitaxial growth processes, but these two methods have relatively complex fabrication processes and are approaching their technological limits.

[0038] To address the problem of reducing source-drain short circuits between adjacent transistors in integrated circuits through further improvements in processing technology, the following is a specific embodiment of a method for reducing source-drain short circuits. This method includes the following steps: S1, providing a substrate 1 (PR), on which spaced-apart first trench isolation regions 2 (STI) are distributed. At the top of the substrate 1 and the first trench isolation regions 2, a bulk silicon layer 3, an OPL layer 4, an anti-reflection layer 5, and a photoresist layer are deposited sequentially from bottom to top. (Refer to...) Figure 4 The photoresist layer includes a first photoresist layer 61 and a second photoresist layer 62 arranged adjacent to each other. A gap 7 is provided between the first photoresist layer 61 and the second photoresist layer 62. The width of the gap 7 is equal to the minimum distance between the source and drain electrodes 10 of two adjacent transistors in the integrated circuit.

[0039] S2, etching the middle part of the OPL layer 4 by using a photolithography process to obtain an etching groove 8. The anti-reflection layer 5 and the photoresist layer 61 / 62 constitute a mask. When the OPL layer 4 is etched by using the photolithography process, the light passes through the gap 7 between the first photoresist layer 61 and the second photoresist layer 62 to etch the anti-reflection layer 5 and the OPL layer 4 below, and the width of the etching groove 8 is equal to the width of the gap 7. The width of the gap 7 and the width of the etching groove 8 are both 30 nm to 46.3 nm, and 39 nm is preferred in this embodiment. The gap is flexibly set according to the minimum distance between the source / drain electrodes 10 of two adjacent transistors.

[0040] S3, placing the substrate in a photoresist remover to remove the first photoresist layer 61 and the second photoresist layer 62, so that the upper surface of the remaining anti-reflection layer 5 is exposed, as shown in FIG. 4. Figure 5 .

[0041] S4, depositing a first etching layer 91 on the inner surface of the etching groove 8 and the upper surface of the anti-reflection layer 5 by using an atomic layer deposition method, as shown in FIG. 5. Figure 6 The material of the first etching layer 91 is SiN, and the thickness is

[0042] S5, depositing a second etching layer 92 on the upper surface of the first etching layer 91 by using an atomic layer deposition method, as shown in FIG. 6. Figure 7 The material of the second etching layer is SiO2, and the thickness is

[0043] S6, etching the first etching layer 91 and the second etching layer 92 by using a photolithography process to remove the first etching layer 91 and the second etching layer 92 above the OPL layer 4, and remove part of the first etching layer 91 and the second etching layer 92 inside the etching groove 8 to obtain an isolation layer 11. The width of the isolation layer 11 is equal to the minimum distance between the source / drain electrodes 10 of two adjacent transistors. The isolation layer 11 includes the first etching layer and the second etching layer. In this embodiment, the thickness of the isolation layer 11 is b, and the thickness b is in the range of 30.3 nm to 46.3 nm. The thickness is set according to the position of the source / drain electrodes of the adjacent transistors. Then, the remaining anti-reflection layer 5 is cleaned by using a wet cleaning method, as shown in FIG. 7. Figure 8 The cleaning liquid for the wet cleaning method is sulfuric acid with a mass concentration of 98% and hydrogen peroxide with a mass concentration of 30%. The mass ratio of the sulfuric acid to the hydrogen peroxide is 5:1. The cleaning temperature when the wet cleaning method is used is 125°C. The cleaning liquid has strong acidity, and the anti-reflection layer 5 is removed under the corrosion of the strong acid solution.

[0044] S7, removing the OPL layer 4 on both sides of the isolation layer 11 by using a dry etching method, as shown in FIG. 8. Figure 9The OPL layer is an amorphous carbon hard mask layer, which is a hydrocarbon and mainly composed of carbon with a small amount of hydrogen doped;

[0045] S8, growing the source and drain 10 from the body silicon layer 3 on both sides of the isolation layer 11 by using an epitaxial growth process; the source and drain 10 is made of silicon germanium (SiGe), and refer to Figure 10 .

[0046] The above source and drain short circuit method is a preparation method of source and drain of adjacent transistors in an integrated circuit. In the method, the setting of the isolation layer increases the epitaxial growth (EPI) process window when growing the source and drain of the transistor (the transistor is a PMOS transistor but is not limited to a PMOS transistor). Therefore, in the epitaxial growth of the source and drain in the above step S8, the source and drain are separated by the isolation layer, which effectively reduces the risk of short circuit caused by bridging of the source and drain compared with the source and drain structure shown in Figure 1 .

[0047] The above method is applied to the manufacture of an integrated circuit, which is a static random access memory containing a plurality of transistors. The static random access memory includes at least two adjacent transistors, which are planar transistors (Planner) or fin field effect transistors (FinFET). The transistors each include a source and drain 11. The minimum width between the source and drain 11 of the two adjacent transistors is 30.3 nm, and the maximum width is 46.3 nm. The isolation layer 11 is provided between the source and drain of the two adjacent transistors in the static random access memory, and the isolation layer 11 is prepared by the above method of reducing the short circuit of the source and drain.

[0048] The width of the isolation layer 11 is equal to the minimum distance between the source and drain of the two adjacent transistors. Therefore, when manufacturing the source and drain of the transistor in the integrated circuit (the integrated circuit includes the static random access memory), the width of the isolation layer can be determined according to the minimum distance between the source and drain of the adjacent transistors required. In this embodiment, the minimum distance between the source and drain of the transistor is 30.3 nm. Under the condition that the active area size of the transistor is the same as the currently commonly used active area size of the transistor (the active area mainly refers to the source and drain of the transistor), even if the distance between the source and drain of the two adjacent transistors is reduced according to actual needs, the source and drain of the two adjacent transistors will not be bridged due to the blocking of the isolation layer. Moreover, the reduction of the distance reduces the physical size between semiconductor devices, thereby increasing the density of semiconductor devices per unit area of the integrated circuit and improving the integration of the integrated circuit.

[0049] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present application should be considered within the protection scope of the present application.

Claims

1. A method for reducing source-drain short circuits, the method comprising the following steps: S1. A substrate is provided, wherein a first trench isolation region is distributed on the substrate at intervals, and a bulk silicon layer, an OPL layer, an anti-reflection layer and a photoresist layer are deposited on the substrate and the top of the first trench isolation region in sequence from bottom to top; S2. The middle part of the OPL layer is etched using photolithography to obtain an etched groove; S3. Remove the photoresist layer to expose the top of the anti-reflective layer; S4. Deposit a first etching layer on the inner surface of the etching groove and the top of the anti-reflection layer; S5. Deposit a second etched layer on top of the first etched layer; S6. The first etching layer and the second etching layer are etched using photolithography to remove the first etching layer and the second etching layer above the OPL layer, and at the same time, a portion of the first etching layer and the second etching layer inside the etching trench is removed to obtain an isolation layer. The width of the isolation layer is equal to the minimum distance between the source and drain of two adjacent transistors. S7. Remove the OPL layers on both sides of the isolation layer; S8. Growing source and drain electrodes in the bulk silicon layers on both sides of the isolation layer; The photoresist layer includes a first photoresist layer and a second photoresist layer arranged adjacent to each other, and a gap is provided between the first photoresist layer and the second photoresist layer. The width of the gap is equal to the minimum distance between the source and drain electrodes of adjacent transistors. The width of the gap, the width of the etching trench, and the width of the isolation layer are all equal, and the minimum width of the gap, the width of the etching trench, and the width of the isolation layer is 30.3 nm. The first etched layer is made of SiN and has a thickness of 30 Å to 50 Å. The second etched layer is made of SiO2 and has a thickness of 273 Å to 413 Å. The isolation layer includes a first etched layer and a second etched layer, and the thickness of the isolation layer is 303 Å to 463 Å. The source and drain electrodes are made of germanium-silicon.

2. A static random access memory (SRAM), the SRAM comprising at least two adjacently distributed transistors, each transistor including a source and a drain, characterized in that, An isolation layer is provided between the source and drain of two adjacent transistors, and the isolation layer is prepared by the method for reducing source-drain short circuits as described in claim 1.

3. The static random access memory according to claim 2, characterized in that, The minimum width between the source and drain of two adjacent transistors is 30.3 nm, and the maximum width is 46.3 nm.

4. The static random access memory according to claim 3, characterized in that, The transistor is a planar transistor or a fin field-effect transistor.

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