Memory device and method for forming semiconductor device

Abstract

The embodiment of the invention discloses a memory device and a method for forming a semiconductor device. The memory device includes a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on a first side of the substrate, the first to third transistors each formed with a first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, the fourth to seventh transistors each formed with a second conductivity, in which the first level is disposed vertically with respect to the second level. The first to seventh transistors are operable to form a static random access memory (SRAM) cell.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods for forming semiconductor devices. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the iterative reduction in the size of the smallest component, allowing more components to be integrated into a given area. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a memory device is provided, comprising: a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on the first side of the substrate, wherein the first transistor to the third transistor are all formed with first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, wherein the fourth transistor to the seventh transistor are all formed with second conductivity, wherein the first level is disposed perpendicular to the second level; wherein the first transistor to the seventh transistor are operatively formed with respect to static random access memory (SRAM) cells.

[0004] According to another aspect of the embodiments of this application, a memory device is provided, comprising: a memory array including a plurality of memory cells; wherein each of the plurality of memory cells includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed on one side of a substrate; wherein the first to third transistors having p-type conductivity of each of the plurality of memory cells are formed at a first level on the side, and the fourth to seventh transistors having n-type conductivity of each of the plurality of memory cells are formed at a second level on the side.

[0005] According to another aspect of the embodiments of this application, a method for forming a semiconductor device is provided, comprising: forming a first active region extending along a first lateral direction at a first level on a first side of a substrate; forming a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure at the first level, the first gate structure to the fourth gate structure extending along a second lateral direction perpendicular to the first lateral direction and passing through the first active region; forming a second active region extending along the first lateral direction at a second level above the first level on the first side; and forming a fifth gate structure, a sixth gate structure, a seventh gate structure, and an eighth gate structure at the second level, the fifth gate structure to the eighth gate structure extending along the second lateral direction and traversing the second active region; wherein the first active region and the first gate structure to the fourth gate structure operably form a first transistor, a second transistor, and a third transistor having a first conductivity of a memory cell, and the second active region and the fifth gate structure to the eighth gate structure operably form a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor having a second conductivity of a memory cell. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 An example circuit diagram of a memory cell according to some embodiments is shown.

[0008] Figures 2-7 It is shown that, according to some embodiments, they are commonly configured to be formed in a CFET structure Figure 1 The layout of the memory cells.

[0009] Figure 8 and Figure 9 Together, they illustrate, according to some embodiments, including Figure 1 An example diagram of a memory array with multiple memory cells.

[0010] Figure 10 The following are examples of implementations based on... Figures 8-9 A cross-sectional view of a semiconductor device formed by mapping.

[0011] Figure 11 and Figure 12 Together, they illustrate, according to some embodiments, including Figure 1 Another example diagram of a memory array with multiple memory cells.

[0012] Figure 13 and Figure 14 Together, they illustrate, according to some embodiments, including Figure 1 Another mapping of a memory array of multiple memory cells.

[0013] Figure 15 Another example circuit diagram of a memory cell according to some embodiments is shown.

[0014] Figure 16 Another example circuit diagram of a memory cell according to some embodiments is shown.

[0015] Figure 17 Another example circuit diagram of a memory cell according to some embodiments is shown.

[0016] Figure 18 and Figure 19 Together, they illustrate, according to some embodiments, including Figure 16 An example diagram of a memory array with multiple memory cells.

[0017] Figure 20 The following are examples of implementations based on... Figures 18-19 A cross-sectional view of a semiconductor device formed by mapping.

[0018] Figure 21 An example flowchart of a method for forming a semiconductor device including memory cells configured with CFET structures, according to some embodiments, is shown.

[0019] Figures 22-30 The passage according to some embodiments is shown. Figure 21 Cross-sectional views of example semiconductor devices manufactured using this method at various manufacturing stages.

[0020] Figure 31 An example flowchart of a method for forming a semiconductor device including memory cells configured with CFET structures, according to some embodiments, is shown.

[0021] Figures 32-42 The passage according to some embodiments is shown. Figure 31 Cross-sectional views of example semiconductor devices manufactured using this method at various manufacturing stages.

[0022] Figure 43 The following are examples of implementations based on... Figures 8-9 A cross-sectional view of a semiconductor device formed by mapping. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0025] A complementary field-effect transistor (CFET) is a type of gate-all-agent (GAA) field-effect transistor. Generally, a GAA FET comprises multiple nanostructures, such as nanosheets or nanowires, stacked vertically together. P-type and n-type GAA FETs are formed on the same horizontal plane on a substrate and separated by an isolation structure. In contrast, CFETs are typically fabricated by vertically stacking p-type and n-type GAA FETs together. This configuration of stacking n-type and p-type transistors in a single structure eliminates the need for n-to-p separation, reduces the active region footprint, and increases the transistor density within the chip. This stacking concept is not limited to GAA FETs; for example, CFETs can be formed using FinFET devices or a combination of GAAFETs and FinFETs.

[0026] Static Random Access Memory (SRAM) cells are commonly used in integrated circuits. SRAM cells have the advantageous characteristic of retaining data without requiring refresh. SRAM cells can include different numbers of transistors and are typically indicated by the number of transistors, such as a six-transistor (6T) SRAM cell, a seven-transistor (7T) SRAM cell, an eight-transistor (8T) SRAM cell, etc. Transistors typically form data latches for storing bits. Additional transistors can be added to control access to the transistors. SRAM cells are typically arranged as an array of rows and columns. Each row of an SRAM cell is connected to a word line (WL) that determines whether the SRAM cell is selected. Each column of an SRAM cell is connected to a bit line (BL) or a pair of complementary bit lines (BL and BLB) for storing bits read into or from the SRAM cell.

[0027] Generally, multi-port SRAM cells (e.g., 7T SRAM cells, 8T SRAM cells) offer advantages over single-port SRAM cells because they allow simultaneous read and write operations to different memory locations. This significantly increases system bandwidth and is particularly useful in applications where multiple processors or units need to access memory simultaneously, improving performance and efficiency compared to single-port designs. Some examples of advantages that multi-port SRAM cells can offer over single-port SRAM include, but are not limited to, parallel access, higher throughput, reduced latency, and better suitability for high-performance applications.

[0028] Multiport SRAM cells based on CFET structures have been proposed. For example, to form a multiport SRAM cell with eight transistors, a first layer comprising multiple p-type transistors (e.g., two pull-up transistors) is first formed on the front side of the substrate, and then a second layer comprising multiple n-type transistors (e.g., two pull-down transistors, two read-write gate transistors, and two read-transfer gate transistors) is formed above the first layer. That is, a conventional 8T SRAM cell has six transistors formed in the second layer, while only two transistors are formed in the first layer, which disadvantageously increases the area occupied by each SRAM cell. This inefficient area usage negatively impacts the integration of multiport SRAM cells into increasingly smaller integrated circuits. Therefore, the existing CFET structures configured for forming multiport memory cells are not entirely satisfactory in some respects.

[0029] This disclosure provides various embodiments of semiconductor devices (e.g., memory devices) formed with a CFET structure having first and second front-side layers on a substrate for forming transistors of different conductivity types. According to various embodiments of this disclosure, the memory device may include a plurality of multi-port SRAM cells, each SRAM cell including a plurality of transistors (e.g., more than six). In one aspect, as disclosed herein, a multi-port SRAM cell may include seven transistors. For example, first and second pull-up transistors configured as p-type and a read transmission gate transistor are formed at the first front-side layer; and first and second write transmission gate transistors configured as n-type and first and second pull-down transistors are formed at the second front-side layer. In another aspect, as disclosed herein, a multi-port SRAM cell may include eight transistors. For example, first and second pull-up transistors configured as p-type and first and second read transmission gate transistors are formed at the first front-side layer; and first and second write transmission gate transistors configured as n-type and first and second pull-down transistors are formed at the second front-side layer. Furthermore, each of the disclosed multi-port SRAM cells can be formed based on a 4CPP configuration; for example, up to four transistors of the SRAM cell can be formed along a common active region. Therefore, p-type read port transistors (e.g., read transmission gate transistors) can be formed vertically below n-type write port transistors (e.g., write transmission gate transistors). In other words, the read transmission gate transistors can form the same active region as the p-type pull-up transistors, which eliminates the need for additional area (e.g., another active region) to form the read port transistors. Advantageously, the disclosed multi-port SRAM cells do not incur area loss, thereby allowing a large number of these multi-port SRAM cells to be seamlessly integrated with advanced integrated circuits.

[0030] Figure 1 An example circuit diagram of a memory cell 100 according to some embodiments is shown. As shown, the memory cell 100 includes seven transistors operatively forming a 7T SRAM cell. In various embodiments, the seven transistors may be physically formed in a CFET structure, which will be discussed below. For example, the memory cell 100 includes transistors: a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first write transmission gate transistor WPG1, a second write transmission gate transistor WPG2, and a read transmission gate transistor RPG.

[0031] Transistors PU1 and PD1 form a first inverter, and transistors PU2 and PD2 form a second inverter, wherein the first and second inverters are cross-coupled to each other. For example, the source / drain terminals of transistors PU1 and PD1 are connected to each other at a common node 110, which is also coupled to the gate terminals of transistors PU2 and PD2; the source / drain terminals of transistors PU2 and PD2 are connected to each other at a common node 112, which is also coupled to the gate terminals of transistors PU1 and PD1. Specifically, both the first and second inverters are coupled between a first reference voltage 101 and a second reference voltage 103. In some embodiments, the first reference voltage 101 is a power supply voltage applied to the memory cell 100, sometimes referred to as "VDD", and the second reference voltage 103 is a ground voltage, sometimes referred to as "VSS". The first inverter (formed by transistors PU1 and PD1) is connected to transistor WPG1, which is selected by the write word line (WWL), and the second inverter (formed by transistors PU2 and PD2) is connected to transistor WPG2, which is also selected by the WWL. Furthermore, transistor WPG1 is coupled between the write bit line (WBL) and node 110, and transistor WPG2 is coupled between the write anti-phase line (WBLB) and node 112. Transistor RPG is gated by the read word line (RWL) and coupled between node 112 and the read bit line (RBL). In some embodiments, transistors WPG1 and WPG2 are sometimes referred to as write ports of memory cell 100, and transistor RPG is sometimes referred to as read ports of memory cell 100.

[0032] The gate terminals of transistors WPG1 and WPG2 are both connected to WWL. Transistors WPG1 and WPG2 are configured to receive pulse signals through WWL to accordingly enable or block access to memory cell 100 (e.g., write operations). Transistors PD1 and PU1 are coupled between VDD and VSS and coupled to each other at node 110. For example, transistor PU1 has a first source / drain terminal connected to VDD, and transistor PD1 has a first source / drain terminal connected to VSS, wherein the second source / drain terminals of transistors PU1 and PD1 are connected to each other at node 110. Transistor WPG1 has a first source / drain terminal connected to WBL and a second source / drain terminal connected to node 110, which is also coupled to the gate terminals of transistors PU2 and PD2. Similarly, transistors PD2 and PU2 are coupled between VDD and VSS and coupled to each other at node 112. For example, the first source / drain terminal of transistor PU2 is connected to VDD, and the first source / drain terminal of transistor PD2 is connected to VSS, wherein the second source / drain terminals of transistors PU2 and PD2 are connected to each other at node 112. Transistor WPG2 has a first source / drain terminal connected to WBLB and a second source / drain terminal connected to node 112, which is also coupled to the gate terminals of transistors PU1 and PD1.

[0033] In some embodiments, transistors PU1, PU2, and RPG may each comprise a p-type metal-oxide-semiconductor (PMOS) transistor, and transistors PD1, PD2, WPG1, and WPG2 may each comprise an n-type metal-oxide-semiconductor (NMOS) transistor. Although Figure 1 The transistors shown in the memory cell 100 are NMOS or PMOS transistors, but any of a variety of transistors or devices suitable for memory devices can be implemented as at least one transistor in the memory cell 100, such as bipolar junction transistors (BJTs), high electron mobility transistors (HEMTs), etc. Furthermore, as will be discussed below, p-type transistors PU1, PU2, and RPG are all formed as GAA FETs in a first layer disposed on the front side of the substrate, and n-type transistors PD1, PD2, WPG1, and WPG2 are all formed as GAA FETs in a second layer above the first layer.

[0034] In some other embodiments, transistors PU1, PU2, WPG1, and WPG2 may each include a PMOS transistor, and transistors PD1, PD2, and RPG may each include an NMOS transistor. For example, p-type transistors PU1, PU2, WPG1, and WPG2 are all formed as GAA FETs in a first layer disposed on the front side of the substrate, and n-type transistors PD1, PD2, and RPG are all formed as GAA FETs in a second layer above the first layer.

[0035] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 Layouts 200, 300, 400, 500, 600, and 700 are shown respectively, which can be used together to form two memory cells 100 configured as a CFET structure. Figure 1 For example, layouts 200, 300, 400, and 500 may collectively form two memory cells 100 (e.g., arranged along the same row or the same wL). In another example, layouts 200, 300, 600, and 700 may collectively form two memory cells 100 (e.g., arranged along the same row or the same wL). It should be understood that each of layouts 200 to 700 is simplified for illustrative purposes and therefore may include any of a variety of other patterns (or structures) while still remaining within the scope of this disclosure.

[0036] As shown, each of layouts 200 to 700 includes a cell boundary 101 that defines a physical region of two memory cells 100 (a first memory cell and a second memory cell), each memory cell 100 including seven transistors configured using a CFET structure. The CFET structure may include a plurality of first transistors disposed at a first level on the front side of the substrate, and a plurality of second transistors disposed at a second level on the front side of the substrate. In some embodiments, each of these first and second transistors is configured as a GAA FET, while the first and second transistors have opposite conductivity types. In some other embodiments, each of the first and second transistors may be formed as other types of transistor structures, while still remaining within the scope of this disclosure.

[0037] Typically, each of layouts 200 to 700 may include multiple patterns configured to form a corresponding structure; therefore, in the following discussion, these patterns of the disclosed layouts are referred to herein as the structures to be formed. For example, layout 200 is configured to form a structure of a first transistor at a first level on the front side; layout 300 is configured to form a structure of a second transistor at a second level on the front side; layouts 400 / 600 are configured to form a structure at a third level above a second level on the front side of the substrate; and layouts 500 / 700 are configured to form a structure at a first level on the back side of the substrate.

[0038] First refer to Figure 2 The layout 200 may include patterns for forming active regions 210 and 220 and gate structures 230, 235, 240, and 245, respectively. Active regions 210 and 220 may extend in the X direction; gate structures 230 to 245 may extend in the Y direction. Each of the active regions 210 and 220 may be formed as a fin structure or a stacked structure extending in the X direction, and each of the gate structures 230 to 245 may be formed as extending in the Y direction to traverse the active regions 210 and 220. The layout 200 may also include multiple diced patterns, such as 241, 242, and 243, each diced pattern extending in the X direction to traverse one or more of the gate structures 230-245. Dicing patterns 241 to 243 may each be configured to form a dielectric structure, thereby dividing one or more of the gate structures 230-245 into separate gate portions. For example, as... Figure 2 As shown, the cutting pattern 242 can divide the gate structure 230 into gate portions 230A and 230B, the gate structure 235 into gate portions 235A and 235B, the gate structure 240 into gate portions 240A and 240B, and the gate structure 245 into gate portions 245A and 245B.

[0039] Next reference Figure 3The layout 300 may include patterns for forming active regions 310 and 320 and gate structures 330, 335, 340, and 345, respectively. Active regions 310 and 320 may extend in the X direction; gate structures 330 to 345 may extend in the Y direction. Each of the active regions 310 and 320 may be formed as a fin structure or a stacked structure extending in the X direction, and each of the gate structures 330 to 345 may be formed as extending in the Y direction across the active regions 310 and 320. The layout 300 may also include multiple diced patterns, such as 341, 342, and 343, each diced pattern extending in the X direction across one or more gate structures 330-345. Dicing patterns 341 to 343 may each be configured to form a dielectric structure, thereby dividing one or more gate structures 330-345 into separate gate portions. For example, as... Figure 3 As shown, the cutting pattern 342 can divide the gate structure 330 into gate portions 330A and 330B, the gate structure 335 into gate portions 335A and 335B, the gate structure 340 into gate portions 340A and 340B, and the gate structure 345 into gate portions 345A and 345B.

[0040] In some embodiments, active regions 210 and 310 are vertically aligned with each other, active regions 220 and 320 are vertically aligned with each other; gate structures 230 and 330 are vertically aligned with each other, gate structures 235 and 335 are vertically aligned with each other, gate structures 240 and 340 are vertically aligned with each other, and gate structures 245 and 345 are vertically aligned with each other. Furthermore, dicing patterns 241 and 341 are vertically aligned with each other, dicing patterns 242 and 342 are vertically aligned with each other, and dicing patterns 243 and 343 are vertically aligned with each other. Active regions 210 and 310 may be physically formed as a single structure (sometimes referred to as "active region 210 / 310"), active regions 220 and 320 may be physically formed as a single structure (sometimes referred to as "active region 220 / 320"), gate structures 230 and 330 may be physically formed as a single structure (sometimes referred to as "gate structure 230 / 330"), gate structures 235 and 335 may be physically formed as a single structure (sometimes referred to as "gate structure 235 / 335"), gate structures 240 and 340 may be physically formed as a single structure (sometimes referred to as "gate structure 240 / 340"), and gate structures 245 and 345 may be physically formed as a single structure (sometimes referred to as "gate structure 245 / 345").

[0041] As will be discussed below, in addition to gate structures 230 / 330 and 245 / 345, each of gate structures 235 / 335 and 240 / 340 may include a lower portion and an upper portion corresponding to a first level and a second level, respectively, wherein the lower portion and the upper portion are electrically coupled to each other even when a dielectric layer is perpendicularly inserted therebetween. In some embodiments, each of gate structures 230 / 330 and 245 / 345 may further include a lower portion and an upper portion corresponding to a first level and a second level, respectively, but the lower portion and the upper portion are electrically isolated from each other by a dielectric layer perpendicularly inserted therebetween. In other words, the corresponding dielectric layer may completely separate the lower portion and the upper portion of gate structure 230 / 330 or 245 / 345, while the corresponding dielectric layer may partially separate the upper portion and the lower portion of each of gate structures 235 / 335 and 240 / 340.

[0042] For example, active regions 210 / 310 and 220 / 320 may each initially be formed as a stacked structure protruding from the front surface of the substrate. The stack may include a plurality of first semiconductor nanostructures (e.g., first nanosheets) extending in the X direction and perpendicularly separated from each other, and a plurality of second semiconductor nanostructures (e.g., second nanosheets) extending in the X direction and perpendicularly separated from each other. The first nanosheets are located at a first level, and the second nanosheets are located at a second level. According to some embodiments of this disclosure, the first nanosheets formed based on the lower portion of active regions 210 / 310 or the lower portion of active regions 220 / 320 may partially form a first transistor formed at the first level; and the second nanosheets formed based on the upper portion of active regions 210 / 310 or the upper portion of active regions 220 / 320 may partially form a second transistor formed at the second level. Furthermore, the first and second nanosheets may be perpendicularly aligned but separated from each other, with at least one dielectric layer inserted between them.

[0043] Next, the corresponding portions of the first and second nanosheets in each stack covered by gate structures 230 / 330 to 245 / 345 can be retained, these portions initially formed as multiple pseudo (e.g., polysilicon) gate structures. Other portions of the first nanosheet are replaced by multiple first epitaxial structures, and other portions of the second nanosheet are replaced by multiple second epitaxial structures. According to some embodiments of this disclosure, the first epitaxial structure (at a first layer) can be formed with p-type conductivity, and the second epitaxial structure (at a second layer) can be formed with n-type conductivity. The first epitaxial structure can operably form corresponding source / drain terminals of a first transistor at the first layer, and the second epitaxial structure can operably form corresponding source / drain terminals of a second transistor at the second layer.

[0044] Next, each of the pseudo-gate structures 230 / 330 to 245 / 345 can be replaced by a corresponding active (e.g., metal) gate structure to form the first and second transistors. As described above, each active gate structure may include a lower portion and an upper portion corresponding to the first and second levels, respectively. Furthermore, the lower and upper portions of the active gate structures 230 / 330 or 245 / 345 may be electrically isolated from each other, while the upper and lower portions of each of the active gate structures 235 / 335 and 240 / 340 may be electrically coupled to each other. For example, the lower portion of the active gate structure may include one or more first work function metals configured to form the gate terminal of one of the first transistors having p-type conductivity, and the upper portion of the active gate structure may include one or more second work function metals. (Refer to...) Figures 25-43 The details describe a series of manufacturing processes for forming a first transistor at the first level and a second transistor at the second level.

[0045] As a brief overview, the transistors PU1, PU2, and RPG of each of the first and second memory cells 100 can be formed at the first level based on layout 200 (e.g., Figure 2 As shown), and transistors WPG1, WPG2, PD1, and PD2 in each of the first and first memory cells 100 can be formed at a second level based on layout 300 (as shown in...). Figure 3 (As shown in the diagram). Furthermore, pseudo-transistors can be formed in the first level (as shown in the diagram). Figure 2 (represented by the symbol "X" in some embodiments). In some embodiments, transistors PU1, PU2 and RPG at the first level can be p-type conductive, and transistors WPG1, WPG2, PD1 and PD2 at the second level can be n-type conductive.

[0046] Using the first memory unit 100 as a representative example, in Figure 2 In the transistor PU2, a channel, a gate terminal, and source / drain terminals are formed by a subset of the first nanosheets in the active region 210, a gate portion 235A, and a subset of the first epitaxial structures formed by the active region 210 and disposed on the opposite side of the gate structure 235A. Transistor PU1 may include a channel, a gate terminal, and source / drain terminals, formed by another subset of the first nanosheets in the active region 210, a gate portion 240A, and another subset of the first epitaxial structures formed by the active region 210 and disposed on the opposite side of the gate structure 240A. Transistor RPG may include a channel, a gate terminal, and source / drain terminals, formed by yet another subset of the first nanosheets in the active region 210, a gate portion 230A, and yet another subset of the first epitaxial structures formed by the active region 210 and disposed on the opposite side of the gate structure 230A.

[0047] exist Figure 3 In the transistor PD1, transistor WPG2 may include its channel, gate terminal, and source / drain terminals, which are formed by a subset of the second nanosheets in the active region 310, the gate portion 330A, and a subset of the second epitaxial structures formed by the active region 310 and disposed on the opposite side of the gate structure 330A. Transistor PD2 may include its channel, gate terminal, and source / drain terminals, which are formed by another subset of the second nanosheets in the active region 310, the gate portion 335A, and another subset of the second epitaxial structures formed by the active region 310 and disposed on the opposite side of the gate structure 335A. Transistor PD1 may include its channel, gate terminal, and source / drain terminals, which are formed by another subset of the second nanosheets in the active region 310, the gate portion 340A, and another subset of the second epitaxial structures formed by the active region 310 and disposed on the opposite side of the gate structure 340A. The transistor WPG1 may include its channel, gate terminal and source / drain terminals, which are formed by a subset of the second nanosheet in the active region 310, the gate portion 345A and a subset of the second epitaxial structure formed by the active region 310 and disposed on the opposite side of the gate structure 345A.

[0048] Refer again Figure 2 The layout 200 may also include patterns for forming source / drain contact structures 250, 252, 254, 256, 258, 262, 266, and 268, respectively. Similarly, in Figure 3 In this configuration, layout 300 may further include patterns for forming source / drain contact structures 350, 352, 354, 356, 358, 362, 364, and 366, respectively. These source / drain contact structures 250 to 268 and 350 to 366 are sometimes referred to as MDs. Typically, each of these MDs 250 to 268 and 350 to 366 is configured to be electrically connected to the source / drain terminals of the corresponding transistor. For example, each of the MDs 250 to 268 and 350 to 366 may be physically coupled to or surrounding an epitaxial structure of the corresponding transistor. In some embodiments, each of the MDs 250 to 268 and 350 to 366 may extend in the same lateral direction (e.g., the Y direction) as the gate structures 230-245 and 330-345.

[0049] For example, in Figure 2In the first memory cell 100, MD 252 is connected to the second source / drain terminal of transistor PU2 and the first source / drain terminal of transistor RPG; MD 254 is connected to the first source / drain terminal of transistor PU2 and the first source / drain terminal of transistor PU1 in each of the first and second memory cells 100; MD 256 is connected to the second source / drain terminal of transistor PU1 in the first memory cell 100; MD 266 is connected to the second source / drain terminal of transistor PU1 in the second memory cell 100; MD 262 is connected to the second source / drain terminal of transistor PU2 in the second memory cell 100 and the first source / drain terminal of transistor RPG in the second memory cell 100; MD 250 is connected to the second source / drain terminal of transistor RPG in each of the first and second memory cells 100.

[0050] exist Figure 3 In the first memory cell 100, MD 350 is connected to the first source / drain terminal of transistor WPG2; MD 352 is connected to the second source / drain terminals of transistor WPG2 and transistor PD2 in the first memory cell 100; MD 362 is connected to the second source / drain terminals of transistor WPG2 and transistor PD2 in the second memory cell 100; MD 354 is connected to the first source / drain terminals of transistor PD2 and transistor PD1 in the first memory cell 100; MD 364 is connected to the first source / drain terminals of transistor PD2 and transistor PD1 in the second memory cell 100; MD 356 is connected to the second source / drain terminals of transistor PD1 and transistor WPG1 in the first memory cell 100; MD 366 is connected to the second source / drain terminals of transistor PD1 and transistor WPG1 in the second memory cell 100; MD 358 is connected to the first source / drain terminal of transistor WPG1 in each of the first and second memory cells 100.

[0051] In some embodiments, MD 252 ( Figure 2 ) and MD 352 ( Figure 3 ) can be connected to each other through a first through-hole structure (not shown), MD 256 ( Figure 2 ) and MD 356 ( Figure 3The first memory cell 100 can be interconnected via a second via structure. In other words, the first via structure can extend vertically from the first level to the second level to connect MD 252 to MD 352, and the second via structure can extend vertically from the first level to the second level to connect MD 256 and MD 356. Therefore, the (internal) node 112 of the first memory cell 100 can be partially formed based on MD 252, MD 352, and the first via structure vertically inserted therebetween, where the corresponding source / drain terminals of transistors PU2, PD2, and RPG are connected to each other; and the (internal) node 110 of the first memory cell 100 can be operatively formed based on MD 256, MD 356, and the second via structure vertically inserted therebetween, where the corresponding source / drain terminals of transistors PU1 and PD2 are connected to each other. Nodes 110 and 112 of the second memory cell 100 can be partially formed in a similar manner.

[0052] Refer again Figure 2 The layout 200 may also include patterns for forming a plurality of via structures 270, 271, 272, 273, 274, and 275, respectively. In some embodiments, each of the via structures 270 to 275 may be formed below the MD included in the layout 200. Specifically, each of the via structures 270 to 275 may extend downward from the front side of the substrate (e.g., a first level on the front side) to the back side of the substrate (e.g., a first level on the back side). Such via structures 270 to 275 are sometimes referred to as BVDs.

[0053] For example, BVD 273 is formed below MD 250, allowing MD 250 to be electrically connected to one or more interconnect structures formed in the first level on the back side (e.g., interconnect structures configured as RBLs of first and second memory cells 100 based on layout 500 / 700); BVD 271 is formed below MD 254, allowing MD 254 to be electrically connected to one or more interconnect structures formed in the first level on the back side (e.g., interconnect structures configured as power rails carrying VDD based on layout 500 / 700); BVD 270 is formed below MD 252, allowing MD 252 to be electrically connected to one or more interconnect structures formed in the first level on the back side (e.g., first internal contact structures of the first memory cell 100 based on layout 500 / 700); BVD 272 is formed below MD 256, allowing MD 252 to be electrically connected to one or more interconnect structures formed in the first level on the back side (e.g., first internal contact structures of the first memory cell 100 based on layout 500 / 700); BVD 272 is formed below MD 256, allowing MD 252 to be electrically connected to one or more interconnect structures formed in the first level on the back side (e.g., first internal contact structures of the first memory cell 100 based on layout 500 / 700); 256 is electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., the second internal contact structure of the first memory cell 100 formed based on layout 500 / 700); BVD 274 is formed below MD 262, allowing MD 262 to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., the first internal contact structure of the second memory cell 100 formed based on layout 500 / 700); BVD 275 is formed below MD 266, allowing MD 266 to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., the second internal contact structure of the second memory cell 100 formed based on layout 500 / 700).

[0054] The layout 200 may also include patterns for forming a plurality of via structures 280, 281, 282, 283, 284, and 285, respectively. In some embodiments, each of the via structures 280 to 285 may be formed below a gate structure (or gate portion) included in the layout 200. Specifically, each of the via structures 280 to 285 may extend down from the front side of the substrate (e.g., a first level on the front side) to the back side of the substrate (e.g., a first level on the back side). Such via structures 280 to 285 are sometimes referred to as BVGs.

[0055] For example, BVG 280 is formed below gate portion 230A, allowing gate portion 230A to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., interconnect structures configured as RWLs of the first memory cell 100 based on layout 500 / 700); BVG 283 is formed below gate portion 230B, allowing gate portion 230B to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., interconnect structures configured as RWLs of the second memory cell 100 based on layout 500 / 700); BVG 281 is formed below gate portion 235A, allowing gate portion 235A to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., second internal contacts of the first memory cell 100 based on layout 500 / 700); BVG BVG 284 is formed below gate portion 235B, allowing gate portion 235B to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., the second internal contact of the second memory cell 100 formed based on layout 500 / 700); BVG 282 is formed below gate portion 240A, allowing gate portion 240A to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., the first internal contact of the first memory cell 100 formed based on layout 500 / 700); BVG 285 is formed below gate portion 240B, allowing gate portion 240B to be electrically connected to one or more interconnect structures formed in the first layer on the back side (e.g., the first internal contact of the second memory cell 100 formed based on layout 500 / 700).

[0056] Similarly, layout 300 may also include patterns for forming a plurality of via structures 370, 371, 372, and 373, respectively. In some embodiments, each of the via structures 370 to 373 may be formed above a MD included in layout 300. Specifically, each of the via structures 370 to 373 may extend upward from a second level on the front side to a third level on the front side. Such via structures 370 to 373 are sometimes referred to as VDs.

[0057] For example, VD 370 is formed above MD 350, allowing MD 350 to be electrically connected to one or more interconnect structures formed in the third level on the front side (e.g., interconnect structures of WBLs configured for the first and second memory cells 100 based on layout 400); VD 373 is formed above MD 358, allowing MD 358 to be electrically connected to one or more interconnect structures formed in the third level on the front side (e.g., interconnect structures of WBLs configured for the first and second memory cells 100 based on layout 400); VD 371 is formed above MD 354, allowing MD 354 to be electrically connected to one or more interconnect structures formed in the third level on the front side (e.g., interconnect structures of power rails configured to carry the VSS of the first memory cell 100 based on layout 400); VD 372 is formed above MD 364, allowing MD 358 ...3 is formed above MD 358, allowing MD 358 to be electrically connected to one or more interconnect structures formed in the third level on the front side (e.g., interconnect structures of power 364 is electrically connected to one or more interconnect structures formed in the third level on the front side (e.g., the power rail interconnect structure of the VSS configured to carry the second memory cell 100 based on layout 400).

[0058] The layout 300 may also include patterns for forming a plurality of via structures 380, 381, 382, ​​and 383, respectively. In some embodiments, each of the via structures 380 to 383 may be formed over a gate structure (or gate portion) included in the layout 300. Specifically, each of the via structures 380 to 383 may extend upward from a second level on the front side to a third level on the front side. Such via structures 380 to 383 are sometimes referred to as VGs.

[0059] For example, VG 380 is formed above gate portion 330A, and VG 381 is formed above gate portion 345A, allowing gate portions 330A and 345A to be electrically connected to one or more interconnect structures formed in the third layer on the front side (e.g., interconnect structures configured as WWL of the first memory cell 100 based on layout 400); VG 382 is formed above gate portion 330B, and VG 383 is formed above gate portion 345B, thereby allowing gate portions 330B and 345B to be electrically connected to one or more interconnect structures formed in the third layer on the front side (e.g., interconnect structures configured as WWL of the second memory cell 100 based on layout 400).

[0060] Next reference Figure 4 Layout 400 may include patterns for forming interconnect structures 410, 420, 430, 440, 450, and 460 respectively in a third layer on the front side. This is based on layout 300 ( Figure 3The third layer above the second layer is sometimes referred to as the bottom layer of a plurality of front metallization layers, such as the M0 layer, and the interconnect structures 410 to 460 disposed therein are sometimes each referred to as M0 orbitals. The front metallization layers typically comprise one or more dielectric materials (e.g., silicon, oxide, low-k dielectric, etc.) with embedded corresponding metal orbitals formed of, for example, copper. These M0 orbitals may extend in the same direction (e.g., the X direction) as the active regions 210-220 and 310-320.

[0061] In some embodiments, each of the M0 rails 410 to 440 can be coupled to a corresponding underlying MD via VD, or coupled to a corresponding underlying gate structure (gate portion) in the second layer via VG. For example, M0 rail 410 is coupled to gate portions 330A and 335A via VG 380 and 381, respectively; M0 rail 420 is coupled to MD 350 via VD 370; M0 rail 430 is coupled to MD 354 via VD 371; 440 is coupled to gate portions 330B and 335B via VG 382 and 383, respectively; M0 rail 450 is coupled to MD 358 via VD 373; and M0 rail 460 is coupled to MD 364 via VD 372.

[0062] M0 rail 410 is operably used as part of the WWL of the first memory cell 100; M0 rail 420 is operably used as part of the WBL of the first and second memory cells 100; M0 rail 430 is operably used as part of the power rail carrying the ground voltage VSS of the first memory cell 100; M0 rail 440 is operably used as part of the WWL of the second memory cell 100; M0 rail 450 is operably used as part of the WBLB of the first and second memory cells 100; M0 rail 460 is operably used as part of the power rail carrying the ground voltage VSS of the second memory cell 100.

[0063] Then refer to Figure 5 The layout 500 may include patterns for forming interconnect structures 510, 520, 530, 535, 540, 550, 560, and 565, respectively, in a first layer on the back side. The first layer on the back side may sometimes be referred to as the bottom layer of a plurality of back-side metallization layers, such as a BMO layer, and the interconnect structures 510 to 565 disposed therein may each be referred to as BMO orbitals. The back-side metallization layer typically comprises one or more dielectric materials (e.g., silicon, oxide, low-k dielectric, etc.) embedded with corresponding metal orbitals formed of, for example, copper. These BMO orbitals may extend along the same direction (e.g., the X direction) as the active regions 210-220 and 310-320.

[0064] In some embodiments, each of the BMO orbitals 510 to 565 may be coupled via BVD to a corresponding one of the overlay MDs in the first layer on the front side, or via BVG to a corresponding one of the overlay gate structures (gate portions) in the first layer on the front side. For example, BM0 track 510 is coupled to MD 254 via BVD 271; BM0 track 540 is coupled to MD 250 via BVD 273; BM0 track 520 is coupled to gate portion 230A via BVG 280; BM0 track 550 is coupled to gate portion 230B via BVG 283; BM0 track 530 is coupled to MD 252 and gate portion 240A via BVD 270 and BVG 282, respectively; BM0 track 535 is coupled to MD 256 and gate portion 235A via BVD 272 and BVG 281, respectively; BM0 track 560 is coupled to MD 262 and gate portion 240B via BVD 274 and BVG 285, respectively; BM0 track 565 is coupled to MD 266 and gate portion 235B via BVD 275 and BVG 284, respectively.

[0065] BM0 track 510 can be operably used as a portion of the power rail carrying the power supply voltage VDD of the first and second memory cells 100; BM0 track 540 can be operably used as a portion of the RBL of the first and second memory cells 100; BM0 track 520 can be operably used as a portion of the RWL of the first memory cell 100; and BM0 track 550 can be operably used as a portion of the RWL of the second memory cell 100. Furthermore, BM0 tracks 530 and 535 can be used as the first and second internal contact structures of the first memory cell 100, respectively; BM0 tracks 560 and 565 can be used as the first and second internal contact structures of the second memory cell 100, respectively.

[0066] Figure 6 The layout of 600 and Figure 4 The layout is basically the same as the 400, except for some differences in configuration and functions. Figure 7 The layout of 700 and Figure 5Layout 500 is substantially similar. Therefore, the following discussion will focus on the differences. For example, layout 600 also includes M0 tracks 410 to 460. However, M0 track 420 is configured as the VSS of the first memory cell, M0 track 430 is configured as the WBL of the first and second memory cells, M0 track 450 is configured as the VSS of the second memory cell, and M0 track 460 is configured as the WB for the first and second memory cells. Layout 700 is the same as layout 500 (e.g., it also includes BMO tracks 510, 520, 530, 535, 540, 550, 560 and 565 respectively configured as the VDD of the first and second memory cells, the RWL of the first memory cell, the first internal contact structure of the first memory cell, the second internal contact structure of the first memory cell, the RBL of the first and second memory cells, the RWL of the second memory cell, the first internal contact structure of the second memory cell, and the second external contact structure of the second memory cell).

[0067] Figure 8 and Figure 9 An example mapping 800 of a memory array including multiple memory cells 100 according to some embodiments is illustrated. For example, the memory array may include four memory cells 100 (such as the first memory cell, second memory cell, and fourth memory cell shown). Specifically, Figure 8 The first level of mapping 800 is shown (similar to...) Figure 2 The layout of 200), Figure 9 This shows the second and higher levels of mapping 800 (similar to...) Figure 3 The layout 300), in which the first and second levels can be vertically aligned with each other.

[0068] For the sake of simplicity, Figure 8 and Figure 9 The diagram shows the corresponding active regions of the seven transistors in each of the four memory cells (e.g., Figure 8 The active regions 802, 804, 806, and 808, and Figure 9 The active regions 902, 904, 906, and 908) and the gate structure (e.g., Figure 8 The gate structures 812, 814, 816 and 818, and Figure 9 The gate structures are 912, 914, 916, and 918, but this is not intended to limit the scope of the disclosure. As shown, in Figure 8 In this context, the individual transistor RPGs of two or more memory cells can share the same gate structure. For example, the transistor RPGs of the first and second memory cells share a first portion of gate structure 812, and the transistor RPGs of the third and fourth memory cells share a second portion of gate structure 812. Similarly, in... Figure 9 In this configuration, corresponding transistors WPG1 of two or more memory cells may share the same gate structure, and corresponding transistors WPG2 of two or more memory cells may share the same gate structure. In some embodiments, these four memory cells may be operatively configured along a common row (e.g., a WL) and along corresponding four columns (e.g., four pairs of BL / BLB).

[0069] Figure 10 The following is illustrated based on mapping 800 according to some embodiments. Figures 8-9 A cross-sectional view of a portion of the semiconductor device formed. For example, Figure 10 The cross-sectional view is taken along line AA, such as... Figures 8-9 As shown. Specifically, line AA follows... Figure 8 The active area 802 and Figure 9 The active region 902 extends or is cut along the first memory cell.

[0070] As shown, transistors PU2, PU1, and RPG are formed in a first layer on the front side of the substrate, and transistors WPG2, PD2, PD1, and WPG1 are formed in a second layer above the first layer. Transistors PD2 and PU2 are vertically aligned with each other; transistors PD1 and PU1 are vertically aligned with each other; transistors WPG1 and RPG are vertically aligned with each other; and transistors WPG2 and the dummy transistor are vertically aligned with each other.

[0071] In some embodiments, transistors PU2, PU1, and RPG are formed of p-type, with the source / drain terminals of each transistor formed of a p-type epitaxial structure, and their gate terminals (or active gate structures) formed of one or more p-type work function metals; transistors WPG2, PD2, PD1, and WPG1 are formed of n-type, with the source / drain terminals of each transistor formed of an n-type epitaxial structure, and their gate terminals (or active gate structures) formed of one or more n-type work function metals.

[0072] Using vertically arranged transistors RPG and WPG1 as representative examples, transistor RPG has a plurality of nanosheets 1010 operably configured as its channel, p-type epitaxial structures 1014 and 1016 operably configured as its source / drain terminals, and a gate structure 1012 operably configured as its gate terminal; and transistor WPG1 has a plurality of nanosheets 1020 operably configured as its channel, n-type epitaxial structures 1024 and 1026 operably configured as its source / drain terminals, and a gate structure 1022 operably configured as its gate terminal. Each nanosheet 1010 is enclosed by a gate structure 1012, which may include a gate dielectric and one or more p-type work function metals, and its ends are coupled to the p-type epitaxial structures 1014 and 1016, respectively. Each nanosheet 1020 is encapsulated by a gate structure 1022, which may include a gate dielectric and one or more n-type work function metals, and its ends are coupled to n-type epitaxial structures 1024 and 1026, respectively. According to some embodiments, the gate structures 1012 and 1022 are electrically isolated from each other by a dielectric layer 1050. For example, in a direction perpendicular to... Figure 10 Another cross-sectional view of the cross-section (e.g., Figure 43 In this structure, gate structure 1012 (or one or more work function metals thereof) and gate structure 1022 (or one or more work function metals thereof) are separated from each other by dielectric layer 1050. In other words, the work function metal of gate structure 1012 and the work function metal of gate structure 1022 do not contact each other. Furthermore, one of the source / drain terminals of the dummy transistor (X) can be replaced by dielectric structure 1060, to which one end of each nanosheet of the dummy transistor is coupled.

[0073] According to some embodiments, Figure 11 and Figure 12 Together, they illustrate example mapping 1100. Figure 13 and Figure 14 Together, another example mapping 1300 is shown. Each of mappings 1100 and 1300 is similar to... Figures 8-9 The mapping 800 shown, for example, is a memory array comprising four memory cells 100 arranged along a common row (or WL).

[0074] In some embodiments, mapping 1100 shows that the gate structures of transistors RPG, PU2, and PU1 in each of the four memory cells are formed by a first combination of work function metals or a first threshold voltage. Figure 11 ); and the gate structure of transistors WPG2, PD2, PD1 and WPG1 in each of the four memory cells is formed by a second combination of work function metals or a second threshold voltage. Figure 12 ).

[0075] In some embodiments, mapping 1300 shows that the gate structures of transistors PU2 and PU1 in each of the four memory cells are formed by a first combination of work function metals or a first threshold voltage. Figure 13 The gate structure of the transistor RPG and dummy transistor in each of the four memory cells is formed by a second combination of work function metals or a second threshold voltage. Figure 13 The gate structures of transistors PD2 and PD1 in each of the four memory cells are formed by a third combination of work function metals or a third threshold voltage. Figure 14 ); and the gate structures of transistors WPG1 and WPG2 in each of the four memory cells are formed by a fourth combination of work function metals or a fourth threshold voltage. Figure 14 ).

[0076] Figure 15 Another example circuit diagram of a memory cell 1500 according to some embodiments is shown, which includes seven transistors operatively forming a 7T SRAM cell. Except that transistors WPG1 and WPG2 of memory cell 1500 are configured as p-type and transistor RPG is configured as n-type, memory cell 1500 is similar to memory cell 100 (e.g., including a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first write transmission gate transistor WPG1, a second write transmission gate transistor WPG2, and a read transmission gate transistor RPG).

[0077] In some embodiments, these seven transistors can be physically formed using the CFET structure described above. For example, transistors PU1, PU2, WPG1, and WPG2 can be formed at a first front-side layer, and transistors PD1, PD2, and RPG can be formed at a second front-side layer above the first front-side layer. Specifically, transistors PD1 and PU1 are vertically aligned with each other; transistors PD2 and PU2 are vertically aligned with each other; and transistor RPG is vertically aligned with one of transistors WPG1 or WPG2.

[0078] Figure 16 An example circuit diagram of a memory cell 1600 according to some embodiments is shown. The memory cell 1600 includes eight transistors operatively forming an 8T SRAM cell. The memory cell 1600 includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first write transmission gate transistor WPG1, a second write transmission gate transistor WPG2, a first read transmission gate transistor RPG1, and a second read transmission gate transistor RPG2.

[0079] In some embodiments, transistors PU1, PU2, RPG1, and RPG2 of the memory cell 1600 are configured as p-type, and transistors PD1, PD2, WPG1, and WPG2 are configured as n-type. These eight transistors can be physically formed using the CFET structure described above. For example, transistors PU1, PU2, RPG1, and RPG2 can be formed at a first front-side layer, and transistors PD1, PD2, WPG1, and WPG2 can be formed at a second front-side layer above the first front-side layer. Specifically, transistors PD1 and PU1 are vertically aligned with each other; transistors PD2 and PU2 are vertically aligned with each other; transistors RPG1 and WPG1 are vertically aligned with each other; and transistors RPG2 and WPG2 are vertically aligned with each other.

[0080] Figure 17 Another example circuit diagram of a memory cell 1700 according to some embodiments is shown. The memory cell 1700 includes eight transistors operatively forming an 8T SRAM cell. The memory cell 1700 includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first write transmission gate transistor WPG1, a second write transmission gate transistor WPG2, a first read transmission gate transistor RPG1, and a second read transmission gate transistor RPG2.

[0081] In some embodiments, transistors PU1, PU2, WPG1, and WPG2 of the memory cell 1700 are configured as p-type, and transistors PD1, PD2, RPG1, and RPG2 are configured as n-type. These eight transistors can be physically formed using the CFET structure described above. For example, transistors PU1, PU2, WPG1, and WPG2 can be formed at a first front-side layer, and transistors PD1, PD2, RPG1, and RPG2 can be formed at a second front-side layer above the first front-side layer. Specifically, transistors PD1 and PU1 are vertically aligned with each other; transistors PD2 and PU2 are vertically aligned with each other; transistors RPG1 and WPG1 are vertically aligned with each other; and transistors RPG2 and WPG2 are vertically aligned with each other.

[0082] Figure 18 and Figure 19 Example Figure 1800 is shown, illustrating a memory array comprising a plurality of memory cells 1600 according to some embodiments. For example, the memory array may include four memory cells 1600 (such as the first memory cell, second memory cell, and fourth memory cell shown). Specifically, Figure 18 The first level of mapping 1800 is shown (corresponding transistors RPG1, RPG2, PU1, and PU2 configured to form the first through fourth memory cells 1600). Figure 19The second and higher levels of Figure 1800 are shown (set to form the corresponding transistors WPG1, WPG2, PD1 and PD2 of the first to fourth memory cells 1600), wherein the first and second levels can be vertically aligned with each other.

[0083] For the sake of simplicity, Figure 18 and Figure 19 The corresponding active regions of eight transistors in each of the four memory cells 1600 are shown (e.g., Figure 18 The active regions 1802, 1804, 1806 and 1808, and Figure 19 The active regions 1902, 1904, 1906 and 1908) and the gate structure (e.g. Figure 18 The gate structures 1812, 1814, 1816 and 1818, and Figure 9 The gate structures described are 1912, 1914, 1916, and 1918, but this is not intended to limit the scope of this disclosure. As shown, in Figure 18 In this context, corresponding transistors RPG1 and / or RPG2 of two or more memory cells can share the same gate structure. For example, transistors RPG1 of the first and second memory cells share a first portion of gate structure 1812, and transistors RPG1 of the third and fourth memory cells share a second portion of gate structure 1812. Similarly, in Figure 19 In this configuration, the corresponding transistors WPG1 and / or WPG2 of two or more memory cells may share the same gate structure. In some embodiments, these four memory cells may be operatively configured along a common row (e.g., a WL) and along corresponding four columns (e.g., four pairs of BL / BLB).

[0084] Figure 20 The following is illustrated based on mapping 1800 according to some embodiments. Figures 18-19 A cross-sectional view of a portion of the semiconductor device formed. For example, Figure 20 The cross-sectional view is taken along line AA, such as... Figures 18-19 As shown. Specifically, line AA follows... Figure 18 The active region 1802 and Figure 19 The active region 1902 extends or is truncated along the first memory cell.

[0085] As shown, transistors PU2, PU1, RPG2, and RPG1 are formed in a first layer on the front side of the substrate, and transistors WPG2, PD2, PD1, and WPG1 are formed in a second layer above the first layer. Transistors PD2 and PU2 are vertically aligned with each other; transistors PD1 and PU1 are vertically aligned with each other; transistors WPG1 and RPG1 are vertically aligned with each other; and transistors WPG2 and RPG2 are vertically aligned with each other. In some embodiments, transistors PU2, PU1, RPG2, and RPG1 are formed of p-type, with the source / drain terminals of each transistor formed of a p-type epitaxial structure, and their gate terminals (or active gate structures) formed of one or more p-type work function metals; transistors WPG2, PD2, PD1, and WPG1 are formed of n-type, with the source / drain terminals of each transistor formed of an n-type epitaxial structure, and their gate terminals (or active gate structures) formed of one or more n-type work function metals.

[0086] Figure 21 A flowchart of an example method 2100 for forming a memory cell configured as a CFET structure is shown according to some embodiments of the present disclosure. For example, at least some operations (or steps) of method 2100 can be used to form a memory cell 100 in a CFET structure. Figure 1 ), memory unit 1500 ( Figure 15 ), memory unit 1600 ( Figure 16 ) or memory unit 1700 ( Figure 17 The CFET structure includes multiple p-type transistors disposed on a first layer on the front side of the substrate and multiple n-type transistors disposed on a second layer on the front side of the substrate.

[0087] It should be understood that method 2100 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that... Figure 2 Additional operations may be provided before, during, and after method 2100. And only a few of these additional operations may be briefly described here. In some embodiments, the operation of method 2100 may be associated with cross-sectional views of the CFET structure 2200 at various manufacturing stages, as shown below. Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 and Figure 30 As shown, this will be discussed in further detail below.

[0088] In brief, method 2100 begins with operation 2102, forming multiple dummy gate structures over a stack comprising a lower portion and an upper portion. The lower portion comprises multiple first nanostructures and multiple second nanostructures stacked alternately on top of each other, and the upper portion comprises multiple third nanostructures and fourth nanostructures stacked alternately on top of each other. The first and third nanostructures may be formed of a first semiconductor material, and the second and fourth nanostructures may be formed of a second semiconductor material. Furthermore, the lower and upper portions may be separated from each other by a fifth nanostructure formed of a third semiconductor material. Method 2100 continues to operation 2104, etching the stack to form source / drain recesses. Method 2100 continues to operation 2106, laterally recessing the second and fourth nanostructures. Method 2100 continues to operation 2108, forming multiple internal spacers. Method 2100 continues to operation 2110, selectively removing the fifth nanostructure. Method 2100 continues to operation 2112, forming a dielectric layer between the lower and upper portions. Method 2100 continues to operation 2114, forming a plurality of p-type epitaxial structures in the lower portion and a plurality of n-type epitaxial structures in the upper portion. Method 2100 continues to operation 2116, forming a first active gate structure in the lower portion and a second active gate structure in the upper portion. Method 2100 continues to operation 2118, forming a plurality of interconnect structures.

[0089] Corresponding to Figure 21 Operation 2102, Figure 22 This is a cross-sectional view of a CFET structure 2200 at one of the various manufacturing stages, which includes multiple dummy gate structures 2202 above a stack 2204. Figure 22 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0090] In some embodiments, a stack 2204 may be formed over a semiconductor substrate 2201, and then a dummy gate structure 2202 may be formed over the stack 2204. The stack 2204 may extend along the X direction, and the dummy gate structure 2202 may extend along the Y direction to cross or otherwise traverse the stack 2204. The stack 2204 includes a lower portion 2204-1 and an upper portion 2204-2, which may correspond to a first level and a second level on the front side of the substrate, respectively. The lower portion 2204-1 includes a plurality of first nanostructures 2206 and a plurality of second nanostructures 2208 alternately stacked on top of each other, and the upper portion 2204-2 includes a plurality of third nanostructures 2210 and a plurality of four nanostructures 2212 alternately stacked on top of each other.

[0091] The substrate 2201, the first nanostructure 2206, and the third nanostructure 2210 can be formed of a first semiconductor material (e.g., silicon (Si)), while the second nanostructure 2208 and the fourth nanostructure 2212 can be formed of a second semiconductor material (e.g., silicon-germanium (Si)). 1-x Ge x Furthermore, the lower portion 2204-1 and the upper portion 2204-2 are formed by a third semiconductor material (e.g., silicon-germanium (Si)). 1-y Ge y The fifth nanostructure 2214 formed is separated from each other. In some embodiments, the molar ratio "x" of the second semiconductor material can be less than 0.5, and the molar ratio "y" of the third semiconductor material can be greater than 0.5.

[0092] Nanostructures 2206 to 2212 can be epitaxially grown from semiconductor substrate 2201. For example, each of nanostructures 2206 to 2212 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD (MOCVD)), and / or other suitable epitaxial growth processes. After growing nanostructures 2206 to 2212 as a blanket stack on substrate 2201, the blanket stack can be patterned to form Figure 22 The stack 2204 shown has a longitudinal direction in the X direction and a relatively narrow width in the Y direction. After the stack 2204 is formed, a dummy gate structure 2202 comprising a dummy gate dielectric (e.g., silicon oxide) and a dummy gate material (e.g., polysilicon) is formed across the stack 2204.

[0093] Corresponding to Figure 21 Operation 2104, Figure 23 This is a cross-sectional view of the CFET structure 2200 at one of the various manufacturing stages, in which the source / drain recesses 2220 are formed. Figure 23 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0094] To form the source / drain recesses 2220, a pair of gate spacers 2216 can be formed on opposite sidewalls of the dummy gate structure 2202. Next, using the dummy gate structure 2202 and the gate spacers 2216 as a mask, the stack 2204 is patterned again using an anisotropic etching process to form the source / drain recesses 2220. This anisotropic etching process can include reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof.

[0095] Corresponding to Figure 21 Operation 2106, Figure 24This is a cross-sectional view of the CFET structure 2200 at one of the various manufacturing stages, in which the second nanostructure 2208 and the fourth nanostructure 2212 are laterally recessed. Figure 24 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0096] As shown, the second nanostructure 2208 and the fourth nanostructure 2212 (made of Si) are removed (e.g., etched) using a "pull-back" process. 1-x Ge x The respective ends of each of the nanostructures 2205 and 2212 are retracted by a pullback distance. For example, the pullback process may include an isotropic etching process using hydrogen chloride (HCl) gas to etch SiGe (e.g., Si) with a lower Ge content. 1-x Ge x ), without attacking Si or SiGe with a high Ge content (e.g., Si). 1-y Ge y Therefore, in this process, the nanostructures 2206(Si), 2210(Si), and 2214(Si) 1-y Ge y It can remain basically intact and can form multiple recesses 2224, each recess extending inward from the source / drain recess 2220.

[0097] Corresponding to Figure 21 Operation 2108, Figure 25 This is a cross-sectional view of the CFET structure 2200, which includes multiple internal spacers 2222, at one of the various manufacturing stages. Figure 25 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0098] The internal spacer 2222 can be formed by filling the recess 2224 with a dielectric material. For example, the internal spacer 2222 can be deposited using, for example, a conformal deposition process and subsequent isotropic or anisotropic etchback to remove excess spacer material on the sidewalls of the stack 2204. The dielectric material used to form the internal spacer 2222 includes silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxynitride, or any other type of dielectric material suitable for forming insulating gate sidewall spacers of transistors (e.g., a dielectric material with a dielectric constant k less than about 5).

[0099] Corresponding to Figure 21 Operation 2110, Figure 26 This is a cross-sectional view of the CFET structure 2200 at one of the various manufacturing stages, in which the fifth nanometer structure 2214 has been removed. Figure 26The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0100] After forming the internal spacer 2222, Si can be etched. 1-y Ge y The fifth nanostructure 2214 is selectively removed using an isotropic etching process that does not attack Si. Therefore, the first nanostructure 2206 (Si) and the third nanostructure 2210 (Si) remain substantially intact, while the fifth nanostructure 2214 (Si) remains largely intact. 1-y Ge y The second nanostructure 2208 (Si) can be completely removed. 1-x Ge x ) and the fourth nanostructure 2212 (Si 1-x Ge x The remaining portion can be preserved under the protection of the internal spacer 2220.

[0101] Corresponding to Figure 21 Operation 2112, Figure 27 This is a cross-sectional view of the CFET structure 2200, including the dielectric layer 2230, at one of the various manufacturing stages. Figure 27 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0102] After removing the fifth nanostructure 2214, a space is formed between the lower portion 2204-1 and the upper portion 2204-2. A dielectric layer 2230 can be formed by filling this space with a dielectric material. The dielectric material used to form the dielectric layer 2230 includes silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxynitride, or any other type of dielectric material suitable for forming an insulating structure of a transistor (e.g., a dielectric material with a dielectric constant k less than about 5).

[0103] Corresponding to Figure 21 Operation 2114, Figure 28 This is a cross-sectional view of the CFET structure 2200 at one of the various manufacturing stages, including multiple first epitaxial structures 2232 and multiple second epitaxial structures 2234. Figure 28 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0104] As shown, a pair of first epitaxial structures 2232 are coupled to the ends of each first nanostructure 2206; and a pair of second epitaxial structures 2234 are coupled to the ends of each third nanostructure 2210. The first epitaxial structures 2232 can be formed by a first epitaxial growth process, followed by a second epitaxial growth process for forming the second epitaxial structures 2234. Furthermore, one or more dielectric layers 2236 can be formed between the first and second epitaxial growth processes to electrically isolate the first epitaxial structures 2232 and 2234. Each of the first and second epitaxial growth processes can include selective epitaxial growth (SEG), CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epitaxial processes. Specifically, the first epitaxial structure 2232 can be grown from the first nanostructure 2206, and the second epitaxial structure 2234 can be grown from the third nanostructure 2210.

[0105] The first epitaxial structure 2232 and the second epitaxial structure 2234 may each comprise silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), any other suitable material, or a combination thereof. Furthermore, in-situ doping (ISD) may be applied during the formation of each of the first epitaxial structure 2232 and the second epitaxial structure 2234. For example, the first epitaxial structure 2232 may be doped by implanting a p-type dopant (e.g., boron (B)); and the second epitaxial structure 2234 may be doped by implanting an n-type dopant (e.g., arsenic (As), phosphorus (P)). In some embodiments, the first epitaxial structure 2232 may be coupled to each first nanostructure 2206 via a lightly doped region 2233 (e.g., SiGeB); and the second epitaxial structure 2234 may be coupled to each third nanostructure 2210 via a lightly doped region 2235 (e.g., SiP).

[0106] Corresponding to Figure 21 Operation 2116, Figure 29 This is a cross-sectional view of the CFET structure 2200 at one of the various manufacturing stages, including the first active gate structure 2242 and the second active gate structure 224. Figure 29 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0107] As shown, a first active gate structure 2242 surrounds each first nanostructure 2206; a second active gate structure 2244 surrounds each third nanostructure 2210. To form the first active gate structure 2242 and the second active gate structure 2244, the dummy gate structure 2202, the remaining portions of the second nanostructure 2208, and the remaining portions of the fourth nanostructure 2212 are removed. Therefore, a first gate trench exposing each first nanostructure 2206 can be formed in the lower portion 2204-1 (e.g., the first layer); and a second gate trench exposing each third nanostructure 2210 can be formed in the upper portion 2204-2 (e.g., the second layer). Next, the first active gate structure 2242 can be formed in the first gate trench to surround each first nanostructure 2206; and the second active gate structure 2244 can be formed in the second gate trench to surround each third nanostructure 2210.

[0108] In some embodiments, the first active gate structure 2242 may include a first gate dielectric and a first gate metal; the second active gate structure 2244 may include a second gate dielectric and a second gate metal. The first / second gate dielectric may be formed of different high-k dielectric materials or similar high-k dielectric materials. Exemplary high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The first / second gate dielectric may include a stack of multiple high-k dielectric materials. The first gate metal may include one or more p-type work function metals, which may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof; and the second gate metal may include one or more n-type work function metals, which may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.

[0109] After forming the first and second active gate structures 2242-2244, at least one p-type transistor can be formed at the first level and at least one n-type transistor can be formed at the second level. The p-type transistor can be operatively formed based on the first nanostructure 2206, the gate structure 2242, and a pair of first epitaxial structures 2232, for example, they can correspond to the nanostructure 1010, the gate structure 1012, and the epitaxial structures 1014-1016, respectively. Figure 10The n-type transistor can be operatively formed based on a third nanostructure 2210, a gate structure 2244, and a pair of second epitaxial structures 2234, for example, which can correspond to nanostructure 1020, gate structure 1022, and epitaxial structures 1024-1026, respectively. Figure 10 ).

[0110] Corresponding to Figure 21 Operation 2118, Figure 30 This is a cross-sectional view of a CFET structure 2200 including a first connection structure 2252 and a second connection structure 2254 at one of the various manufacturing stages. Figure 30 The cross-sectional view is taken along the length direction of the active region of the CFET structure 2200 (e.g., the X direction mentioned above).

[0111] As shown, the first connection structure 2252 is coupled to a corresponding one of the first epitaxial structures 2232; and the second connection structure 2254 is coupled to a corresponding one of the second epitaxial structures 2234. For example, the first connection structure 2252 may be formed below the first epitaxial structure 2232; and the second connection structure 2254 may be formed above the second epitaxial structure 2234. For example, the first connection structure 2252 may surround the first epitaxial structure 2232; and the second connection structure 2254 may surround the second epitaxial structure 2234. In some embodiments, the first connection structure 2252 and the second connection structure 2254 may each be configured as an MD as described above, which may include titanium, aluminum, nickel, tungsten, tantalum, or other suitable metallic materials.

[0112] Figure 31 A flowchart of another example method 3100 for forming a memory cell configured as a CFET structure according to some embodiments of the present disclosure is shown. For example, at least some operations (or steps) of method 3100 can be used to form memory cell 100 in a CFET structure. Figure 1 ), memory unit 1500 ( Figure 15 ), memory unit 1600 ( Figure 16 ) or memory unit 1700 ( Figure 17 The CFET structure includes multiple p-type transistors disposed on a first layer on the front side of the substrate and multiple n-type transistors disposed on a second layer on the front side of the substrate.

[0113] It should be understood that method 3100 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that... Figure 3 Additional operations may be provided before, during, and after method 3100. And only a few of these additional operations may be briefly described here. In some embodiments, the operation of method 3100 may be associated with cross-sectional views of the CFET structure 3200 at various manufacturing stages, such as... Figure 32 , Figure 33 , Figure 34 , Figure 35 , Figure 36 , Figure 37 , Figure 38 , Figure 39 , Figure 40 , Figure 41 and Figure 42 As shown, this will be discussed in further detail below.

[0114] In brief, method 3100 begins with operation 3102, forming multiple dummy gate structures on a stack comprising a lower portion and an upper portion. The lower portion comprises multiple first nanostructures and multiple second nanostructures stacked alternately on top of each other, and the upper portion comprises multiple third nanostructures and fourth nanostructures stacked alternately on top of each other. The first and third nanostructures may be formed of a first semiconductor material, and the second and fourth nanostructures may be formed of a second semiconductor material. Furthermore, the lower and upper portions may be separated from each other by a fifth nanostructure formed of a third semiconductor material. Method 3100 continues to operation 3104, etching the stack to form source / drain recesses. 3100 continues to operation 3106, removing the second and fourth nanostructures. Method 3100 continues to operation 3108, forming multiple sacrificial oxide layers, each sacrificial oxide layer being located between adjacent first nanostructures or adjacent third nanostructures. Method 3100 continues to operation 3110, laterally recessing the sacrificial oxide layers. Method 3100 continues to operation 3112, forming multiple internal spacers. Method 3100 continues to operation 3114, selectively removing the fifth nanometer structure. Method 3100 continues to operation 3116, forming a dielectric layer between the lower and upper portions. Method 3100 continues to operation 3118, forming multiple p-type epitaxial structures in the lower portion and multiple n-type epitaxial structures in the upper portion. Method 3100 continues to operation 3120, forming a first active gate structure in the lower portion and a second active gate structure in the upper portion. Method 3100 continues to operation 3122, forming multiple interconnect structures.

[0115] Corresponding to Figure 31 Operation 3102, Figure 32 This is a cross-sectional view of a CFET structure 3200 at one of the various manufacturing stages, which includes multiple dummy gate structures 3202 above a stack 3204. Figure 32 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0116] In some embodiments, a stack 3204 may be formed over a semiconductor substrate 3201, and a dummy gate structure 3202 may be formed over the stack 3204. The stack 3204 may extend along the X direction, and the dummy gate structure 3202 may extend along the Y direction to cross or otherwise traverse the stack 3204. The stack 3204 includes a lower portion 3204-1 and an upper portion 3204-2, which may correspond to a first level and a second level on the front side of the substrate, respectively (e.g., ...). Figure 10 , Figure 14 , Figure 24 The lower portion 3204-1 includes a plurality of first nanostructures 3206 and a plurality of second nanostructures 3208 alternately stacked on top of each other, and the upper portion 3204-2 includes a plurality of third nanostructures 3210 and a plurality of four nanostructures 3212 alternately stacked on top of each other.

[0117] The substrate 3201, the first nanostructure 3206, and the third nanostructure 3210 can be formed of a first semiconductor material (e.g., silicon (Si)), while the second nanostructure 3208 and the fourth nanostructure 3212 can be formed of a second semiconductor material (e.g., silicon-germanium (Si)). 1-x Ge x Furthermore, the lower portion 3204-1 and the upper portion 3204-2 are formed by a third semiconductor material (e.g., silicon-germanium (Si)). 1-y Ge y The fifth nanostructure 3214 formed is separated from each other. In some embodiments, the molar ratio "x" of the second semiconductor material can be less than 0.5, and the molar ratio "y" of the third semiconductor material can be greater than 0.5.

[0118] Nanostructures 3206 to 3212 can be epitaxially grown from semiconductor substrate 3201. For example, each of nanostructures 3206 to 3212 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD (MOCVD)), and / or other suitable epitaxial growth processes. After growing nanostructures 3206 to 3212 as a blanket stack on substrate 3201, the blanket stack can be patterned to form Figure 32 The stack 3204 shown has a longitudinal direction in the X direction and a relatively narrow width in the Y direction. After the stack 3204 is formed, a dummy gate structure 3202 comprising a dummy gate dielectric (e.g., silicon oxide) and a dummy gate material (e.g., polysilicon) is formed across the stack 3204.

[0119] Corresponding to Figure 31 Operation 3104, Figure 33This is a cross-sectional view of the CFET structure 3200 at one of the various manufacturing stages, in which the source / drain recesses 3220 are formed. Figure 33 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0120] To form the source / drain recesses 3220, a pair of gate spacers 3216 can be formed on opposite sidewalls of the dummy gate structure 3202. Next, using the dummy gate structure 3202 and the gate spacers 3216 as a mask, the stack 3204 is patterned again using an anisotropic etching process to form the source / drain recesses 3220. This anisotropic etching process can include reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof.

[0121] Corresponding to Figure 31 Operation 3106, Figure 34 This is a cross-sectional view of the CFET structure 3200 at one of the various manufacturing stages, with the second nanostructure 3208 and the fourth nanostructure 3212 removed. Figure 34 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0122] In some embodiments, the second nanostructure 3208 and the fourth nanostructure 3212 may be selectively removed (e.g., etched), while the first nanostructure 3206, the third nanostructure 3210, and the fifth nanostructure 3214 remain substantially intact. The second nanostructure 3208 and the fourth nanostructure 3212 can be completely removed using an isotropic etching process with hydrogen chloride (HCl) gas, which etches SiGe (e.g., Si) with a low Ge content. 1-x Ge x ), without attacking Si or SiGe with a high Ge content (such as Si). 1-y Ge y Therefore, multiple spaces 3223 can be formed. For example... Figure 34 As shown, each space 3223 can be vertically placed between the substrate 3201 and the bottommost of the first nanostructure 3206, between adjacent first nanostructures 3206, between the topmost of the first nanostructure 3206 and the fifth nanostructure 3214, between the fifth nanostructure 3214 and the bottommost of the third nanostructure 3210, or between adjacent third nanostructures 3210.

[0123] Corresponding to Figure 31 Operation 3108, Figure 35 This is a cross-sectional view of a CFET structure 3200 comprising multiple sacrificial oxide layers 3224 at one of the various manufacturing stages. Figure 35 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0124] As shown, sacrificial oxide layers 3224 are formed at least in spaces 3223. In some embodiments, the sacrificial oxide layers 3224 may be deposited using, for example, a conformal deposition process to deposit oxide material, and one or more subsequent isotropic or anisotropic etching processes may be used to remove excess oxide material from the sidewalls of the stack 3204. Thus, as Figure 35 As shown, each of the sacrificial oxide layers 3224 can be vertically placed between the substrate 3201 and the bottommost first nanostructure 3206, between adjacent first nanostructures 3206, between the topmost first nanostructure 3206 and the fifth nanostructure 3214, between the fifth nanostructure 3214 and the bottommost third nanostructure 3210, or between adjacent third nanostructures 3210.

[0125] Corresponding to Figure 31 Operation 3110, Figure 36 This is a cross-sectional view of the CFET structure 3200 at one of the various manufacturing stages, in which the sacrificial oxide layer 3224 is laterally recessed. Figure 36 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0126] As shown, a "pull-back" process is used to remove (e.g., etch) the corresponding ends of each sacrificial oxide layer 3224 to pull back each sacrificial oxide layer 3224 by a pull-back distance. For example, the pull-back process may include an isotropic etching process using hydrofluoric acid (HF) gas, which etches silicon oxide without attacking Si or SiGe with a higher Ge content (e.g., Si). 1- y Ge y Therefore, in this process, the nanostructures 3206(Si), 3210(Si), and 3214(Si) 1-y Ge y It can remain basically intact and can form multiple recesses 3221, each recess extending inward from the source / drain recess 3220.

[0127] Corresponding to Figure 31 Operation 3112, Figure 37 This is a cross-sectional view of a CFET structure 3200 including multiple internal spacers 3222 at one of the various manufacturing stages. Figure 37 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0128] The internal spacer 3222 can be formed by filling the recess 3221 with a dielectric material. For example, the internal spacer 3222 can be deposited using, for example, a conformal deposition process and a subsequent isotropic or anisotropic etch-back to remove excess spacer material on the sidewalls of the stack 3204. The dielectric material used to form the internal spacer 3222 includes silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxynitride, or any other type of dielectric material suitable for forming insulating gate sidewall spacers of transistors (e.g., a dielectric material with a dielectric constant k less than about 5).

[0129] Corresponding to Figure 31 Operation 3114, Figure 38 This is a cross-sectional view of the CFET structure 3200 at one of the various manufacturing stages, with the fifth nanometer structure 3214 removed. Figure 38 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0130] After forming the internal spacer 3222, Si can be etched. 1-y Ge y The fifth nanostructure 3214 is selectively removed using an isotropic etching process that does not attack Si. Therefore, the first nanostructure 3206 (Si) and the third nanostructure 3210 (Si) remain largely intact, while the fifth nanostructure 3214 (Si) remains largely intact. 1-y Ge y The sacrificial oxide layer 3224 can be completely removed, and the remaining portion of the sacrificial oxide layer 3224 can be retained under the protection of the internal spacer 3220.

[0131] Corresponding to Figure 31 Operation 3116, Figure 39 This is a cross-sectional view of the CFET structure 3200, including the dielectric layer 3230, at one of the various manufacturing stages. Figure 39 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0132] After removing the fifth nanostructure 3214, a space is formed between the lower portion 3204-1 and the upper portion 3204-2. A dielectric layer 3230 can be formed by filling this space with a dielectric material. The dielectric material used to form the dielectric layer 3230 includes silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxynitride, or any other type of dielectric material suitable for forming an insulating structure of a transistor (e.g., a dielectric material with a dielectric constant k less than about 5).

[0133] Corresponding to Figure 31 Operation 3118, Figure 40This is a cross-sectional view of a CFET structure 3200 comprising multiple first epitaxial structures 3232 and multiple second epitaxial structures 3234 at one of the various manufacturing stages. Figure 40 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0134] As shown, a pair of first epitaxial structures 3232 are coupled to the ends of each first nanostructure 3206; and a pair of second epitaxial structures 3234 are coupled to the ends of each third nanostructure 3210. The first epitaxial structures 3232 can be formed by a first epitaxial growth process, followed by a second epitaxial growth process for forming the second epitaxial structures 3234. Furthermore, one or more dielectric layers 3230 can be formed between the first and second epitaxial growth processes to electrically isolate the first epitaxial structures 3232 and the second epitaxial structures 3234. Each of the first and second epitaxial growth processes can include selective epitaxial growth (SEG), CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epitaxial processes. Specifically, the first epitaxial structures 3232 can be grown from the first nanostructure 3206, and the second epitaxial structures 3234 can be grown from the third nanostructure 3210.

[0135] The first epitaxial structure 3232 and the second epitaxial structure 3234 may each comprise silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), any other suitable material, or a combination thereof. Furthermore, in-situ doping (ISD) may be applied during the formation of each of the first epitaxial structure 3232 and the second epitaxial structure 3234. For example, the first epitaxial structure 3232 may be doped by implanting a p-type dopant (e.g., boron (B)); and the second epitaxial structure 3234 may be doped by implanting an n-type dopant (e.g., arsenic (As), phosphorus (P)). In some embodiments, the first epitaxial structure 3232 may be coupled to each first nanostructure 3206 via a lightly doped region 3233 (e.g., SiGeB); and the second epitaxial structure 3234 may be coupled to each third nanostructure 3210 via a lightly doped region 3235 (e.g., SiP).

[0136] Corresponding to Figure 31 Operation 3120, Figure 41 This is a cross-sectional view of the CFET structure 3200 at one of the various manufacturing stages, including the first active gate structure 3242 and the second active gate structure 324. Figure 41The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0137] As shown, a first active gate structure 3242 surrounds each first nanostructure 3206; a second active gate structure 3244 surrounds each third nanostructure 3210. To form the first active gate structure 3242 and the second active gate structure 3244, the remaining portions of the dummy gate structure 3202 and the sacrificial oxide layer 3224 are removed. Therefore, a first gate trench exposing each first nanostructure 3206 can be formed in the lower portion 3204-1 (e.g., the first level); and a second gate trench exposing each third nanostructure 3210 can be formed in the upper portion 3204-2 (e.g., the second level). Next, the first active gate structure 3242 can be formed in the first gate trench to surround each first nanostructure 3206; and the second active gate structure 3244 can be formed in the second gate trench to surround each third nanostructure 3210.

[0138] In some embodiments, the first active gate structure 3242 may include a first gate dielectric and a first gate metal; the second active gate structure 3244 may include a second gate dielectric and a second gate metal. The first / second gate dielectric may be formed of different high-k dielectric materials or similar high-k dielectric materials. Exemplary high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The first / second gate dielectric may include a stack of multiple high-k dielectric materials. The first gate metal may include one or more p-type work function metals, which may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof; and the second gate metal may include one or more n-type work function metals, which may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.

[0139] After forming the first and second active gate structures 3242-3244, at least one p-type transistor can be formed at the first level, and at least one n-type transistor can be formed at the second level. The p-type transistor can be operatively formed based on the first nanostructure 3206, the gate structure 3242, and a pair of first epitaxial structures 3232, for example, they can correspond to the nanostructure 1010, the gate structure 1012, and the epitaxial structures 1014-1016, respectively. Figure 10 , Figure 14 , Figure 24The n-type transistor can be operatively formed based on a third nanostructure 3210, a gate structure 3244, and a pair of second epitaxial structures 3234, for example, which can correspond to nanostructure 1020, gate structure 1022, and epitaxial structures 1024-1026, respectively. Figure 10 , Figure 14 , Figure 24 ).

[0140] Corresponding to Figure 31 Operation 3122, Figure 42 This is a cross-sectional view of the CFET structure 3200, including the first connection structure 3252 and the second connection structure 3254, at one of the various manufacturing stages. Figure 42 The cross-sectional view is taken along the length direction of the active region of the CFET structure 3200 (e.g., the X direction mentioned above).

[0141] As shown, the first connecting structure 3252 is coupled to a corresponding one of the first epitaxial structures 3232; and the second connecting structure 3254 is coupled to a corresponding one of the second epitaxial structures 3234. For example, the first connecting structure 3252 may be formed below the first epitaxial structure 3232; and the second connecting structure 3254 may be formed above the second epitaxial structure 3234. As another example, the first connecting structure 3252 may surround the first epitaxial structure 3232; and the second connecting structure 3254 may surround the second epitaxial structure 3234. In some embodiments, the first connecting structure 3252 and the second connecting structure 3254 may each be configured as an MD as described above, which may include titanium, aluminum, nickel, tungsten, tantalum, or other suitable metallic materials.

[0142] In one aspect of this disclosure, a memory device is disclosed. The memory device includes: a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on the first side of the substrate, all of which have first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, all of which have second conductivity, wherein the first level is disposed perpendicular to the second level; wherein the first transistor to the seventh transistor are operatively configured to form static random access memory (SRAM) cells.

[0143] In some embodiments, the first to third transistors are formed based on a first active region, a first gate portion, a second gate portion, a third gate portion, and a fourth gate portion disposed at a first level, and wherein the fourth to seventh transistors are formed based on a second active region, a fifth gate portion, a sixth gate portion, a seventh gate portion, and an eighth gate portion disposed at a second level.

[0144] In some embodiments, the first active region is vertically aligned with the second active region, the first gate portion is vertically aligned with the fifth gate portion, the second gate portion is vertically aligned with the sixth gate portion, the third gate portion is vertically aligned with the seventh gate portion, and the fourth gate portion is vertically aligned with the eighth gate portion.

[0145] In some embodiments, the first transistor and the second transistor are operably used as pull-up transistors for the SRAM cell, the third transistor is operably used as a read transmission gate transistor for the SRAM cell, the fourth transistor and the seventh transistor are operably used as write transmission gate transistors for the SRAM cell, and the fifth transistor and the sixth transistor are operably used as pull-down transistors for the SRAM cell.

[0146] In some embodiments, the first conductivity is p-type and the second conductivity is n-type, and wherein the second layer is vertically located above the first layer on the first side of the substrate.

[0147] In some embodiments, the first transistor and the second transistor are operably used as pull-down transistors of the SRAM cell, the third transistor is operably used as a read transmission gate transistor of the SRAM cell, the fourth transistor and the seventh transistor are operably used as write transmission gate transistors of the SRAM cell, and the fifth transistor and the sixth transistor are operably used as pull-up transistors of the SRAM cell.

[0148] In some embodiments, the first conductivity is n-type and the second conductivity is p-type, wherein the second layer is vertically located below the first layer on the first side of the substrate.

[0149] In some embodiments, the fifth transistor and the sixth transistor are arranged adjacent to each other in the lateral direction, and the fourth transistor and the seventh transistor are arranged in the lateral direction on opposite sides of the fifth transistor and the sixth transistor.

[0150] In some embodiments, the third transistor is vertically aligned with one of the fourth or seventh transistors.

[0151] In some embodiments, the memory device further includes: a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure, formed at a third level on a first side of the substrate, wherein the third level is disposed perpendicular to the first level and the second level; and a fifth interconnect structure, a sixth interconnect structure, a seventh interconnect structure, a first internal contact structure, and a second internal contact structure, formed at a level on a second side of the substrate; wherein each of the first interconnect structure to the seventh interconnect structure and the first internal contact structure to the second internal contact structure extends in a lateral direction, wherein the first transistor to the third transistor and the fourth transistor to the seventh transistor are configured relative to each other.

[0152] In some embodiments, a first interconnect structure is operably used as a write word line of an SRAM cell, a second interconnect structure is operably used as a first write bit line of an SRAM cell, a third interconnect structure is operably used as a second write bit line of an SRAM cell, and a fourth interconnect structure is operably used as a first power rail of an SRAM cell carrying a reference voltage.

[0153] In some embodiments, the fifth interconnect structure is operably used as a second power rail carrying the power supply voltage of the SRAM cell, the sixth interconnect structure is operably used as a read word line of the SRAM cell, and the seventh interconnect structure is operably used as a read bit line of the SRAM cell.

[0154] In another aspect of this disclosure, a memory device is disclosed. The memory device includes: a memory array comprising a plurality of memory cells; wherein each of the plurality of memory cells includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed on one side of a substrate; wherein the first to third transistors of each of the plurality of memory cells having p-type conductivity are formed at a first level on the side, and the fourth to seventh transistors of each of the plurality of memory cells having n-type conductivity are formed at a second level on the side.

[0155] In some embodiments, the first transistor to the third transistor are formed above four first gate structures extending along a first lateral direction, the first transistor and the second transistor are disposed adjacent to each other along a second lateral direction perpendicular to the first lateral direction, and the third transistor is disposed adjacent to the first transistor or the second transistor along the second lateral direction.

[0156] In some embodiments, the fourth to seventh transistors are formed above four second gate structures extending along a first lateral direction, the fifth and sixth transistors are disposed adjacent to each other along a second lateral direction, and the fourth and seventh transistors are disposed on opposite sides of the fifth and sixth transistors along the second lateral direction.

[0157] In some embodiments, the third transistor is vertically aligned with the fourth or seventh transistor.

[0158] In some embodiments, a first memory cell among a plurality of memory cells is formed based on a first active region and a first group of four gate structures at a first level, and a second active region and a second group of four gate structures at a second level, and a second memory cell among a plurality of memory cells is formed based on a third active region and a third group of four gate structures at a first level, and a fourth active region and a fourth group of four gate structures at a second level.

[0159] In some embodiments, the first set of gate structures to the fourth set of gate structures extend along a first lateral direction, the first active region to the fourth active region extend along a second lateral direction perpendicular to the first lateral direction, and wherein the first active region and the third active region are spaced apart from each other along the first lateral direction, and the second active region and the fourth active region are spaced apart from each other along the first lateral direction.

[0160] In another aspect of this disclosure, a method for forming a semiconductor device is disclosed. The method includes: forming a first active region extending along a first lateral direction at a first layer on a first side of a substrate; forming a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure at the first layer, the first gate structure to the fourth gate structure extending along a second lateral direction perpendicular to the first lateral direction and passing through the first active region; forming a second active region extending along the first lateral direction at a second layer above the first layer on the first side; and forming a fifth gate structure, a sixth gate structure, a seventh gate structure, and an eighth gate structure at the second layer, the fifth gate structure to the eighth gate structure extending along the second lateral direction and traversing the second active region; wherein the first active region and the first gate structure to the fourth gate structure operably form a first transistor, a second transistor, and a third transistor having a first conductivity, and the second active region and the fifth gate structure to the eighth gate structure operably form a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor having a second conductivity.

[0161] In some embodiments, the method further includes: forming a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure at a third layer above a second layer on a first side, the first interconnect structure to the third interconnect structure extending along a first lateral direction; and forming a fifth interconnect structure, a sixth interconnect structure, a seventh interconnect structure, a first internal contact structure, and a second internal contact structure at a layer on a second side of the substrate, the fifth interconnect structure to the seventh interconnect structure and the first internal contact structure and the second internal contact structure extending along the first lateral direction; wherein the first interconnect structure is operably used as a write word line of a memory cell, the second interconnect structure is operably used as a first write bit line of a memory cell, the third interconnect structure is operably used as a second write bit line of a memory cell, and the fourth interconnect structure is operably used as a first power rail of a memory cell; and wherein the fifth interconnect structure is operably used as a second power rail carrying a power supply voltage of a memory cell, the sixth interconnect structure is operably used as a read word line of a memory cell, and the seventh interconnect structure is operably used as a read bit line of a memory cell.

[0162] As used herein, the terms “about” and “approximately” generally refer to the value of a given quantity that can vary depending on the specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “about” can refer to a given quantity of value, for example, varying within a range of 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0163] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A memory device, comprising: A substrate having a first side and a second side opposite to each other; A first transistor, a second transistor, and a third transistor are formed at a first level on the first side of the substrate, and the first transistor to the third transistor are all formed with first conductivity. as well as A fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor are formed at a second level on the first side of the substrate, and the fourth to the seventh transistors all have a second conductivity, wherein the first level is disposed perpendicular to the second level. The first to the seventh transistors are operable to form a static random access memory cell.

2. The memory device according to claim 1, wherein, The first transistor to the third transistor are formed based on a first active region, a first gate portion, a second gate portion, a third gate portion and a fourth gate portion disposed at the first level, and wherein the fourth transistor to the seventh transistor are formed based on a second active region, a fifth gate portion, a sixth gate portion, a seventh gate portion and an eighth gate portion disposed at the second level.

3. The memory device according to claim 2, wherein, The first active region is vertically aligned with the second active region, the first gate portion is vertically aligned with the fifth gate portion, the second gate portion is vertically aligned with the sixth gate portion, the third gate portion is vertically aligned with the seventh gate portion, and the fourth gate portion is vertically aligned with the eighth gate portion.

4. The memory device according to claim 1, wherein, The first transistor and the second transistor are operably used as pull-up transistors of the static random access memory (SRAM) cell, the third transistor is operably used as a read transmission gate transistor of the SRAM cell, the fourth transistor and the seventh transistor are operably used as write transmission gate transistors of the SRAM cell, and the fifth transistor and the sixth transistor are operably used as pull-down transistors of the SRAM cell.

5. The memory device according to claim 1, wherein, The first transistor and the second transistor are operably used as pull-down transistors of the static random access memory (SRAM) cell, the third transistor is operably used as a read transmission gate transistor of the SRAM cell, the fourth transistor and the seventh transistor are operably used as write transmission gate transistors of the SRAM cell, and the fifth transistor and the sixth transistor are operably used as pull-up transistors of the SRAM cell.

6. The memory device according to claim 1, wherein, The fifth transistor and the sixth transistor are arranged adjacent to each other in the lateral direction, and the fourth transistor and the seventh transistor are arranged on opposite sides of the fifth transistor and the sixth transistor in the lateral direction.

7. The memory device according to claim 1, further comprising: A first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure are formed at a third layer on the first side of the substrate, wherein the third layer is disposed perpendicularly to the first layer and the second layer; and A fifth interconnect structure, a sixth interconnect structure, a seventh interconnect structure, a first internal contact structure, and a second internal contact structure are formed at a layer on the second side of the substrate; Each of the first interconnect structure to the seventh interconnect structure and the first internal contact structure to the second internal contact structure extends in a lateral direction, wherein the first transistor to the third transistor and the fourth transistor to the seventh transistor are configured relative to each other.

8. The memory device according to claim 7, wherein, The first interconnect structure is operably used as a write word line of the static random access memory cell, the second interconnect structure is operably used as a first write bit line of the static random access memory cell, the third interconnect structure is operably used as a second write bit line of the static random access memory cell, and the fourth interconnect structure is operably used as a first power rail of the static random access memory cell carrying a reference voltage.

9. A memory device, comprising: A memory array, comprising multiple memory cells; Each of the plurality of memory cells includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed on one side of the substrate; In this configuration, the first to third transistors of each of the plurality of memory cells having p-type conductivity are formed at a first level on the side, and the fourth to seventh transistors of each of the plurality of memory cells having n-type conductivity are formed at a second level on the side.

10. A method for forming a semiconductor device, comprising: A first active region extending in a first lateral direction is formed at a first layer on a first side of the substrate; A first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are formed at the first level. The first gate structure to the fourth gate structure extend along a second lateral direction perpendicular to the first lateral direction and pass through the first active region. A second active region extending along the first lateral direction is formed at a second level above the first level on the first side; as well as A fifth gate structure, a sixth gate structure, a seventh gate structure, and an eighth gate structure are formed at the second level, wherein the fifth gate structure to the eighth gate structure extend along the second lateral direction and traverse the second active region; The first active region and the first to fourth gate structures are operably configured to form a first transistor, a second transistor, and a third transistor with first conductivity of a memory cell, and the second active region and the fifth to eighth gate structures are operably configured to form a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor with second conductivity of the memory cell.

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