Self-loading storage unit based on nonvolatile storage unit and storage array

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a self-loading storage unit based on a nonvolatile storage unit and a storage array. The self-loading storage unit comprises an SRAM (Static Random Access Memory) unit structure and a nonvolatile storage structure; the self-loading storage array comprises N rows and N columns of self-loading storage units and N peripheral circuits, the self-loading storage units in the same row share the same word line WL, share the same balance signal line EQ, share the same reset signal line RS, share the same first switching signal STRS and share the same second switching signal STRSN; the self-loading storage units in the same column share the same source line SL, share the same first bit line BL and share the same second bit line BLB; according to the self-loading storage array, the data configured in the configuration storage array circuit cannot be lost after the FPGA is powered down, and the data does not need to be read from an external configuration memory for operation during power-on.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a self-loading memory cell and memory array based on non-volatile memory cells, which can be used for FPGA configuration memory array circuits. Background Technology

[0002] With the development of my country's communications and medical fields, the demand for highly reliable programmable logic devices (PLDs) is becoming increasingly prominent. How to develop next-generation high-performance, high-reliability, low-power non-volatile FPGA core configuration arrays has become one of the hot research topics in the integrated circuit field.

[0003] There are two types of FPGAs: one is a volatile FPGA based on SRAM that requires external non-volatile memory, and the other is a non-volatile FPGA that stores the configuration in memory and does not require external non-volatile memory.

[0004] FPGAs based on SRAM technology are volatile FPGAs. They use an internal SRAM array to store configuration information and can be configured and erased an unlimited number of times. This is currently the mainstream FPGA configuration technology. However, after configuration, all configuration information will be lost when power is turned off and restarted. External non-volatile memory, such as Flash or EEPROM, is required to store configuration information. However, the configuration information in external memory is very likely to be stolen, which reduces its security.

[0005] FPGAs based on non-volatile memory cell technology do not require external non-volatile memory. Configuration information is stored in the internal FPGA configuration memory array, and the configuration information is not lost after power failure and restart. Flash FPGAs are a typical type of non-volatile FPGA, possessing the reprogrammable characteristics of SRAM FPGAs. Furthermore, the Flash switching structure significantly reduces the number of transistors in Flash FPGAs, thus lowering static power consumption. However, Flash FPGAs have certain limitations. The number of erase / write cycles for Flash FPGA memory cells is limited, only around a few hundred times. Secondly, compared to SRAM FPGAs, Flash FPGAs use more advanced manufacturing processes, and their device size and density are much lower. Summary of the Invention

[0006] The purpose of this invention is to provide a self-loading memory unit and memory array based on non-volatile memory units. This invention can ensure that the data configured in the configuration memory array circuit will not be lost after the FPGA is powered off. Compared with traditional SRAM-type FPGAs, it does not need to read data from the external configuration memory to run when powered on, resulting in faster startup speed and greater flexibility.

[0007] To address the aforementioned technical problems, this invention provides a self-loading memory unit based on non-volatile memory cells, comprising: An SRAM cell structure for loading configuration data stored in the non-volatile memory structure includes: a first transfer MOS transistor, a second transfer MOS transistor, a cross-coupled inverter structure, and a first balanced MOS transistor; the two ends of the cross-coupled inverter structure form a first memory node and a second memory node, respectively; the source terminals of the first transfer MOS transistor and the second transfer MOS transistor are respectively connected to the first bit line BL and the second bit line BLB; the drain terminals of the first transfer MOS transistor and the second transfer MOS transistor are respectively connected to the first memory node and the second memory node; the gate terminals of the first transfer MOS transistor and the second transfer MOS transistor are connected to the same word line WL; the gate terminal of the first balanced MOS transistor is connected to the balanced signal line EQ, and the source and drain terminals of the first balanced MOS transistor are respectively connected to the first memory node and the second memory node; A non-volatile memory structure for storing configuration data includes: a third transmission MOSFET, a fourth transmission MOSFET, a fifth transmission MOSFET, a sixth transmission MOSFET, a first non-volatile memory cell, a second non-volatile memory cell, and a first switching MOSFET. The source terminals of the third and fifth transmission MOSFETs are connected to the first bit line BL, and the drain terminals of the third and fifth transmission MOSFETs are connected to the first transmission node at one end of the first non-volatile memory cell. The source terminals of the fourth and sixth transmission MOSFETs are connected to the second bit line BLB. The drain terminals of the S-channel MOSFET and the sixth transmission MOSFET are connected to the second transmission node at one end of the second non-volatile memory cell; the gate terminals of the third transmission MOSFET and the fifth transmission MOSFET are connected to the first switch signal line ST_RS; the gate terminals of the fifth transmission MOSFET and the sixth transmission MOSFET are connected to the second switch signal line ST_RS_N; the gate terminal of the first switch MOSFET is connected to the reset signal line RS, the source terminal of the first switch MOSFET is connected to the source line SL, and the drain terminal of the first switch MOSFET is connected to the third transmission node at the other end of the first non-volatile memory cell and the second non-volatile memory cell.

[0008] Preferably, the cross-coupled inverter structure includes: a first load MOSFET, a second load MOSFET, a first driver MOSFET, and a second driver MOSFET; the source terminal of the first load MOSFET is connected to a power supply, the drain terminal of the first load MOSFET is connected to a first memory node, and the gate terminal of the first load MOSFET is connected to a second memory node; the source terminal of the second load MOSFET is connected to a power supply, the drain terminal of the second load MOSFET is connected to a second memory node, and the gate terminal of the second load MOSFET is connected to the first memory node; the source terminal of the first driver MOSFET is grounded, the drain terminal of the first driver MOSFET is connected to the first memory node, and the gate terminal of the first driver MOSFET is connected to the second memory node; the source terminal of the second driver MOSFET is grounded, the drain terminal of the second driver MOSFET is connected to the second memory node, and the gate terminal of the second driver MOSFET is connected to the first memory node.

[0009] Preferably, it further includes a first non-volatile memory cell programming path and a second non-volatile memory cell programming path; the first non-volatile memory cell programming path is composed of a first bit line BL, a source line SL, a third transmission MOSFET, a fifth transmission MOSFET, and a first switching MOSFET; the second non-volatile memory cell programming path is composed of a second bit line BLB, a source line SL, a fourth transmission MOSFET, a sixth transmission MOSFET, and a first switching MOSFET.

[0010] Preferably, it also includes a self-loading timing sequence, which includes three states: power-on, pre-charge, and loading; used to load the configuration data in the first non-volatile memory unit and the second non-volatile memory unit onto the first storage node and the second storage node in the SRAM cell structure.

[0011] Preferably, it also includes a reset and programming timing sequence, which includes five states: power-on, reset, encoding "1", secondary reset, and encoding "0".

[0012] The present invention also provides a self-loading memory array based on non-volatile memory cells, comprising: An N-row, N-column self-loading memory cell based on non-volatile memory cells as described above; the self-loading memory cell is a sub-cell of the self-loading memory array; the self-loading memory cells in the same column share the same source line SL, the same first bit line BL, and the same second bit line BLB; the self-loading memory cells in the same row share the same word line WL, the same balance signal line EQ, the same reset signal line RS, and the same first switch signal line ST_RS and second switch signal line ST_RS_N; N peripheral circuits, wherein the i-th peripheral circuit has a first terminal connected to the i-th row input address line A[i], a second terminal connected to the input word line WL_IN, a third terminal connected to the input balanced signal line EQ_IN, a fourth terminal connected to the input reset signal line RS_IN, a fifth and a sixth terminal connected to the first input switch signal line ST_RS_IN and the second input switch signal line ST_RS_N_IN, a seventh terminal connected to the i-th row word line WL, an eighth terminal connected to the i-th row balanced signal line EQ, a ninth terminal connected to the i-th row reset signal line RS, and a tenth and an eleventh terminal connected to the i-th row first switch signal line ST_RS and the second switch signal line ST_RS_N; wherein 1≤i≤N.

[0013] Preferably, the peripheral circuit includes five logic gates and AND gates; wherein the first input terminal of the first AND gate is connected to the input address line A[i], the second input terminal is connected to the input word line WL_IN, and the output terminal is connected to the word line WL; the first input terminal of the second AND gate is connected to the input address line A[i], the second input terminal is connected to the input balanced signal line EQ_IN, and the output terminal is connected to the balanced signal line EQ; the first input terminal of the third AND gate is connected to the input address line A[i], the second input terminal is connected to the input reset signal line RS_IN, and the output terminal is connected to the reset signal line RS; the first input terminal of the fourth AND gate X4 is connected to the input address line A[i], the second input terminal is connected to the first input switch signal line ST_RS_IN, and the output terminal is connected to the first switch signal line ST_RS; the first input terminal of the fifth AND gate is connected to the input address line A[i], the second input terminal is connected to the second input switch signal line ST_RS_N_IN, and the output terminal is connected to the second switch signal line ST_RS_N.

[0014] Preferably, the method further includes: under the control of N rows of RS, ST_RS and ST_RS_N signals, 1-bit data in N rows and N columns is used to reset and program the configuration storage unit in N rows and N columns through N columns of BL, BLB and SL signals; and under the control of N rows of WL, EQ, RS, ST_RS and ST_RS_N signals, data loading operation is performed on the self-loading storage array.

[0015] This invention also provides a method for resetting and programming a self-loading memory array, employing a self-loading memory array based on non-volatile memory cells as described above, comprising: When powered on, the source line SL is at a low level, the first bit line BL is at a low level, and the second bit line BLB is at a low level. During reset, the source line SL is high, the first bit line BL is low, the second bit line BLB is low, the input reset signal line RS_IN is high, the first input switch signal line ST_RS_IN is low, and the second input switch signal line ST_RS_N_IN is high. When the voltage of the source line SL is higher than the threshold voltage of the non-volatile memory cell in the configuration memory array, the first non-volatile memory cell and the second non-volatile memory cell are reset from the "low" impedance state to the "high" impedance state. When encoding "1", the second bit line BLB is high, the first bit line BL is low, and the source line SL is low. When the voltage of the second bit line BLB is higher than the threshold voltage of the non-volatile memory cell in the configuration memory array, the second non-volatile memory cell is programmed from a "high" impedance state to a "low" impedance state. At the same time, since the first bit line BL is low, the first non-volatile memory cell remains in a "high" impedance state. During a secondary reset, the source line SL is high, the first bit line BL is low, the second bit line BLB is low, the input reset signal line RS_IN is high, the first input switch signal line ST_RS_IN is low, and the second input switch signal line ST_RS_N_IN is high. When the voltage of the source line SL is higher than the threshold voltage of the non-volatile memory cell in the configuration memory array, the first non-volatile memory cell and the second non-volatile memory cell are reset from a "low" impedance state to a "high" impedance state. When encoding "0", the first bit line BL is high, the second bit line BLB is low, and the source line SL is low. When the voltage of the first bit line BL is higher than the threshold voltage of the non-volatile memory cell in the configuration memory array, the first non-volatile memory cell is programmed from a "high" impedance state to a "low" impedance state. At the same time, since the second bit line BLB is low, the second non-volatile memory cell remains in a "high" impedance state.

[0016] This invention also provides a self-loading method for a self-loading memory array, employing a self-loading memory array based on non-volatile memory cells as described above, comprising: When powered on, the source line SL is at a low level, the first bit line BL is at a low level, and the second bit line BLB is at a low level. During pre-charging, the first bit line BL and the second bit line BLB are both kept at half power supply level. At this time, the input balance signal line EQ_IN is high, so that the first storage node and the second storage node are at the same potential. During loading, the source line SL is low, the balance signal line EQ_IN is low, the first input switch signal line ST_RS_IN is low, the second input switch signal line ST_RS_N_IN is high, and the input reset signal line RS_IN is high. One end of each of the two first and second non-volatile memory cells is connected to the source line SL. Since the resistance values ​​of the two first and second non-volatile memory cells are different, their pull-down capabilities for the voltages of the first and second memory nodes are also different; the side with the lower resistance will experience a faster voltage drop than the other side. When a sufficient voltage difference is generated between the first bit line BL and the second bit line BLB, the input balance signal line EQ_IN is pulled high, connecting the balanced memory node to the first bit line BL and the second bit line BLB. Due to the cross-coupled inverter structure in the SRAM cell structure, the memory node with the lower resistance will be pulled down to 0, while the side with the higher resistance will be driven high. The data in the first and second non-volatile memory cells is loaded into the first and second memory nodes in the SRAM cell structure.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention uses a non-volatile memory cell group as a programming device, which can ensure that the data configured in the non-volatile memory cell group will not be lost after the FPGA is powered off.

[0018] 2. Compared with traditional SRAM-type FPGAs, this invention does not require reading data from an external configuration memory to run upon power-up, resulting in faster startup speed and higher data reliability and confidentiality.

[0019] 3. Compared with Flash-type FPGAs, this invention has a higher number of erase / write cycles based on the characteristics of non-volatile memory cells, and the device size and density can be increased.

[0020] 4. Compared with antifuse FPGA, this invention has greater flexibility, can achieve a larger device size, and can be refreshed periodically. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a self-loading storage array based on non-volatile memory cells provided by the present invention.

[0022] Figure 2 This is a schematic diagram of a self-loading memory unit based on a non-volatile memory unit provided by the present invention.

[0023] Figure 3 This is a schematic diagram of a peripheral circuit structure provided by the present invention.

[0024] Figure 4This is a schematic diagram of a programming operation method for a self-loading memory array based on non-volatile memory cells provided by the present invention.

[0025] Figure 5 This is a schematic diagram of a loading operation mode of a self-loading memory array based on non-volatile memory cells provided by the present invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Example 1

[0027] This invention provides a schematic diagram of a self-loading memory array based on non-volatile memory cells, the implementation structure of which is as follows: Figure 1 As shown, it includes a self-loading storage unit with N rows and N columns and N peripheral circuit structures.

[0028] The aforementioned N rows and N columns of self-loading memory units share the same source line SL, the same first bit line BL, and the same second bit line BLB. Self-loading memory units in the same row share the same word line WL, the same balanced signal line EQ, the same reset signal line RS, and the same first switch signal line ST_RS and second switch signal line ST_RS_N. Under the control of the N rows of RS, ST_RS, and ST_RS_N signals, 1-bit data from the N rows and N columns resets and programs the N rows and N columns of configuration memory units via the N columns of BL, BLB, and SL. Under the control of the N rows of WL, EQ, RS, ST_RS, and ST_RS_N signals, data loading operations can be performed on the self-loading memory units. The N peripheral circuits, wherein the i-th peripheral circuit has a first terminal connected to the i-th row input address line A[i], a second terminal connected to the input word line WL_IN, a third terminal connected to the input balance signal line EQ_IN, a fourth terminal connected to the input reset signal line RS_IN, a fifth and a sixth terminal connected to the first input switch signal line ST_RS_IN and the second input switch signal line ST_RS_N_IN, a seventh terminal connected to the i-th row word line WL, an eighth terminal connected to the i-th row balance signal line EQ, a ninth terminal connected to the i-th row reset signal line RS, and a tenth and an eleventh terminal connected to the i-th row first switch signal line ST_RS and the second switch signal line ST_RS_N, where 1≤i≤N. Example 2

[0029] This invention provides a self-loading memory cell structure based on non-volatile memory cells, the implementation of which is as follows: Figure 2 As shown, it includes SRAM cell structure and non-volatile memory structure.

[0030] The SRAM cell structure includes two transmission transistors, two load transistors, two driver transistors, and one balancing transistor. The two transmission transistors are a first transmission MOSFET N1 and a second transmission MOSFET N2; the two load transistors are a first load MOSFET P1 and a second load MOSFET P2; the two driver transistors are a first driver MOSFET N3 and a second driver MOSFET N4; and the one balancing transistor is a first balancing MOSFET N5. The first load MOSFET P1, the first driver MOSFET N3, the second load MOSFET P2, and the second driver MOSFET N4 form a cross-coupled inverter structure, forming a first memory node Q and a second memory node QN. The source of the first transmission MOSFET N1 is connected to the first bit line BL, the drain is connected to the first memory node Q, and the gate is connected to the word line WL. The source of the second transmission MOSFET N2 is connected to the second bit line BLB, the drain is connected to the second memory node QN, and the gate is connected to the word line WL. The source of the first load MOSFET P1 is connected to the power supply, the drain is connected to the first memory node Q, and the gate is connected to the second memory node QN. The source of the second load MOSFET P2 is connected to the power supply, the drain is connected to the second memory node QN, and the gate is connected to the first memory node Q. The source of the first driver MOSFET N3 is grounded, the drain is connected to the first memory node Q, and the gate is connected to the second memory node QN. The source of the second driver MOSFET N4 is grounded, the drain is connected to the second memory node QN, and the gate is connected to the first memory node Q. The source of the first balancing MOSFET N5 is connected to the first memory node Q, the drain is connected to the second memory node QN, and the gate is connected to the balancing signal line EQ.

[0031] The non-volatile memory structure includes four transmission transistors, two non-volatile memory cells, and one switching transistor; wherein the four transmission transistors are the third transmission MOSFET P3, the fourth transmission MOSFET P4, the fifth transmission MOSFET N6, and the sixth transmission MOSFET N7, the two non-volatile memory cells are the first non-volatile memory cell M1 and the second non-volatile memory cell M2, and the one switching transistor is the first switching MOSFET N8. The source of the third transmission MOSFET P3 is connected to the first bit line BL, the drain is connected to the first transmission node T1, and the gate is connected to the first switch signal ST_RS; the source of the fourth transmission MOSFET P4 is connected to the second bit line BLB, the drain is connected to the second transmission node T2, and the gate is connected to the first switch signal ST_RS; the source of the fifth transmission MOSFET N6 is connected to the first bit line BL, the drain is connected to the first transmission node T1, and the gate is connected to the second switch signal ST_RS_N; the source of the sixth transmission MOSFET N7 is connected to the second bit line BLB, the drain is connected to the second transmission node T2, and the gate is connected to the first switch signal ST_RS; one side of the first non-volatile memory cell M1 is connected to the first transmission node T1, and the other side is connected to the third transmission node T3; one side of the second non-volatile memory cell M2 is connected to the second transmission node T2, and the other side is connected to the third transmission node T3; the source of the first switch MOSFET N8 is connected to the source line SL, the drain is connected to the third transmission node T3, and the gate is connected to the reset signal line RS. Example 3

[0032] In this example, the peripheral circuit structure includes five AND gates; the first AND gate X1 has its first input connected to the input address line A[i], its second input connected to the input word line WL_IN, and its output connected to the word line WL; the second AND gate X2 has its first input connected to the input address line A[i], its second input connected to the input balanced signal line EQ_IN, and its output connected to the balanced signal line EQ; the third AND gate X3 has its first input connected to the input address line A[i], its second input connected to the input reset signal line RS_IN, and its output connected to the reset signal line RS; the fourth AND gate X4 has its first input connected to the input address line A[i], its second input connected to the first input switch signal line ST_RS_IN, and its output connected to the first switch signal line ST_RS; the fifth AND gate X5 has its first input connected to the input address line A[i], its second input connected to the second input switch signal line ST_RS_N_IN, and its output connected to the second switch signal line ST_RS_N. Example 4

[0033] This example provides a reset and programming timing diagram for a self-loading memory array based on non-volatile memory cells. The reset and programming timing diagram includes five states: power-on, reset, encoding "1", secondary reset, and encoding "0". When powered on, the source line SL is at a low level, the first bit line BL is at a low level, and the second bit line BLB is at a low level. During reset, the source line SL is high, the first bit line BL is low, the second bit line BLB is low, the input reset signal line RS_IN is high, the first input switch signal line ST_RS_IN is low, and the second input switch signal line ST_RS_N_IN is high. When the voltage of the source line SL is higher than the threshold voltage of the non-volatile memory cell in the configuration memory cell array, the non-volatile memory cell is reset from a "low" impedance state to a "high" impedance state. When encoding "1", the second bit line BLB is high, the first bit line BL is low, and the source line SL is low. When the voltage of the second bit line BLB is higher than the threshold voltage of the non-volatile memory cell in the configuration memory cell array, the second non-volatile memory cell is programmed from a "high" impedance state to a "low" impedance state. At the same time, since the first bit line BL is low, the first non-volatile memory cell remains in a "high" impedance state. During a secondary reset, the source line SL is high, the first bit line BL is low, the second bit line BLB is low, the input reset signal line RS_IN is high, the first input switch signal line ST_RS_IN is low, and the second input switch signal line ST_RS_N_IN is high. When the voltage of the source line SL is higher than the threshold voltage of the non-volatile memory cell in the configuration memory cell array, the non-volatile memory cell is reset from a "low" impedance state to a "high" impedance state. When encoding "0", the first bit line BL is high, the second bit line BLB is low, and the source line SL is low. When the voltage of the first bit line BL is higher than the threshold voltage of the non-volatile memory cell in the configuration memory cell array, the first non-volatile memory cell is programmed from a "high" impedance state to a "low" impedance state. At the same time, since the second bit line BLB is low, the second non-volatile memory cell remains in a "high" impedance state. Example 5

[0034] In this example, a self-loading timing sequence for a self-loading memory array based on non-volatile memory cells is provided. The self-loading timing sequence loads data from the non-volatile memory cells into the SRAM cells. The self-loading timing sequence includes three states: power-on, pre-charge, and loading. When powered on, the source line SL is at a low level, the first bit line BL is at a low level, and the second bit line BLB is at a low level. During pre-charging, both the first bit line BL and the second bit line BLB are kept at VDD / 2 level. At this time, the input balance signal line EQ_IN is high level, so that the first storage node Q and the second storage node QN are at the same potential. During loading, the source line SL is low, the balance signal line EQ_IN is low, the first input switch signal line ST_RS_IN is low, the second input switch signal line ST_RS_N_IN is high, and the input reset signal line RS_IN is high. Two non-volatile memory cells are connected at one end to the source line SL. Since the two non-volatile memory cells have different resistance values, their pull-down capabilities for the first and second memory nodes also differ; the side with the lower resistance will experience a faster voltage drop than the other side. When a sufficient voltage difference is generated between the first bit line BL and the second bit line BLB, the input balance signal line EQ_IN is pulled high, connecting the balanced memory node to the first bit line BL and the second bit line BLB. Due to the cross-coupled inverter structure in the SRAM cell structure, the memory node with the lower resistance is pulled down to 0, while the side with the higher resistance is driven high, loading the data from the non-volatile memory cells into the memory nodes in the SRAM cell structure.

[0035] As a preferred embodiment, the self-loading timing includes three states: power-on, pre-charge, and loading, which loads the data in the non-volatile memory cell into the storage node in the SRAM cell.

[0036] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A self-loading memory cell based on a non-volatile memory cell, characterized in that, The application relates to a non-volatile memory structure and a SRAM unit structure. The SRAM unit structure is used for loading configuration data stored in the non-volatile memory structure and comprises a first transfer MOS tube, a second transfer MOS tube, a cross-coupled inverter structure and a first balance MOS tube; the cross-coupled inverter structure forms a first storage node and a second storage node at two ends respectively; the source ends of the first transfer MOS tube and the second transfer MOS tube are connected with a first bit line BL and a second bit line BLB respectively; the drain ends of the first transfer MOS tube and the second transfer MOS tube are connected with the first storage node and the second storage node respectively; the gate ends of the first transfer MOS tube and the second transfer MOS tube are connected with the same word line WL; the gate end of the first balance MOS tube is connected with an equalization signal line EQ, and the source end and the drain end of the first balance MOS tube are connected with the first storage node and the second storage node respectively. The non-volatile memory structure is used for storing configuration data and comprises a third transfer MOS tube, a fourth transfer MOS tube, a fifth transfer MOS tube, a sixth transfer MOS tube, a first non-volatile memory unit, a second non-volatile memory unit and a first switch MOS tube; the source ends of the third transfer MOS tube and the fifth transfer MOS tube are connected with the first bit line BL, and the drain ends of the third transfer MOS tube and the fifth transfer MOS tube are connected with a first transfer node at one end of the first non-volatile memory unit; the source ends of the fourth transfer MOS tube and the sixth transfer MOS tube are connected with the second bit line BLB, and the drain ends of the fourth transfer MOS tube and the sixth transfer MOS tube are connected with a second transfer node at one end of the second non-volatile memory unit; the gate ends of the third transfer MOS tube and the fifth transfer MOS tube are connected with a first switch signal line ST_RS; the gate ends of the fifth transfer MOS tube and the sixth transfer MOS tube are connected with a second switch signal line ST_RS_N; the gate end of the first switch MOS tube is connected with a reset signal line RS, the source end of the first switch MOS tube is connected with a source line SL, and the drain end of the first switch MOS tube is connected with a third transfer node at the other end of the first non-volatile memory unit and the second non-volatile memory unit.

2. A self-loading memory cell based on a non-volatile memory cell as claimed in claim 1, characterized in that, The cross-coupled inverter structure comprises a first load MOS tube, a second load MOS tube, a first drive MOS tube and a second drive MOS tube; the source end of the first load MOS tube is connected with a power supply, the drain end of the first load MOS tube is connected with the first storage node, and the gate end of the first load MOS tube is connected with the second storage node; the source end of the second load MOS tube is connected with the power supply, the drain end of the second load MOS tube is connected with the second storage node, and the gate end of the second load MOS tube is connected with the first storage node; the source end of the first drive MOS tube is grounded, the drain end of the first drive MOS tube is connected with the first storage node, and the gate end of the first drive MOS tube is connected with the second storage node; the source end of the second drive MOS tube is grounded, the drain end of the second drive MOS tube is connected with the second storage node, and the gate end of the second drive MOS tube is connected with the first storage node.

3. A self-loading memory cell based on a non-volatile memory cell as claimed in claim 1, characterized in that, The first nonvolatile memory cell programming path is composed of a first bit line BL, a source line SL, a third transfer MOS transistor, a fifth transfer MOS transistor and a first switch MOS transistor; and the second nonvolatile memory cell programming path is composed of a second bit line BLB, the source line SL, a fourth transfer MOS transistor, a sixth transfer MOS transistor and the first switch MOS transistor.

4. A self-loading memory cell based on a non-volatile memory cell as claimed in claim 1, characterized in that, The self-loading timing sequence comprises: power-on, pre-charge and loading three states; and loading configuration data in the first nonvolatile memory cell and the second nonvolatile memory cell onto the first storage node and the second storage node in the SRAM cell structure.

5. A self-loading memory cell based on a non-volatile memory cell as claimed in claim 1, wherein, The reset and programming timing sequence comprises: power-on, reset, programming "1", secondary reset and programming "0" five states.

6. A self-loading memory array based on non-volatile memory cells, characterized in that, The self-loading memory cell comprises: N rows and N columns of self-loading memory cells based on the nonvolatile memory cell according to any one of claims 1-5; The self-loading memory cell is a subunit of the self-loading memory array; self-loading memory cells in the same column share the same source line SL, the same first bit line BL and the same second bit line BLB; and self-loading memory cells in the same row share the same word line WL, the same balance signal line EQ, the same reset signal line RS, the same first switch signal line ST_RS and the same second switch signal line ST_RS_N; N peripheral circuits, wherein the i-th peripheral circuit is provided with a first end connected with the i-th row of input address line A[i], a second end connected with the input word line WL_IN, a third end connected with the input balance signal line EQ_IN, a fourth end connected with the input reset signal line RS_IN, a fifth end and a sixth end connected with the first input switch signal line ST_RS_IN and the second input switch signal line ST_RS_N_IN, a seventh end connected with the i-th row of word line WL, an eighth end connected with the i-th row of balance signal line EQ, a ninth end connected with the i-th row of reset signal line RS, a tenth end and an eleventh end connected with the i-th row of first switch signal line ST_RS and the second switch signal line ST_RS_N; wherein 1≤i≤N.

7. A self-loading memory array based on nonvolatile memory cells as recited in claim 6, wherein, The peripheral circuit includes five logic gates and gates; wherein the first input end of the first gate is connected with the input address line A[i], the second input end is connected with the input word line WL_IN, and the output end is connected with the word line WL; the first input end of the second gate is connected with the input address line A[i], the second input end is connected with the input balance signal line EQ_IN, and the output end is connected with the balance signal line EQ; the first input end of the third gate is connected with the input address line A[i], the second input end is connected with the input reset signal line RS_IN, and the output end is connected with the reset signal line RS; the first input end of the fourth gate X4 is connected with the input address line A[i], the second input end is connected with the first input switch signal line ST_RS_IN, and the output end is connected with the first switch signal line ST_RS; the first input end of the fifth gate is connected with the input address line A[i], the second input end is connected with the second input switch signal line ST_RS_N_IN, and the output end is connected with the second switch signal line ST_RS_N.

8. A self-loading memory array based on nonvolatile memory cells as recited in claim 6, wherein, Further comprising: Under the control of N rows of RS, ST_RS and ST_RS_N signals, 1-bit data of N rows and N columns is reset and programmed to the N rows and N columns of configuration storage units through N columns of BL, BLB and SL signals; Under the control of N rows of WL, EQ, RS, ST_RS and ST_RS_N signals, the self-loading storage array is loaded with data.

9. A method for resetting and programming a self-loading memory array, using a nonvolatile memory cell based self-loading memory array as claimed in claim 6, wherein, Comprising: When powered on, the source line SL is low, the first bit line BL is low, and the second bit line BLB is low; When reset, the source line SL is high, the first bit line BL is low, the second bit line BLB is low, the input reset signal line RS_IN is high, the first input switch signal line ST_RS_IN is low, and the second input switch signal line ST_RS_N_IN is high; when the voltage of the source line SL is higher than the threshold voltage of the non-volatile storage unit in the configuration storage array, the first non-volatile storage unit and the second non-volatile storage unit are reset from the "low" resistance state to the "high" resistance state; When "1" is programmed, the second bit line BLB is high, the first bit line BL is low, and the source line SL is low; when the voltage of the second bit line BLB is higher than the threshold voltage of the non-volatile storage unit in the configuration storage array, the second non-volatile storage unit is programmed from the "high" resistance state to the "low" resistance state, and at the same time, due to the low level of the first bit line BL, the first non-volatile storage unit remains unchanged in the "high" resistance state; When reset, the source line SL is high, the first bit line BL is low, the second bit line BLB is low, the input reset signal line RS_IN is high, the first input switch signal line ST_RS_IN is low, and the second input switch signal line ST_RS_N_IN is high; when the voltage of the source line SL is higher than the threshold voltage of the non-volatile storage unit in the configuration storage array, the first non-volatile storage unit and the second non-volatile storage unit are reset from the "low" resistance state to the "high" resistance state; When "0" is programmed, the first bit line BL is high, the second bit line BLB is low, and the source line SL is low; when the voltage of the first bit line BL is higher than the threshold voltage of the nonvolatile memory cell in the configuration memory array, the first nonvolatile memory cell is programmed from the "high" resistance state to the "low" resistance state, and the second nonvolatile memory cell remains in the "high" resistance state due to the low voltage of the second bit line BLB.

10. A self-loading method of a self-loading memory array using a nonvolatile memory cell based self-loading memory array as claimed in claim 6, wherein, The application comprises: When powered on, the source line SL is low, the first bit line BL is low, and the second bit line BLB is low. When pre-charged, the first bit line BL and the second bit line BLB are both kept at half of the power supply voltage, at this time, the input balance signal line EQ_IN is high, so that the first storage node and the second storage node are at the same potential. When loaded, the source line SL is low, the balance signal line EQ_IN is low, the first input switch signal line ST_RS_IN is low, the second input switch signal line ST_RS_N_IN is high, and the input reset signal line RS_IN is high, so that one end of the two first nonvolatile memory cells and the second nonvolatile memory cell is connected to the source line SL, the resistance values of the two first nonvolatile memory cells and the second nonvolatile memory cell are different, and the voltage pull-down capabilities of the first storage node and the second storage node are also different, and the side with the lower resistance value will have a faster voltage drop than the other side; when the first bit line BL and the second bit line BLB generate a sufficient voltage difference, the input balance signal line EQ_IN is pulled up to connect the balanced storage node to the first bit line BL and the second bit line BLB; due to the cross-coupled inverter structure in the SRAM cell structure, the storage node with the lower resistance value will be pulled down to 0, and the other side with the higher resistance value will be driven to a high level, and the data in the first nonvolatile memory cell and the second nonvolatile memory cell is loaded into the first storage node and the second storage node in the SRAM cell structure.

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